EE247 Lecture 17. EECS 247 Lecture 17: Data Converters- ADC Design, Sampling 2009 Page 1. Practical Sampling Summary So Far! v IN

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1 EE247 Lecure 17 ADC Converers Sampling (coninued) Sampling swich consideraions Clock volage boosers Sampling swich charge injecion & clock feedhrough Complemenary swich Use of dummy device Boom-plae swiching Track & hold T/H circuis T/H combined wih summing/difference funcion T/H circui incorporaing gain & offse cancellaion EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 1 kt/c noise 2 C 12kBT VFS 0.72 R << B fc s 2B Finie R sw limied bandwidh g sw = f (n ) disorion 2 Pracical Sampling Summary So Far! v IN M1 v OUT C Vin W gon = go 1 for go μcox ( VDD Vh ) VDD V = h L Allowing long enough seling ime reduce disorion due o sw non-linear behavior EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 2

Signal Disorion Due o Sampling Swich Nonlineariy SFDR sensiive o sampling disorion - improve lineariy by: Larger V DD /V FS Higher sampling bandwidh Soluions: Overdesign Larger swiches Issue:

2 Signal Disorion Due o Sampling Swich Nonlineariy SFDR sensiive o sampling disorion - improve lineariy by: Larger V DD /V FS Higher sampling bandwidh Soluions: Overdesign Larger swiches Issue: Increased swich charge injecion Increased nonlinear S &D juncion cap. Maximize V DD /V FS Decreased dynamic range if V DD cons. Complemenary swich? Consan & max. S f(n )? 10bi ADC T s /τ = 20 V DD V h = 2V V FS = 1V EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 3 Sampling Use of Complemenary Swiches g o g n o g o T =g on + g o p B g o p B Complemenary n & p swich advanages: Increase in he overall conducance lower ime consan Linearize he swich conducance for he range V hp < Vin < Vdd - V hn EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 4

Complemenary Swich Issues Supply Volage Evoluion Supply volage has scaled down wih echnology scaling Threshold volages do no scale accordingly Ref: A.

EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 5 Complemenary Swich Effec of Supply Volage Scaling g effecive g o n g o T =go n + g o p

3 Complemenary Swich Issues Supply Volage Evoluion Supply volage has scaled down wih echnology scaling Threshold volages do no scale accordingly Ref: A. Abo e al, A 1.5-V, 10-bi, 14.3-MS/s CMOS Pipeline Analog-o-Digial Converer, JSSC May 1999, pp EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 5 Complemenary Swich Effec of Supply Volage Scaling g effecive g o n g o T =go n + g o p g o p B B As supply volage scales down inpu volage range for consan g o shrinks Complemenary swich no effecive when V DD becomes comparable o 2xV h EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 6

4 Boosed & Consan S Sampling S =cons. OFF ON Gae volage S =low Device off Beware of signal feedhrough due o parasiic capaciors Increase gae overdrive volage as much as possible + keep S consan Swich overdrive volage independen of signal level Error due o finie R ON linear (o 1s order) Lower R on lower ime consan EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 7 Consan S Sampling (= he swich inpu erminal) EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 8

5 Consan S Sampling Circui VDD=3V P_N M1 M2 M3 M8 M6 VP1 100ns P C1 PB C2 C3 M12 P M4 M5 M9 VS1 1.5V 1MHz Va Vg M11 Vb Chold This Example: All device sizes:w/l=10μ/0.35μ All capacior size: 1pF (excep for Chold) Noe: Each criical swich requires a separae clock booser Sampling swich & C Ref: A. Abo e al, A 1.5-V, 10-bi, 14.3-MS/s CMOS Pipeline Analog-o-Digial Converer, JSSC May 1999, pp EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 9 VDD=0 3V M1 0ff C1 PB 0 3V Clock Volage Doubler C2 M2 Sauraion mode 0 3V 0 (3V-V h M2 ) 0 0 M1 Triode VDD=3V M2 off 3V 0 3V (3V-V M2 h ) (6V-V M2 h ) Acquire charge C1 C2 PB 3V 0 0 3V P P VP1 =clock 0 3V VP1 3V 0 a) Sar up b) Nex clock phase EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 10

6 Clock Volage Doubler M1 0ff 3V ~6V VDD=3V C1 PB 0 3V P VP1 M2 0 3V (6V-V M2 h ) (3V-V M2 h ) ~ 3V Acquires C2 charge 3V 0 M2 Triode Boh C1 & C2 charged o VDD afer 1.5 clock cycle Noe ha boom plae of C1 & C2 is eiher 0 or VDD while op plaes are a VDD or 2VDD c) Nex clock phase EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 11 Clock Volage Doubler VDD=3V 2VDD M1 M2 P_Boos R1 C1 PB C2 R2 VDD P 0 VP1 Clock period: 100ns *R1 & R2=1GOhm dummy resisors added for simulaion only EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 12

7 Consan S Sampler: Φ Low VDD=3V ~ 2 VDD (boosed clock) M3 Triode OFF VDD C3 M4 Sampling swich M11 is OFF VDD M12 Triode Inpu volage source OFF M11 OFF VS1 1.5V 1MHz Chold 1pF Device OFF C3 charged o ~VDD EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 13 Consan S Sampler: Φ High VDD C3 1pF M8 C3 previously charged o VDD M8 & M9 are on: C3 across G-S of M11 M9 VS1 1.5V 1MHz M11 Chold M11 on wih consan VGS = VDD Mission accomplished!? EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 14

8 Consan S Sampling Inpu Swich ae Chold Signal Inpu Signal EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 15 Consan S Sampling? EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 16

9 Consan S Sampling? During he ime period: n < V ou S =consan=v DD Larger S -V h compared o no boos S =ce and no a funcion of inpu volage Significan lineariy improvemen IR During he ime period: n >V ou : S = V DD -IR Larger S -V h compared o no boos S is a funcion of IR and hence inpu volage Lineariy improvemen no as pronounced as for n < V ou EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 17 Clock Muliplier M7 & M13 for reliabiliy Remaining issues: -S consan only for n <V ou Boosed Clock Sampling Complee Circui -Nonlineariy due o Vh dependence of M11on bodysource volage Swich Ref: A. Abo e al, A 1.5-V, 10-bi, 14.3-MS/s CMOS Pipeline Analog-o-Digial Converer, JSSC May 1999, pp EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 18

10 Boosed Clock Sampling Design Consideraion Choice of value for C3: C3 oo large large charging curren large dynamic power dissipaion VDD C3 M8 C3 oo small Vgae-Vs= VDD.C3/(C3+Cx) Loss of VGS due o low raio of Cx/C3 Cx includes C GS of M11 plus all oher parasiics caps. M9 Cx Vin M11 Chold Ref: A. Abo e al, A 1.5-V, 10-bi, 14.3-MS/s CMOS Pipeline Analog-o-Digial Converer, JSSC May 1999, pp EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 19 Advanced Clock Boosing Technique Ref: M. Walari e al., "A self-calibraed pipeline ADC wih 200MHz IFsampling fronend," ISSCC 2002, Dig. Tech. Papers, pp. 314 Sampling Swich Two floaing volages sources generaed and conneced o Gae and S & D EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 20

11 Advanced Clock Boosing Technique clk low Sampling Swich clk low Capaciors C1a & C1b charged o VDD MS off Hold mode EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 21 Advanced Clock Boosing Technique clk high Sampling Swich clk high Top plae of C1a & C1b conneced o gae of sampling swich Boom plae of C1a conneced o V IN Boom plae of C1b conneced o V OUT VGS & VGD of MS VDD & ac signal on G of MS average of V IN & V OUT EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 22

12 Advanced Clock Boosing Technique Ref: M. Walari e al., "A self-calibraed pipeline ADC wih 200MHz IFsampling fronend," ISSCC 2002, Dig. Tech. Papers, pp. 314 Sampling Swich Gae racks average of inpu and oupu, reduces effec of I R drop a high frequencies Bulk also racks signal reduced body effec (echnology used allows connecing bulk o S) Repored measured SFDR = 76.5dB a f in =200MHz EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 23 Consan Conducance Swich Ref: H. Pan e al., "A 3.3-V 12-b 50-MS/s A/D converer in 0.6um CMOS wih over 80-dB SFDR," IEEE J. Solid-Sae Circuis, pp , Dec EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 24

13 Consan Conducance Swich OFF Ref: H. Pan e al., "A 3.3-V 12-b 50-MS/s A/D converer in 0.6um CMOS wih over 80-dB SFDR," IEEE J. Solid-Sae Circuis, pp , Dec EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 25 Consan Conducance Swich M2 Consan curren consan g ds ON M1 replica of M2 & same VGS as M2 M1 also consan g ds Noe: Auhors repor requiremen of 280MHz GBW for he opamp for 12bi 50Ms/s ADC Also, opamp common-mode compliance for full inpu range required Ref: H. Pan e al., "A 3.3-V 12-b 50-MS/s A/D converer in 0.6um CMOS wih over 80-dB SFDR," IEEE J. Solid-Sae Circuis, pp , Dec EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 26

14 Swich Off-Mode Feedhrough Cancellaion Ref: M. Walari e al., "A self-calibraed pipeline ADC wih 200MHz IF-sampling fronend," ISSCC 2002, Dig. Techn. Papers, pp. 314 EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 27 Pracical Sampling Issues v IN M1 C v OUT Swich induced noise due o M1 finie channel resisance Clock jier Finie R sw limied bandwidh finie acquisiion ime R sw = f(n ) disorion Swich charge injecion & clock feedhrough EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 28

15 Sampling Swich Charge Injecion & Clock Feedhrough Swiching from Track o Hold V H +V h M1 VO V L V O ΔV C s off Firs assume is a DC volage When swich urns off offse volage induced on C s Why? EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 29 Sampling Swich Charge Injecion MOS xor operaing in riode region Cross secion view L D Disribued channel resisance & gae & juncion capaciances G C ov C ov L S C j sb B C j db D C HOLD Channel disribued RC nework formed beween G,S, and D Channel o subsrae juncion capaciance disribued & volage dependan Drain/Source juncion capaciors o subsrae volage dependan Over-lap capaciance C ov = L D xwxc ox associaed wih G-S & G-D overlap EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 30

16 Swich Charge Injecion Slow Clock V H Device sill conducing +V h V L - off Slow clock clock fall ime >> device speed During he period (- o off ) curren in channel discharges channel charge ino low impedance signal source Only source of error Clock feedhrough from C ov o C s EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 31 Swich Clock Feedhrough Slow Clock VG V H C ov +V h D C Δ = + ( ε ) ( ) ov V Vi Vh VL Cov + Cs Cov ( V h V L) Cs o = i+δ + C s V L V O V V V C C C V V V V V V 1 V V V = V 1+ + V ( ) ( ) ov ov ov o = i i+ h L = i h L C s C s Cs o i os - off ΔV Cov C where ε = ; V = V V C s ( ) ov os h L Cs EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 32

17 Swich Charge Injecion & Clock Feedhrough Slow Clock- Example M1 10μ/0.18μ VO C s =1pF V H +V h ' 2 ov μ ox μ h L C = 0.1fF / C = 9fF / V = 0.4V V = 0 Cov 10μx0.1fF / μ ε = = =.1% Cs 1pF Allowing ε = 1/ 2LSB ADCresoluion < ~9bi C V = V V = 0.4mV ( ) ov os h L Cs V L V O - off ΔV EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 33 Swich Charge Injecion & Clock Feedhrough Fas Clock Q ch nqch n+m=1 M1 VO mq ch C s =1pF V H +V h V L V O ΔV off Sudden gae volage drop no gae volage o esablish curren in channel channel charge has no choice bu o escape ou owards S & D EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 34

18 Swich Charge Injecion & Clock Feedhrough Fas Clock Clock Fall-Time << Device Speed: C 1 Q Δ V = V V ( ) ov ch o H L Cov + Cs 2 Cs ov ( VH VL) + ( ε ) 1 WCoxL ε = (( )) C 1 WC L V V V C C 2 C V V 1 V ox H i h ov s s o = i + + os where 2 Cs C 1 WC L V V = ( V V ) C 2 C ov os H L s ( V ) ox H h s For simpliciy i is assumed channel charge divided equally beween S & D Source of error channel charge ransfer + clock feedhrough via C ov o C s V H V L V O off +V h ΔV EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 35 Swich Charge Injecion & Clock Feedhrough Fas Clock- Example M1 10μ /0.18μ V H VO +V h C s =1pF ff ff Cov = 0.1, Cox = 9,V 2 h = 0.4V,VDD = 1.8V, VL = 0 μ μ WLCox 10μx0.18μx9fF / μ ε = 1/ 2 = = 1.6% ~5 bi C 1pF ov os H L s s 2 ( V ) C 1 WCoxL VH h V = ( V V ) = 1.8mV 14.6mV = 16.4mV C 2 C s V L V O off ΔV EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 36

19 Swich Charge Injecion & Clock Feedhrough Example-Summary ε V OS 1.6% 16mV.1% 0.4mV Clock fall ime Clock fall ime Error funcion of: Clock fall ime Inpu volage level Source impedance Sampling capaciance size Swich size Clock fall/rise should be conrolled no o be faser (sharper) han necessary EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 37 Swich Charge Injecion Error Reducion How do we reduce he error? Reduce swich size o reduce channel charge? 1Qch Δ Vo = 2Cs Cs Ts τ = RONC s = (noe: = kτ ) W μcox ( VGS Vh) 2 L Consider he figure of meri (FOM): W μcox ( VGS Vh) 1 L Cs FOM = 2 τ ΔV C WC L V V V FOM μ L (( )) o s ox H i h 2 Reducing swich size increases τ increased disorion no a viable soluion Small τ and small ΔV use minimum chanel lengh (mandaed by echnology) For a given echnology τ x ΔV ~ consan EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 38

20 Sampling Swich Charge Injecion & Clock Feedhrough Summary Exra charge injeced ono sampling swich device urn-off Channel charge injecion Clock feedhrough o C s via C ov Issues due o charge injecion & clock feedhrough: DC offse induced on hold C Inpu dependan error volage disorion Soluions: Slowing down clock edges as much as possible Complemenary swich? Addiion of dummy swiches? Boom-plae sampling? EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 39 Swich Charge Injecion & Clock Feedhrough Complemenary Swich V H B B B V L In slow clock case if area of n & p devices & widhs are equal (W n =W p ) effec of overlap capacior for n & p devices o firs order cancel (cancellaion accuracy depends on maching of n & p widh and overlap lengh L D ) Since in CMOS echnologies μ n ~2.5μ p choice of W n =W p no opimal from lineariy perspecive (W p >W n preferable) EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 40

21 Swich Charge Injecion Complemenary Swich Fas Clock ( ) Q = W C L V V V ch n n ox n H i h n ch p p ox p i L ( Vh p ) Q = W C L V V 1 Qch n Q ΔVo 2 Cs C ch p s V H V L ( ) Vo= Vi 1+ ε + Vos 1 WnCoxLn+ WpCoxLp ε 2 Cs In fas clock case To 1 s order, offse due o overlap caps cancelled for equal device widh Inpu volage dependan error worse! B EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 41 Swich Charge Injecion Dummy Swich M1 B M2 V O C s V H B Q 1 Q 2 W M2 =1/2W M1 1 Q Q Q 2 M1 M1 1 ch + ov V L M2 M2 2 ch + ov Q Q 2Q 1 For W W Q Q & Q 2Q 2 M 1 M2 M 2 = M1 2 = 1 ov = ov EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 42

22 M1 Swich Charge Injecion Dummy Swich B M2 V O C s V H B Q 1 Q 2 W M2 =1/2W M1 V L Dummy swich same L as main swich bu half W Main device clock goes low, dummy device gae goes high dummy swich acquires same amoun of channel charge main swich needs o lose Effecive only if exacly half of he charge sored in M1 is ransferred o M2 (depends on inpu/oupu node impedance) and requires good maching beween clock fall/rise EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 43 Swich Charge Injecion Dummy Swich R M1 B M2 W M2 =1/2W M1 VO C s C s To guaranee half of charge goes o each side creae he same environmen on boh sides Add capacior equal o sampling capacior o he oher side of he swich + add fixed resisor o emulae inpu resisance of following circui Issues: Degrades sampling bandwidh EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 44

23 Dummy Swich Effeciveness Tes Dummy swich W=1/2W main As Vin is increased Vc1-Vin is decreased channel charge decreased less charge injecion Noe large Ls good device area maching Ref: L. A. Biensman e al, An Eigh-Channel 8 13i Microprocessor Compaible NMOS D/A Converer wih Programmable Scaling, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980 EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 45 φ + V O+ Swich Charge Injecion Differenial Sampling Cs V V = V V V = V o+ o od i+ i id V + V V + V Voc = = 2 2 Vo+ = Vi Vos1 V = V 1+ + V o+ o i+ i Vic ( ε ) ( ε ) ( ε + ε ) o i 2 os2 ( ε ε ) V = V + V + V + V V od id id 1 2 ic os1 os2 - Cs To 1 s order, offse erms cancel V O- Noe gain error ε sill abou he same Has he advanage of beer immuniy o noise coupling and cancellaion of even order harmonics EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 46

24 Avoiding Swich Charge Injecion Boom Plae Sampling D M1 V H Cs V O V L D M2 Swiches M2 opened slighly earlier compared o M1 Injeced charge by he opening of M2 is consan since is GS volage is consan & eliminaed when used differenially Since C s boom plae is already open when M1 is opened No signal dependan charge injeced on C s EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 47 Flip-Around Track & Hold φ 2 S2A D D φ 2 v IN D C φ 2 S3 S1A S2 v OUT S1 Concep based on boomplae sampling v CM EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 48

25 Flip-Around T/H-Basic Operaion high φ 2 S2A D D φ 2 v IN D S1A C φ 2 S2 S3 Charging C vout Q φ1 =V IN xc S1 v CM Noe: Opamp has o be sable in uniy-gain configuraion EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 49 Flip-Around T/H-Basic Operaion φ 2 high φ 2 S2A D D φ 2 D C φ 2 S3 Holding v IN S1A S2 v OUT S1 v CM Q φ2 =V OUT xc V OUT = V IN EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 50

26 Flip-Around T/H - Timing φ 2 S2A D D v IN D C φ 2 S3 φ 2 S1A S1 S2 v CM vout S1 opens earlier han S1A No resisive pah from C boom plae o Gnd charge can no change "Boom Plae Sampling" EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 51 Charge Injecion A he insan of ransiioning from rack o hold mode, some of he charge sored in sampling swich S1 is dumped ono C Wih "Boom Plae Sampling", only charge injecion componen due o opening of S1 and is o firs-order independen of v IN Only a dc offse is added. This dc offse can be removed wih a differenial archiecure EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 52

27 Flip-Around T/H Consan swich S o minimize disorion φ 2 S2A D D φ 2 v IN D S1A C φ 2 S2 S3 v OUT S1 v CM Noe: Among all swiches only S1A & S2A experience full inpu volage swing EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 53 Flip-Around T/H S1 is chosen o be an n-channel MOSFET Since i always swiches he same volage, i s onresisance, R S1, is signal-independen (o firs order) Choosing R S1 >> R S1A minimizes he non-linear componen of R = R S1A + R S1 Typically, S1A is a wide (much lower resisance han S1) & consan S swich In pracice size of S1A is limied by he (nonlinear) S/D capaciance ha also adds disorion If S1A s resisance is negligible delay depends only on S1 resisance S1 resisance is independen of V IN error due o finie ime-consan independen of V IN EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 54

28 Differenial Flip-Around T/H Choice of Sampling Swich Size C s =7pF THD simulaed w/o sampling swich boosed clock -45dB THD simulaed wih sampling swich boosed clock (see graph) Ref: K. Vleugels e al, A 2.5-V Sigma Dela Modulaor for Broadband Communicaions Applicaions IEEE JSSC, VOL. 36, NO. 12, DECEMBER 2001, pp EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 55 Differenial Flip-Around T/H S11 S12 Offse volage associaed wih charge injecion of S11 & S12 cancelled by differenial naure of he circui During inpu sampling phase amp oupus shored ogeher Ref: W. Yang, e al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC Wih 85-dB SFDR a Nyquis Inpu, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 56

29 Differenial Flip-Around T/H Gain=1 Feedback facor=1 φ2 EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 57 Differenial Flip-Around T/H Issues: Inpu Common-Mode Range 1.7V VCM=1.5V 1V 1V 1V 0.5V 1.2V 1.3V 0.8V Δn-cm =1-1.5= - 0.5V Δn-cm =V ou_com -V sig_com Amplifier needs o have large inpu common-mode compliance EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 58

30 Inpu Common-Mode Cancellaion Noe: Shoring swich M3 added Ref: R. Yen, e al. A MOS Swiched-Capacior Insrumenaion Amplifier, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 59 Inpu Common-Mode Cancellaion 1V+0.2V V-0.2V Track mode (φ high) V C1 =V I1, V C2 =V I2 V o1 =V o2 =0 Hold mode (φ low) V o1 +V o2 =0 V o1 -V o2 = -(V I1 -V I2 )(C 1 /(C 1 +C 3 )) Inpu common-mode level removed EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 60

31 Swiched-Capacior Techniques Combining Track & Hold wih Oher Funcions T/H + Charge redisribuion amplifier T/H & Inpu difference amplifier T/H & summing amplifier Differenial T/H combined wih gain sage Differenial T/H including offse cancellaion EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 61 T/H + Charge Redisribuion Amplifier Track mode: (S1, S3 on S2 off) V C1 =V os V IN, V C2 =0 V o =V os EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 62

32 T/H + Charge Redisribuion Amplifier Hold Mode 2 1 Hold/amplify mode (S1, S3 off S2 on) Offse NOT cancelled, bu no amplified Inpu-referred offse =(C 2 /C 1 ) x V OS, & ofen C 2 <C 1 EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 63 T/H & Inpu Difference Amplifier Sample mode: (S1, S3 on S2 off) V C1 =V os V I1, V C2 =0 V o =V os EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 64

33 Inpu Difference Amplifier Con d Subrac/Amplify mode (S1, S3 off S2 on) During previous phase: V C1 =V os V I1, V C2 =0 V o =V os 1 Offse NOT cancelled, bu no amplified Inpu-referred offse =(C 2 /C 1 )xv OS, & C 2 <C 1 EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2009 Page 65

EE247 Lecture 18. EECS 247 Lecture 18: Data Converters 2005 H.K. Page 1. Sampling Distortion Effect of Supply Voltage

EE247 Lecture 18. EECS 247 Lecture 18: Data Converters 2005 H.K. Page 1. Sampling Distortion Effect of Supply Voltage EE247 Lecure 18 ADC Converers Sampling Sampling swich induced disorion Sampling swich conducance dependence on inpu volage Sampling swich charge injecion Complemenary swich Use of dummy device Boom-plae