Chapter 6: Memory Diagnosis

Transcription

1 Chapter 6: Memory Diagnosis i Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli, Taiwan

2 Outline Introduction RAM Diagnosis Algorithms RAM BISD Diagnostic Data Compression Memory Bitmapping using BIST Diagnosis Methodology in Serial BIST Designs References 2

3 Introduction Why diagnosis is important Yield improvement Repair Design/process debugging Diagnosis Fault location Fault identification Process monitoring Bitmap Fault location 3

4 RAM Diagnosis Algorithms Basic RAM faults are distinguished Stuck-at fault (SAF) Coupling faults State coupling fault (CFst) Idempotent coupling fault (CFid) Inversion coupling fault (CFin) Goals of a diagnosis algorithm Distinguishing i different fault types Locating the aggressors of coupling faults Diagnosis algorithm Low time complexity 4

5 CF(A P,A S,V S ) Notation A P =H or L: position of the aggressor with respect to the victim A S : state/operation of the aggressor that activates the fault V S : faulty state/operation of the victim CF(X): intra-word coupling faults X=(x x 2 x B ): a B-bit word E.g., CFst(0) Italic represents the victim Others are possible aggressors 5

6 Diagnosis for Bit-Oriented Memories March test A finite sequence of March elements March C : { ( w 0); ( r 0, w ); ( r, w 0); ( r 0, w ); ( r, w 0); ( r 0)} Fault dictionary E0 E E2 E3 E4 SAF(0) CFst(L,0,0), CFid(L,,0) CFin(H,, )

7 Diagnosis for Bit-Oriented Memories March-7N diagnosis algorithm { ( w 0); ( r 0, w, r ); ( r ); ( r, w 0, r 0); ( r 0); ( r0, w, r); ( r); ( r, w0, r0); ( r0)} The faults can be detected by the second march element Bit 0 is addressed Bit is addressed r0: r: SAF() SAF(0) r: r0: SAF(0), SAF(), CFin, CFid,. 7

8 March-7N Fault Dictionary E0 E E2 E3 E4 E5 E6 E7 E8 E9 E0 E SAF(0) SAF() CFst(L,0,0) CFst(H,0,0) CFst(L,0,) CFst(H,0,) CFid(H,,) CFid(H,,0) CFin(L,, ) CFin(L,, ) CFin(H,, ) CFin(H,, )

9 Locating CF Aggressors The aggressor of a CF can be located by an adaptive algorithm: { ( wa); w V; ( wa, rv)} v v or { ( wa); w V; ( wa, rv)} For example, the second cell has a CFst(H,0,) v v

10 Diagnosis for Word-Oriented Memories Two-phase procedure:.phase-: Use a diagnosis algorithm on different data background words for SAFs and intra-word CFs 2.Phase-2: Use the diagnosis algorithms for bit-oriented memories on solid backgrounds for inter-word CFs The order of phase- and phase-2 can not be changed 0

11 ( Phase- Diagnosis Algorithm { w0); ( wd, rd, w0, r0); ( w); ( wd, rd, w, r)} D = {000,000,000,000} for 4-bit words Let the background be d i and the expected data output be Y F i (Y): set of faults detected t d in bit i of a word F i (Y): set of faults detected in other bits of a word

12 Fault Sets for the First Bit w0 wd, rd w0, r0 w w D, rd w, r d 0 d d 2 d The fault set for the fist bit F 0 (000)=SAF(0) U CFst(0000) F 0 0( (0)=SAF() ( ) U CFst(000) F 0 (0)=SAF() U CFst() F 0 ()=SAF(0) U CFst(0) 2

13 Distinguishing Faults The SAFs can be obtained by the following set operation F 0 (000) (0) SAF(0) SAF() F 0 () (0) CFst(X) can be obtained by deleting the SAFs from the fault sets SAFs and CFst(X) in other bits can be obtained by a similar approach 3

14 Fault Set for Other Bits SAFs and CFst(X) have been identified in the previous step Fault set (intra-word CFs) for the second, third, and fourth bits F 0 0( (000) = CFin( ) U CFid( ) ) F 0 (0) = CFin( ) U CFid( ) F 0 (0) = CFin( ) U CFid( 000) F 0 () = CFin( ) U CFid( 000) 4

15 Distinguishing Faults CFin(X) and CFid(X) can be obtained by the set operation similar to that for SAFs and CFst(X) Other situations can be analyzed by the same way, and all the intra-word coupling faults can be distinguished 5

16 Locating the CFst(X) Aggressors Assume that a CF(X) occurs and the victim is the vth bit of the faulty word, i.e., the rest of the bits are possible aggressors To figure out the aggressor, an adaptive March- like algorithm is depicted as follows: {( wx );( wd, rd )} Where for 0 i B and i v, and D = X d i { d0, d,, d B } = {0 0,0 0,,00 0 The worst case operations is B- for wd and rd, respectively The overall complexity is m(2b-) for locating all the aggressors inside a RAM with B-bit words and m CFst(X) faults } 6

17 Comparison of Diagnosis Resolution Diagnosis resolution = The number of distinguished faults The number of all target faults Algorithms March-20N [3] 59% Diagnosis [4] 22.7% March Cd [5] 63.6% March Ed [5] March-7N 90.9% 00% Diagnosis resolution 7

18 Comparison of Time Complexity Algorithms March-20N [3] 20 N 5 N Diagnosis [4] 2 N 5 N March Cd [5] 3 N 3 N March Ed [5] 8 N 3 N March-7N 7 N 3 N Time complexity time complexity for first-part test time complexity for second-part test 8

19 Comparison with Diagnosis Diagnosis Ours Number of CFs 9

20 RAM BISD Embedded memory test and diagnosis is an important issue in SOC development BIST is a cost-effective solution, even is the best solution, for embedded memories Low cost At-speed testing Low pin count overhead A BISD design for embedded memories includes BIST Diagnostic data receiver (DDR) 20

21 A RAM BISD Architecture ADDR DI DO WEB CS OE BE F BSO BS I BMS DDR ERR EOP CONT CMD TGO TPG ADDR_T DI_T DO_T WEB_T ADDR_S DI_S DO_S WEB_S SRAM BSC BRS BGO CTR DONE ENA CS_T OE_T CS_S OE_S CLK Test_se 2

22 BISD in Diagnosis Mode In diagnosis mode it can run user-specified march algorithm for test/diagnosis EOP format: Addr Session Syndrome A sample of timing diagram is as follows CLK ERR EOP BEF BSO CONT 22

23 SOC Challenges: Test Data Reduction Conventional test data transportation Workstation Phase transport t ATE Phase 2 transport Chip Disk Pattern memory Source: C.-W. Wu, J.-F. Li, C.-T. Huang, JCIEE

24 Test Data Compression Generic architecture for test data compression and decompression TAM com mpression deco mpression com mpression decom mpression com mpression decom mpression Core Wrapper Core2 Wrapper Core N Wrapper Source: C.-W. Wu, J.-F. Li, C.-T. Huang, JCIEE

25 Diagnostic Data Compression Memory BIST with diagnostic support Embedded memories usually have wide-length words Purpose Reducing testing time and storage requirement of ATE 25

26 Background Diagnostic data for word-oriented RAMs Faulty-cell address March Syndrome Hamming Syndrome March Syndrome A k-bit sequence in which the ith bit is (0) if the fault is detected (not detected) by the ith Read operation For example, the March syndrome for stuck-at-0 t 0fault ltis (000000) for the March-7N test 26

27 Hamming syndrome Background The module-2 sum of the expected fault-free free data output vector and the output vector from the memory under test Diagnosis data usually has to be exported from the BISD circuit serially to the external tester Excessive time for diagnostic test Increased tester storage requirement Compression can solve this problem 27

28 Compression by Syndrome Accumulation Conventional approach for exporting diagnostic data: Each time a fault is detected, the BISD circuit exports the faulty-cell address and March syndrome There is redundancy since a fault can be detected by many Read operations during the test process 28

29 Syndrome Accumulation Process 000 Column address SAF(0) Row address CFst(H,0,0) Fault SAF() SAF() CFin(L,, ) CFin(L,, ) SAF(0) CFst(H,0,0) Diagnostic data D=(0000, ) D2=(00, ) D3=(0000, ) D4=(0000, ) 29

30 Syndrome Accumulation Circuit Rst Up/dow wn shift re gister Clk Hit S S 0 Vdd S 0 Vdd S 0 Vdd W0 M0 W M Wk- Mk- Addres ssing Mec chanism W0 M0 W M Wk- Mk- Data Register Mask Register Faulty-cell Address March Syndrome CAM Data Register 30

31 Syndrome Accumulation Circuit Rst Clk Up/d down shift register Hit S S Data Register 0 0 W0 Mask Register Vdd M0 S Ad ddressing Me chanism M0 W0 W Vdd S 0 0 Vdd W M M Wk- Mk- Wk- Mk Data Register 3

32 Compression Ratio We define the compression ratio as R= Number of compressed bits Number of original bits Compression comparison RAM size March Cd Modified March C March-26N March-2N March-7N 256K 36.84% 26.9% 30.30% 45.7% 28.89% 52K 36.52% 25.79% 29.95% 45.45% 45% 28.55% M 36.23% 25.42% 29.62% 45.2% 28.24% 32

33 Hamming Syndrome Compression Embedded RAMs usually have wide-length words Most of the diagnostic data is Hamming syndrome For example, if an 8kx256-bit RAM is diagnosed by the March Cd [5], which h has 72 Read operations (extended for word-oriented memories with 9 data backgrounds) 3-bit faulty address 7-bit March syndrome 256-bit Hamming syndrome The ratio of Hamming syndrome and the diagnostic data is about

34 Tree-Based Coding Technique A source message can be regarded as the combinations of symbols with different sizes For example, a source message ( ) can be represented by five 4-bit symbols { }, or four 5-bit symbols { }, or so on Only three unique symbols { } are included for 4-bit symbols We can compress the message based on the three unique symbols 34

35 Tree-Based Coding Technique Assumptions A source message S = { s, s,, s } With probabilities S has been sorted with Encoding procedure e { 2 m, p 2, p m p, S Partition the symbols of into parts unique symbols S { s, s,, s } are obtained n With probabilities Where p, p 2, = p, p 2 = p 2, p n 2 = { 2 n p, p, p n m p n = p i i = n p m 35

36 Tree-Based Coding Technique Algorithm of the tree-based code Step : Select two symbols with the smallest probabilities s i and s in as leaves, then generate j S an intermediate node as their parent Step 2: Mark the edge from parent to one child with 0 and dthe other with ith Step 3: Assign the above two probabilities with their sum, then the new S = ( S { si, s j}) { si + s j}. If S is the only root left, then stop. Otherwise repeat step 36

37 Hamming Syndrome Compression Defects are usually distributed in the wafer randomly Fault distribution of a RAM is also random The percentage of the faulty bits with respect to the size of RAM is very small Most of bits of Hamming syndrome are 0s Partition each Hamming syndrome into B-bit symbols The symbol with all 0s usually has the highest probability 37

38 Hamming Syndrome Compression Tree-based Symbol 0000 Hexadecimal 0 Codeword A B A B C C D D E F 0 E F

39 Experimental Results RF R for 64-bit HS R for 28-bit HS R for 256-bit HS B=4 B=8 B=6 B=4 B=8 B=6 B=4 B=8 B= Without Other faults With two Faulty rows 28.6% 7.5% 2.9% 28.7% 7.6% 3.% 28.7% 7.7% 3.2% 26.8% 5.% 9.6% 26.9% 5.2% 9.7% 26.9% 5.2% 9.9% 25.9% 3.8% 8.0% 26.0% 3.9% 8.% 26.% 4.0% 8.2% 28.8% 7.7% 3.3% 27.0% 5.3% 0.0% 26.% 4.% 8.2% 29.0% 8.2% 4.% 27.2% 5.7% 0.7% 26.4% 4.5% 9.0% 32.3% 20.4% 5.3% 30.6% 8.% 2.3% 29.8% 7.% 0.% 3.% 9.5% 4.5% 29.3% 7.%.6% 28.5% 6.% 0.0% 30.5% 9.4% 4.2% 28.8% 6.9%.3% 28.% 5.7% 9.7% 30.% 8.9% 4.3% 28.6% 6.5%.2% 27.8% 5.5% 9.7% 29.8% 8.8% 4.6% 28.% 6.3%.2% 27.5% 5.4% 9.7% 3.7% 22.4% 20.5% 3.9% 22.3% 20.7% With 0% cluster faults 3.9% 22.4% 2.0% 3.9% 22.5% 2.2% 32.4% 23.2% 22.3% 29.0% 8.0% 4.2% 29.% 8.% 4.4% 29.% 8.2% 4.5% 29.3% 8.4% 4.8% 29.6% 9.0% 5.8% 27.5% 5.9% 0.9% 27.7% 6.0%.% 27.7% 6.%.3% 27.8% 6.2%.5% 28.3% 7.0% 2.7% 39

40 A BISD with Compression Capability 40

41 Syndrome Compressor Architecture 4

42 Area Cost of Syndrome Compressor 42

43 Memory Testing & Bitmapping A RAM is built-up as shown below D Address Scrambling Control Q When a memory is tested, a bitmap can be made Bitmap A topological representation of the read operations on a memory during a test 43

44 Bitmap Fault Types of Interest Complete dead All cells in the memory cell array fail at least one read operation 44

45 Bitmap Fault Types of Interest Single cell fault One isolated cell fails at least one read operation 45

46 Bitmap Fault Types of Interest Column fault All cells in one memory column fail 46

47 Bitmap Fault Types of Interest Partial column fault Many, but not all cells in one memory column fail 47

48 Bitmap Fault Types of Interest Row fault All cells in one memory row fail 48

49 Bitmap Fault Types of Interest Partial row fault Many, but not all cells in one memory row fail 49

50 Process Monitoring Any failing bitmap will consist of one or more of the bitmap fault types described above Once a bitmap fault type and its location have been determined for a failing memory Conclusions can be drawn regarding g the physical failure mode and its location For example, a column fault may be caused by a shorted bitline 50

51 Bitmapping Using BIST Normal I/Os BIST Scrambler Test Collar RAM Diagnostic Data output DDR 5

52 Diagnosis Using Serial BIST Serial fault masking effect SA (RxW 0) 8 Output data X X X X X X X X X X Next state ( R0W ) 8 Output data Next state 52

53 Diagnosis Using Serial BIST Using bidirectional serial interface Memory Write Read Latch Latch Latch Shift_left/right SI SO 53

54 Diagnosis Using Serial BIST Two-phase diagnosis methodology Phase-: shift-right operation (RxWW 0) 8 Output data SA X X X X X X X X X X Next state Phase-2: shift-left operation ( R0W ) 8 Output data Next state 54

55 Summary The following topics have been given March-based diagnosis algorithms RAM BISD methodology RAM BISD with compression capability Memory bitmapping using BIST Diagnosis methodology in serial BIST designs 55

56 References [] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, ``A built-in self-test and self-diagnosis scheme for embedded SRAM'', in Proc. 9th IEEE Asian Test Symp. (ATS),Taipei, Dec. 2000, pp [2]J.-F. Li, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, March-based diagnosis algorithms for Stuck-At and coupling faults, Proc. Int. Test Conf. (ITC), Oct., 200, pp [3]I.-Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lweandowski, Built in self repair for embedded high density SRAM, in Proc. Int. Conf. (ITC), Oct. 998, pp [4]T.-J. Bergfeld, et al., Diagnostic testing of embedded memories using BIST, in Proc. Design, Automation and Test in Europe (DATE), Paris, Mar. 2000, pp [5]V. N. Yarmolik, et al., RAM diagnostic tests, in Proc. IEEE Workshop on Memory Technology, Design and Testing (MTDT), 996, pp [6]J.-F. Li, R-S R.-S. Tzeng and C.-W. Wu, Wu Diagnostic data compression techniques for embedded memories with built-in self-test, Journal of Electronic Testing: Theory and Applications, vol. 8, pp , [7]I. Schanstra, et al., Semiconductor manufacturing process monitoring using built- in self-test for embedded memories, in Proc. Int. Test Conf. (ITC), Oct. 998, pp [8]D.-C. Huang and W.-B. Jone, A parallel built-in self-diagnostic method for embedded memory arrays, IEEE Trans. On CAD, vol.2, no. 4, pp , April,