DPSK signal carrier synchronization module implemented on the FPGA

Transcription

1 06 Sixth Itratioal Cofrc o Itrumtatio & Maurmt, Computr, Commuicatio ad Cotrol DPSK igal carrir ychroiatio modul implmtd o th FPGA Yufi Yag, Zhuomig i, Ricai Tia, Xiaoli Zhag 3 School of Elctroic ad Iformatio Egirig, Harbi Ititut of Tchology, Harbi, Chia Scic ad Tchology o Iformatio Tramiio ad Dimiatio i Commuicatio twork aboratory, Shijiahuag, Chia 3 School of Iformatio ad Commuicatio Egirig, Harbi Egirig Uivrity, Harbi, Chia yyf63760@qq.com, huomig@hit.du.c, rctiai@hit.du.c, hagxiaoli@hrbu.du.c Abtract Thi papr propo a mthod to implmt th modifid quar loop digitally o th FPGA to olv th problm, that th divid circuit i th traditioal quar loop i difficult to achiv. Th modifid quar loop ha a imilar tructur to th traditioal quar loop. Th mthod of modifid quar loop i to multiply quadratur output togthr to rplac th divid circuit. I thi papr, a pcific mthod i giv to digiti th quar loop. Th output carrir igal ad th frqucy diffrc will b aalyd i th coditio of diffrt iitial frqucy offt, paramtr of th loop filtr ad iput SR. Kyword digital pha-lockd loop; quar loop; carrir ychroiatio; FPGA I. ITRODUCTIO I a commuicatio ytm, mot dmodulatio chm mploy o-cohrt dmodulatio for bttr prformac. Ad th cohrt dmodulatio i rquird to xtract cohrt carrir. Sigal i th commuicatio proc will produc a frqucy offt du to th Dopplr Effct. A a rult, th local carrir ad th igal big rcivd wo t b ychroid. Thi will b th rao for rror of dmodulatio. Thu producig a local carrir with th am frqucy ad pha of th rcivd igal i vry importat. Carrir ychroiatio ha two ca. O i that th rcivd igal compriig a carrir uch a ASK ad th othr i that th rcivd igal do ot cotai carrir uch a DPSK. I thi papr, w focu o th cod ca. W will u DPSK igal a a xampl to xtract carrir from upprd carrir modulatio chm. I rct yar th tudy of carrir ychroiatio ha alrady b vry matur. Th commo mthod ar Squar loop [], Cota loop [], Dciio Fdback P [3] ad o o. Squar loop i bad o th pricipl of P (Pha ockd oop [4], which i a clod loop pha gativ fdback cotrol ytm ad ca grat a high dgr of tability clock [5]. For dcraig rror withi a aalog pha-lockd loop, a all-digital pha-lockd loop (ADP with oly digital compot ad digital opratio i ud [6]. I th DPSK modulatio ytm, Squar loop i th mot commo way to xtract th aychroou carrir [7]. With th dvlopmt of digital itgratd circuit, mor ad mor aalog circuit ar gradually rplacd by digital itgratd circuit. Buildig th digital modl of th aalog circuit ha b a urgt tak. At th am tim, with tchological dvlopmt digital itgratd circuit ar udrgoig rapid traformatio. ASIC, DSP, CPU ad FPGA, four mthod of achivig platform i modr digital igal procig play a uparallld rol [8]. I th cour of procig a igal, FPGA utili paralll mthod to proc igal. So ow i om high-pd digital igal procig, FPGA i playig a icraigly importat rol. I thi papr, w will dtail th digitiatio proc of th quar loop ad tablih a digital modl of th pha dtctor loop filtr ad low pa filtr. W will dtrmi th atural agular frqucy of th loop ad th total loop gai ad th bit width of frqucy word. Fially w will implmt th quar loop o th FPGA, ad aaly th rult of th output of local carrir igal, th gap btw th iput igal carrir ad th local carrir udr diffrt SR, ad diffrt iitial diffrc of th ocillatio frqucy ad th iput igal frqucy ad diffrt paramtr of th loop filtr C adc. Th rmaidr of thi papr i orgaid a follow: Sctio II itroduc th baic modl ad fudamtal cocpt of P ad quar loop. Th dig proc ad pcific paramtr will b dtaild i thi ctio. Aalytical ad imulatio rult ar dicud i Sctio III ad th cocluio i draw i lat ctio. II. OOP FUDAMETAS AD DETAIED DESIG PROCESS Squar loop i improvd o th bai of P. Whil P (Pha ockd oop i a clod loop pha gativ fdback cotrol ytm. Thi gativ fdback cotrol ytm i compod of PD (Pha Dtctor F (oop Filtr ad VCO (Voltag-Cotrolld Ocillator. Th mathmatical modl of PD, F ad VCO ca b implifid a U i ( t ( d p F( p p ( K / p 0 ( /6 $ IEEE DOI 0.09/IMCCC

2 Th w ca build th pha modl of Pha-lockd loop. ( t ( t i[.] U d ud ( t F( p u ( c t Fig. P pha modl ( K p So w ca dduc th gral form of th pha lockd loop dyamic quatio. It i a follow. p ( t p ( t KF( pi ( t (4 I girig applicatio, a raoabl approximatio of th quatio i dd. Th oliar quatio ca approximat a liar quatio. It ca b writt a p ( t p ( t KF( p ( t (5 So it i a liar cod-ordr ytm with gral prformac charactritic of cod ordr liar ytm. Circuit aalyi of cod ordr loop i vry matur, ad thr ar a lot of aalyi rult ca b rfrcd. Scod-ordr ytm rpo may b o-ocillatory or ocillatory. Uually w u o dampig ocillatio frqucy ad dampig factor to dcrib th rpo of th ytm. Scod-ordr digital loop rpo ca till u o-dampig ocillatio frqucy ad dampig factor to dcrib. Paramtr covrio rlatiohip btw aalog loop ad digital loop ca b tablihd. o mattr what th workig viromt i, th loop will ivitably b affctd by oi ad itrfrc. For th phalockd loop, th mot commo oi i Gauia whit oi. Output pha oi variac i th whit Gauia oi coditio ha importat girig igificac. Th variac i how a follow. B 0 Ui (6 0 i Gauia whit oi powr pctral dity at th iput. B i aothr importat loop oi prformac paramtr Sidd oi badwidth of th loop. Whil B i a follow. 0 B H( j F df( H (7 For th idal cod ordr loop, 8 0 / B i a follow. B 4 (8 A w ca, B ca b compltly rprtd by atural ocillatio frqucy of th loop ad dampig factor. I a commuicatio ytm, w uually u th cocpt of SR to maur th quality of th igal. A w all kow, iput SR ma that iput igal carrir powr ratio of th powr of th oi through frot loop badwidth. ( S / i Ui (9 B W ca dfi a loop SR to rflct th ihibitio o th loop oi. It ca b xprd a follow. ( S / 0 0 i Ui (0 B Aftr dducig th quatio (0, w ca gt Bi ( S / ( S / i ( B From th abov dicuio, w ca gt th cocluio that loop SR will dtrmi th pha jittr aftr th loop lockd. Thrfor, bfor writig Vrilog HD cod, w hav to fully udrtad th digitally implmtd tructur of compot i th loop. Th digitalid compot compriig th pha lockd loop will b dicud blow. Aftr amplig, th pha dtctor output igal u ( k U i ( k ( d d To implmt a digital filtr, w hav to fid th mthod of th aalog filtr mappig ito th digital domai. Th biliar traform i th mot commoly ud. Biliar traform i vry impl Jut apply th followig formula. (3 T T (4 T Thrfor, th digital ytm fuctio of th idal itgral filtr i F T T ( C C (5 Accordig to th formula, it i ay to com to th raliatio of th digital loop filtr tructur IPUT CK C C Fig. Digital loop filtr tructur OUTPUT 06

3 f W dfi K0 a frqucy cotrol gai of CO, f ad uit i rad / V ad dfi K 0 Tdd a pha cotrol gai of CO, ad uit i rad / V. Mawhil T d i th pha accumulatio word updat cycl. I th digital domai, CO quivalt of pha accumulator. So th pha modl of th CO i ( k ( k ( k ( k K u ( k (6 0 c Uig th proprti of th -traform, th rlatiohip btw CO output pha ad cotrol voltag i K0 ( k ( uc( k u ( c k (7 Digital pha-lockd loop dyamic quatio i ( k KF( ( ( k (8 K i rad, Sytm fuctio of th digital pha lockd loop i UdK 0 i th total gai for th digital loop, uit KF( ( H ( (9 KF( ( Equatio (5 will b ubtitutd ito th quatio (9. Th corrpodig ytm fuctio digital cod ordr phalockd loop filtr ca b obtaid. It i a follow. KC ( KC KC H ( (0 ( KC ( KC KC Aftr biliar traformatio th ytm fuctio of aalog pha-lockd loop i covrtd ito th digital domai ytm fuctio. H [4w T ( w T ] ( w T [( w T 4w T] [4 4w T ( w T ] [( w T 8] [4 4w T ( w T ] ( To mak two formula compltly qual, w d to ur th umrator ad domiator cofficit ar all qual. Fially, i girig, w u approximat mthod to dal with thi problm. Wh wt 4( wt 8w T w T C ( 4 4w T ( wt K K C 4( wt 4 4w T ( wt ( wt K K ( Th abov formula i two loop filtr cofficit calculatio formula, which ar widly ud i girig. I ordr to ur tabl opratio of th loop, w mut ur that th tir digital pha-lockd loop i caual ad tabl. Timdomai dicrt ytm thory how that cary ad ufficit coditio of th digital ytm tability i that all pol of th clod-loop fuctio ar iid th uit circl. It i ay to gt th rag of th loop filtr cofficit a follow. KC 4KC KC KC 0 (3 Th mai ida of th quar loop i to covrt th rcivd igal quard. Sigal aftr covrio will cotai cod harmoic of carrir. Ad th through a arrow bad filtr, th cod harmoic igal i filtrd out. xt th igal will go through a dividig circuit. Th igal with th am frqucy ad pha of th carrir wav ca b obtaid. Whri th arrow bad filtr ca b rplacd by a pha lockd loop. A th traditioal dividig circuit cotitutd by a digital dividr, it will dtroy th i wav, which d to add a filtr circuit aftr that. Th implmt will b mor complx, o w u a modifid quar loop. Squar loop iput Cohrt carrir output bpf lpf loopfiltr co[ ( t ] c t i[ ( t ] c t VCO/ CO Fig.3 Modifid quar loop tructur Th mthod of modifid quar loop i to multiply quadratur output togthr. Th w d it to th pha dtctor. Thu limiatig th d for divid circuit, you ca av a lot of ytm rourc. Accordac with th rquirmt of thi articl, th pcific dig proc i a follow. Firt, th atural agular frqucy of th loop w hould b digd. Accordig to th rquirmt of rapid acquiitio of badwidth> = 00 kh ad th formula /(, it ca b calculatd that w > 70.7 kh. Alo bcau 8 ( S / ibi 3 w kh (4 ( S / Hr, w choo w T 0., thu w 300kH. Thrfor, th fial loop atural agular frqucy rag 70.7kH w 300kH (5 W choic w =50 kh. So th total loop gai i KmUiUo K K 0Ud K 0 (6 K 0 i th VCO cotrol gai. I th digital pha-lockd loop, w u CO itad of VCO. So th VCO cotrol gai i th CO pha cotrol gai K 0. Km i th gai factor i th multiplir of th pha dtctor. Ui i th amplitud of th iput igal. Uo i amplitud of th output igal of th local ocillator CO. Bcau 07

4 K f 0 Tdd (7 UiUo of th total loop gai formula i dcidd by bit wid of th output of valid data B lp.th maximum amplitud ofuiuo i B lp-. Th total gai of th digital pha lockd loop i f Blp K Tdd(. T dd 8/ f. By adjutig th loop gai, modifid quar loop ca b compltly quivalt to th origial quar loop. Sic th multiplicatio of th two orthogoal igal will brig a multiplicatio factor of /, th total loop gai of th modifid quar loop i f K T Blp dd ( (8 Fially, th data for th multiplicatio ar two 5-bit biary data. All valid data bit i 9 bit. Thrfor, th bit width of th output data of th loop filtr ffctiv i Blp 9. I th proc of th dig ad implmtatio of DDS, a rul hould b followd to ur that th total loop gai i approximatly qual to. Th w will calculat th DDS frqucy word bit width. Accordig to th total loop gai quatio f K T Blp dd ( (9 Calculatio how that, wh = 3, w ca gt that K = Th iitial valu ad th iitial pha of th DDS frqucy cotrol word ar M / 0 f 0 f (30 M 0 / (3 Aumig that th iitial frqucy f 0 = 6MH, M 0 = Ad accordig to th formula 4( wt 8w T w T C (3 4 4w T ( wt K K 4( wt ( wt C (33 4 4w T ( wt K K C ad C ca b calculatd by ubtitutig th calculatd paramtr,. W ca vrify that all pol of th fuctio i th clod-loop ar iid th uit circl. III. VERIOG HD CODIG AD SQUARE OOP SIMUATIO Grally pakig, FPGA dig ha bottom-up ad topdow two dig ida. Hr w u th top-dow mthod. Th ida of Top-dow ma dig top-lvl modul firt. Itrfac ad fuctio of th lowr lvl modul hould b digd i th top modul. Th top-lvl modul i how a follow. Fig.4 Th top-lvl RT chmatic of quar loop Thr ar thr multiplir, o low pa filtr, o CO ad o loop filtr i th top-lvl modul. DDS ad th multiplir ca b mad from IP cor. ow-pa filtr ad loop filtr ar rquird to maually writ Vrilog HD Cod. ow pa filtr dig u IIR typ. But thr i o radymad IIR filtr IP cor ca b ud. Thrfor, w d to maually writ Vrilog HD cod. Dig paramtr of MATAB ar quatid by 3bit. IIR filtr implmtatio tructur ca b grally dividd ito dirct typ ad cacad. A th IIR filtr i thi xampl i th fourth ordr, w will u cacad tructur. IIR filtr tructur i ot complicatd. It ca b a two impl multiply-add tructur. Multiply-add tructur of ro cofficit ad multiply-add tructur pol cofficit. I fact, th digital loop filtr i a firt ordr IIR filtr. But it hould b otd that ulik th prviou IIR filtr, th clock of th loop filtr i pha accumulatio clock of DDS rathr tha th data amplig clock. Aftr th compltio of th dig ad implmtatio of FPGA girig. W d to prform imulatio tt of th ytm w digd. Firt, w u MATAB to grat origial tt timulu data, avig th pcifid grat data fil to th pcifid path. Scod, w pcify th iput ad output fil i th tt bch ad imulatio. Bfor imulatio, w d to imply modify th program to mt th rquirmt of th iitial frqucy offt btw th ocillatio frqucy ad th iput igal frqucy i 50 kh5 kh ad 0 kh. Th CO output igal i how i th fig.5 ad th output frqucy offt (df btw iput igal ad local ocillator i how i th fig.6. 08

5 th df igal i.9348 kh aftr th loop i lockd. Thi i rlatd to th loop filtr paramtr C adc. What w will do xt i to imulat output wh th paramtr C ad C i chagd ad th iitial frqucy offt i 5 kh ad th SR i 00dB. Th rult ar how i fig.7. Fig.5 Th CO output igal udr th iitial frqucy diffrc of 5 kh From th fig.5 w ca obtai that th output i igal of CO i ychroid with th iput igal. It ma that th output igal i th ychroiatio carrir igal to b xtractd. W ca that thr i a gap btw th output igal ad th iput igal. Bcau carrir ychroiatio proc tak tim. What w d to do i adjut th pha btw iput igal ad th CO output igal to implmt ychroiatio of carrir pha. Fig.6 Th output igal of df udr diffrt iitial frqucy offt From th imulatio rult w ca obrv that pha lockd loop lockig i ralid. From th fig.6 w ca fid that th tim cot for lockig i.8m approximatly wh th iitial frqucy offt i 50 kh. Th tim cot for lockig i 0.6m approximatly wh th iitial frqucy offt i 5 kh. Th tim cot for lockig i 0.m approximatly wh th iitial frqucy offt i 0 kh ad th lockig ralid oly aftr a ocillatio. So w ca that th largr th iitial frqucy offt i, th logr th tim rquird for lockig i. Th imulatio how that th ma frqucy diffrc of th firt i 50 kh ad th cod i 5 kh ad th third i H. It th am with th ttig of iitial frqucy offt. Mawhil, th max pak-to-pak valu of Fig.7 Th output igal of df udr diffrt paramtr of loop filtr I th fig.7, w ca that th loop lockig i ralid i diffrt loop filtr paramtr. I th firt o, th tim cot for lockig i 0.6m approximatly wh th paramtr of th loop filtr C ad C I th cod o, th tim cot for lockig i 0.m approximatly wh th paramtr of th loop filtr C adc = I th third o, th tim cot for lockig i 0.05m approximatly wh th paramtr of th loop filtrc 0.85 adc = So w ca draw a cocluio that th gratr th paramtr valu i, th logr tim th lockig tak. Mawhil, i th firt o, th max pak-to-pak valu of th df igal i.9348 kh aftr th loop i lockd wh th paramtr of th loop filtr C ad C I th cod o, th max pak-to-pak valu of th df igal i 3.34 kh aftr th loop i lockd wh th paramtr of th loop filtr C adc = I th third o, th max pak-to-pak valu of th df igal i kh aftr th loop i lockd wh th paramtr of th loop filtrc 0.85 adc = So w ca draw a cocluio that th gratr th paramtr valu i, th gratr th max pak-to-pak valu of th df igal i. Th loop filtr paramtr C ad C i up to th total loop gai K ad th atural agular frqucy of th loop w. Th total loop gai K i approximatly. So it i up to w. Th mallr th valu of w i, th lowr th rquird SR i for th loop lockig. It ma that th loop i air to b lockd i th poor coditio ad th tady pha rror aftr th loop i lockd i mallr 09

6 ad th tim cot for lockig i logr. Whil th gratr th valu of w i, th widr th bad of fat acquiitio i. Th tady pha rror i biggr aftr th loop i lockd mawhil th tim cot for lockig i hortr. What w will do xt i to imulat th output igal df wh th SR of th iput igal i 00dB or 6dB. Th iitial frqucy offt i 0 kh. Th paramtr of th loop filtr ar C ad C Th rult ar how i fig.8 ad fig.9. Fig.8 Th output igal udr iput SR i 00dB draw that th lowr th iput SR i, th logr tim cot for lockig i ad th biggr th tady pha rror i aftr th loop i lockd. W ca alo fid that thr i pha rvral btw th carrir xtractd ad th iput carrir. Thi i xactly th phomo that th quar loop ca t ovrcom thir ow hortcomig that thr i a 80 dgr pha ucrtaity. But it wo t b a problm wh w u DPSK igal. ACKOWEDGMET W apprciat lab mmbr Zhjia Xiao, Mgqi Wag ad Juqig Qi for thir dicuio ad commt. Th author gratfully ackowldg th upport of th grat of Scic ad Tchology o Iformatio Tramiio ad Dimiatio i Commuicatio twork aboratory o.ex COCUSIO I thi papr, a modifid quar loop i propod. It ha a imilar tructur to th traditioal quar loop. Th pha modlig of th P ad th tructur ar prtd. Th imulat rult how that th largr th iitial frqucy diffrc i, th logr th tim rquird for lockig i. Th mallr th valu of w i, th lowr th rquird SR i for th loop lockig. Th tady pha rror aftr th loop lockd i mallr ad th tim cot for lockig i logr. Whil th gratr th valu of w i, th widr th bad of fat acquiitio i. Th tady pha rror aftr th loop lockd i biggr ad th tim cot for lockig i hortr. Th lowr th iput SR i, th logr tim cot for lockig i ad th biggr th tady pha rror i. Ad th loop ca b lockd v th iput SR i 6dB. REFERECES Fig.9 Th output igal udr iput SR i 6dB I th fig.8 ad fig.9, w ca that th loop lockig i ralid i diffrt iput SR v wh th SR i 6dB. I th fig.8, th tim cot for lockig i 0.m approximatly wh th iput SR i 00dB. I th fig.9, th tim cot for lockig i.3m approximatly wh th iput SR i 6dB. Th max pak-to-pak valu of th df igal i.9348 kh aftr th loop i lockd wh th iput SR i 00dB. Th max pak-to-pak valu of th df igal i 4.066kH aftr th loop i lockd, wh th iput SR i 6dB. Th cocluio ca b [] Hog J S, acatr M J. Badpa charactritic of w dual-mod microtrip quar loop roator[j]. Elctroic ttr, 995, 3(: [] Cah C R. Improvig Frqucy Acquiitio of a Cota oop[j]. IEEE Traactio o Commuicatio, 977, 5(: [3] Raphali D, Yaiv O. ar-optimal P dig for dciio-fdback carrir ad timig rcovry.[j]. IEEE Traactio o Commuicatio, 00, 49(9: [4] Maati J G. ow-jittr proc-idpdt D ad P bad o lf-biad tchiqu[j]. Solid-Stat Circuit, IEEE Joural of, 996, 3(: [5] Arbl Y. Fractioal pha-lockd loop for gratig high-dfiitio ad tadard-dfiitio rfrc clock: US, US785408[P]. 00. [6] Chag H H. All-digital pha-lockd loop: US, US B[P]. 0. [7] il T, Gli U, Stubkjar K E. Rductio of AM-iducd palty i DPSK rcivr by um-quar dmodulatio[j]. IEEE Photoic Tchology ttr, 99, 4(3: [8] Paradh-Afhar H, I P. Highly Vratil DSP Block for Improvd FPGA Arithmtic Prformac[C]// IEEE Itratioal Sympoium o Fild-Programmabl Cutom Computig Machi, FCCM 00, Charlott, orth Carolia, Ua, -4 May. 00: