Interconnect Yield Model for Manufacturability Prediction in Synthesis of Standard Cell Based Designs *

Transcription

1 Interconnect Yield Model for Manufacturability Prediction in Synthesis of Standard Cell Based Designs * Hans T. Heineken and Wojciech Maly Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA 523. Abstract A sound IC design methodology must be supported by adequate manufacturability assessment tools. These tools should assist a designer in predicting IC manufacturing cost in as early a design stage as possible. In this paper a yield model is proposed that takes as input a standard cell netlist and produces as output a yield estimate without performing placement and routing. This yield model has been successfully used to predict the interconnect yield of standard cell designs that were implemented with two place and route tools. The proposed yield model can be used as a crucial component in the objective function of a circuit synthesis tool as well as in technology mapping optimization..0 Introduction Current trends in IC manufacturing force IC producers - especially fabless design houses - to consider a variety of manufacturing options during the design process. These options include various silicon vendors and/or technologies in which to implement a particular design. Consequently, there is a growing need to perform a quick assessment of a design s manufacturability, preferably before completion of all design stages. A need also exists to compare silicon fabrication options in terms of possible manufacturing costs in as early a design stage as possible. Manufacturability, in its basic form, can be measured in terms of the number of defect free IC chips obtained from a single manufactured wafer []. This number can be easily derived if die area and manufacturing yield are known. Prediction of these two design attributes is, therefore, crucial to any sound IC design methodology. Unfortunately the impact of many design decisions on manufacturability is currently not well understood and modeled. For instance, yield loss is typically modeled as a function of die size: the larger the area of the die the lower the yield. The relationship, in its simplest form, the Poisson yield model, can be expressed as Y=exp(-A o D) where A o is the die area and D is the defect density [2]. However, this relationship has been shown to provide a poor estimate of yield [3,4]. Therefore an area estimate does not suffice in estimating yield, and a need for an accurate manufacturability assessment of an IC translates into a need for an accurate yield estimation model. In this paper, a yield modeling technique which * This work has been supported in part by Semiconductor Research Corp. under contract 96-DC-068. addresses the core of the above problem is presented. More specifically this paper proposes a yield model which can be used for yield loss prediction of standard cell interconnects. 2.0 Applied Modeling Methodology The cost of a defect-free IC die can be expressed as: C = C wafer N die Y () where C wafer is the cost of a wafer, Y is the yield of the wafer, and N die is the number of dies per wafer. N die is a function of the area of the wafer, A wafer, and the area of the die, A die. The most critical components of a new design s manufacturability are therefore A die and Y. Prediction of die area is relatively well understood [5,6,7]. Consequently yield estimation is the most crucial element of any accurate manufacturability assessment task. The yield of a standard cell design can be expressed as a product of the yields of the cells and the yield of the interconnects between cells. Since the list of cells of a new design is known during the circuit synthesis stage, one can predict cell-related yield loss using the cell layouts from a library. (A cell s yield can be estimated from previous fabrication experience or with tools such as CODEF [8]. CODEF takes as input a set of processing steps and a set of contamination parameters, and estimates the sensitivity of a cell's layout to defects.) The yield of the interconnect channels, on the other hand, is more difficult to assess early in the design process - their layouts are not available until after cells are placed and routed. Therefore, the interconnect yield must be modeled as a function of attributes taken from design data available before layout. To this end, this paper proposes an interconnect yield model that models yield as a function of a netlist s structural attributes. The following methodology was used to develop the interconnect yield model proposed in this paper:. A yield model was selected that successfully models yield as a function of layout attributes. In particular, this model relates yield to the critical area curves of an IC. (The critical area is a measure of the sensitivity of a layout to defects [9,0,].) 2. The yield model was then simplified. The obtained model expresses yield as a function of a single critical area point for a single metal layer. (A critical area point is the critical area at a given defect radius.) 3. An interconnect length model was developed that models the distribution parameters, mean and variance, ICCAD /96 $ ΙΕΕΕ

2 of an interconnect's physical length as a function of netlist attributes. 4. The critical area point was then modeled as a function of interconnect lengths. Consequently the yield was modeled as a function of interconnect lengths and hence of structural attributes of a netlist. 3.0 Yield Modeling Yield loss occurs when there is an unacceptable mismatch between expected and actual functionality of a fabricated IC. In a mature process a dominant mechanism causing yield loss is defects deposited or formed on a particular layer of an IC []. There are numerous defectrelated yield models (see [2]). One that has been successfully used to model yield treats defects as two-dimensional disks of extra or missing material embedded in a conducting, semiconducting, or insulating layer of an IC [9]. These defects are assumed to have a defect density, D oi, which specifies the frequency of occurrence of defects of type i; and a defect size distribution, f i (r), which specifies the variation in frequency between defects of different radii, r, for defects of type i. A widely used defect size distribution function is f i (r)=k/r p, where r is the defect radius, and k and p are parameters of the model [0]. The defect density variation, D i (r), for defects of type i, can be calculated by multiplying the defect size distribution, f i (r), by the defect density, D oi [3]: D i ( r) = D oi k r p = K i r p (2) where the constant K i is substituted for the product D oi k. The defect-related yield model also uses the concept of critical area [9,0,]. The latter is a measure of the sensitivity of a layout to defects. Critical area, Acr i (r), is defined for defects of type i and radius r as the area of a layout where if the center of a circular defect forms a fault occurs in the circuit. Fig. shows an example of the critical area for an array of three metal lines for a defect of radius r. Defects of extra metal material Defect causing fault w (short) s r Defect not Critical area causing fault for defects with r radius r Metal line Fig. Critical area for an array of metal lines. 3. Critical Area-Based Yield Model Given the critical area of an IC and the defect density and size distributions for a given defect type i, the defectrelated yield, Y i, of an IC can be derived using a Poisson based yield model [9]: Y i N = exp Acr i ( r)d i ( r)dr, Y (3) die = 0 Y i i = Y die is the defect-related yield of the die for all defect types and N is the number of defect types. This model has been used successfully to model yield in a high-volume fab line [4]. 3.2 Single Layer Critical Area-Based Yield Model In the designs used in [4], it was observed that a correlation exists between the critical areas of the metal layers. This is also the case with standard cells designs. Fig. 2 plots metal critical area vs. metal2 critical area for defect radii of 0.8 and.2 µm, for ten standard cell designs. Observe that with such a degree of correlation, the critical area function of one layer can be easily expressed in terms of the critical area of the other layer. Moreover, a single layer can well represent the defect sensitivity of both layers. Critical Area - Metal (µm 2 ) Critical Area - Metal (µm 2 ) 3e+5 6e+5 4e+5 2e+3 4e+3 6e+3 Critical Area - Metal2 (µm 2 ) a) Defect radius = 0.8µm. 3e+5 Critical Area - Metal2 (µm 2 ) b) Defect radius =.2µm. Fig 2. Metal vs. metal2 critical area. 8e+3 4e+5 In the remainder of this paper the subscript i in model (3) is dropped, and, unless otherwise noted, the implied defect type is extra material metal. (In a subsequent section it will be demonstrated that the metal2 yield can be modeled as a function of the metal yield.) 3.3 Simplified Yield Model In [4], it was shown that the critical area curve can be well approximated by two linear functions, one modeling the initial rise in the critical area, the second modeling the critical area as it begins to saturate (Fig. 3). Of the two linear functions only the first, representing the initial rise of the critical area, is of relevance from a yield perspective. This is a consequence of the value of the model parameter p in (2). The value of p is such that defects larger than those covered by the first linear function

3 Critical Area (µm 2 ) 2e+6 2e+6 e+6 5e Defect Radius (µm) Fig 3. Linear approximation of critical area curve. occur so infrequently that they have a negligible contribution to yield. When ignoring defects with radii covered by the second linear function, model (3) calculates the error in metal yield for the standard cell design used in Fig. 3 to be.% (using defect model parameters p=3.5, K=20). Using only the first linear function to approximate critical area, it was shown in [4] that the yield can be expressed as: Km Y = exp , (4) ( p ) ( p 2)rp 2 where r is half the minimum spacing between metal lines, and m is the slope of the first linear function. The slope is m = Acr(r 2 ) / (r 2 -r ), where the critical area points (r,0) and (r 2,Acr(r 2 )) are the end points of the linear function. Note from Fig. 3 that the rise in critical area is well modeled by a linear function. Therefore, in principle, any critical area point (r o,acr(r o )), such that r <r o <r 2, can be chosen to calculate the slope. Table lists examples of the estimated metal yields of ten standard cell designs using equations (3) and (4). The model parameters used are p=3.5 and K=20; the critical area point in slope m is at a defect radius r o =0.8µm. The average difference between the estimates generated by yield models (3) and (4) is less than 0.3%. Table. Estimated yields of ten standard cell designs. Circuits Extracted Critical Area Linear Approximation Number of Cells Estimated Metal Yield (Model (3)) Estimated Metal Yield (Model (4)) Standard Cell Yield Modeling As was already mentioned the key difficulty in estimating the functional yield loss of standard cell layouts lies in estimating the yield loss of the interconnect channels. This is for the following reasons:. The probability of failure owing to a defect in the layout of a particular cell can be derived up front, given that the cell s layout and hence critical area is known. This is not the case for the interconnect channels whose layouts are known only after placement and routing. 2. Yield loss owing to defects takes place primarily in the metal layers. This is because a) the defect count is higher in the metal layers - typically over twice that in the poly layer; b) the use of metal layers is more extensive than the other layers. Since the metal layers in a standard cell design are primarily reserved for the interconnect layers (and the power rails) it especially important to estimate the yield loss in the interconnect channels. 4.0 Interconnect Length Model The interconnect length model used in this paper was described in [4]. It was derived by extracting structural attributes from standard cell netlists and analyzing relationships between these attributes and the physical interconnect lengths. This interconnect model is briefly described in the remainder of this section. In a subsequent section it is used to help estimate the slope of the critical area of the interconnect channels, m, in formula (4). 4. Net Weight In the interconnect length model presented below, a differentiation is made between interconnects and nets. Interconnects are multi-terminal equipotential regions connecting inputs and outputs of cells in a layout; nets are two terminal portions of an interconnect connecting the output of a cell with the input of a cell on the same interconnect. For instance, in Fig. 4, interconnects are, 2, 3, etc.; nets of interconnect 5 are cd, ce, and cf, (nets are labeled by the cells they connect - net cd connects cells c and d). The model, built for estimating worst case critical path delay, is concerned with the estimation of the distribution parameters, mean and variance, of net lengths. i 2 i 2 a b 3 4 c 5 Fig 4. Network used to define circuit and net attributes. The interconnect length model presented in [4] identifies two attributes that directly affected the length of a net. These attributes are: size - number of cells attached to the interconnect on which the net resides. In Fig. 4, size of net cd = {c,d,e,f} = 4. i 3 i 4 i d e f 9 0 o g h o 2 2 o 3 3 o 4

4 attint_nc - number of interconnects attached to the cells of a net excluding the interconnect from which the net is taken and excluding interconnects common to both the input and output cells of a net. In Fig. 4, attint_nc of net cd = {3,4,6,9} = 4. The cumulative sum of these attributes is defined as the net weight, i.e., net_weight = size + attint_nc. In Fig. 4, the net_weight of net cd = 8. Fig. 5 show a plot of the mean net length as a function of net weight for one of the circuits in Table. The figure shows that the mean can be modeled as a linear function of net weight. (The variance can be similarly modeled.) The net length distribution for a given net weight was determined to be a gamma distribution. Mean Net Length (µm) Net Weight Fig 5. Mean net length vs. net weight. 4.2 Circuit Congestion The slopes of mean length and variance length vs. net weight are different for different designs, and incremental changes to the circuit topology do not overtly affect the slopes. The slopes were therefore assumed to be a function of the overall interconnect density or congestion of a circuit. A good measure of the congestion is the neighborhood population of a circuit. The concept of neighborhood population has been used previously to model interconnect lengths [5] and is defined here in the following way. Let Distance(cell,cell2) be the number of cells traversed in the shortest path between cells and 2 (in Fig. 4, Distance(a,g)=3). The neighborhood population of a cell at level i, Ngh(cell) i, is the number of cells residing within a distance i from the cell (in Fig. 4, Ngh(d) = {c,e,f,g,h} =5, and Ngh(d) 2 = {a,b} =2). The total neighborhood population at level i, Angh i, is the sum of the neighborhood populations for all cells at level i (in Fig. 4, Angh =22). An analysis of standard cell designs show that the slope of the mean of the net length vs. net weight correlates well with the total neighborhood population at level 3 (Fig. 6) [4]. Inserting this into the interconnect length model, the mean net length for a given net weight, l mean (net_weight), can be expressed as: l mean ( net_weight) = a m + b m ( Angh 3 )net_weight (5) where a m and b m are model parameters. (For the layout of the designs in Table a m =.3, and b m =4.95x0-5. The average error in estimating mean net length using this model was 8.64%.) Slope Mean Length/ Net Weight (µm) Angh 3 Fig 6. Slope net length vs. total neighborhood pop. 5.0 Interconnect Yield Model The interconnect yield model defines a wire as that part of an interconnect in a layout restricted to a single track in the interconnect channel. Wire density is the number of wires crossing a given cross-section of a layout. The interconnect yield model presented in this paper has been developed in the following way. First an analysis was performed on the wire density in a standard cell layout. Next, a relationship was developed between the wire density and the critical area. The wire density was then modeled as a function of net length. This in turn was used to model the critical area and hence yield as a function of a circuit s structural attributes. 5. Wire Density Fig. 7 shows an example of wire density of the metal (horizontal) layer for a typical standard cell design. The x axis represents the distance in microns along the bottom of the layout (lower left corner of the layout is the origin). The y axis gives the number of wires crossing a vertical cross-section of the die at discrete distances along the x axis. The number of cross-sections at which the number of wires is counted is 000. Wire Density Distance from lower left corner of die (µm) Fig 7. Wire density along x axis of die. It is apparent from Fig. 7 that the density of wires, i.e., the number of wires crossing a particular cross-section of the layout, remains relatively constant as x increases. Only at the far edges of the die does the wire density decrease rapidly to zero. 5.2 Wire Critical Area The critical area of the interconnects can be approximated by averaging the wire density and the spacing

5 between wires. Let N avg be the wire density averaged across the die: N cr N avg = N i N (6) i = cr where N i is the wire density at cross-section i, and N cr is the number of cross-sections at which the wire density is measured. Let s avg be the spacing between wires averaged across the die. The critical area for a given defect radius r o can then be approximated as: Acr ( r o ) dwn avg = ( 2r o s avg )WN avg (7) where d is the height of the critical area, and W is the width of the die (Fig. 8). The average spacing between wires is assumed to be a constant for a given place and route tool. Consequently, if (7) holds, the critical area for a given defect radius is proportional to the width of the die and to the average wire density. This is illustrated in Fig. 9 where the metal critical area at a defect radius of r o =0.8µm is plotted versus WN avg for the ten designs from Table. Metal Wire Critical Area: Acr(r) Critical Area (µm 2 ). 5.3 Wire Length The total wire length in Fig. 8 is N avg W. The total wire length, L, in the original die can be approximated by multiplying the mean net length for a given net weight by the number of nets with that net weight, and summing across all net weights: L = l mean ()n i i (8) i = net_weight where l mean is the mean net length for a given net weight i as calculated using (5); and n i is the number of nets with a net weight i. Substituting (8) for N avg W in (7), the critical area for a w W Fig 8. Critical area of wires. d s avg Number of wires: N avg 4e+5 6e+5 8e+5 WN avg Fig 9. Critical area (r o =0.8µm) vs. (die width)(# wires). given defect radius can be derived. Fig. 0 shows the critical area for a defect radius of 0.8µm plotted against the total interconnect length for the ten designs from Table. From this figure it is apparent that the critical area for a given defect radius r o correlates to L and can be expressed as: Acr ( r o ) = a A + b A l i n i (9) i = net_weight (The values of the model parameters, a A and b A, for the designs in Table are and 0.44, respectively, for a defect radius of 0.8µm.) Critical Area (µm 2 ) 5e+5 e+6 Total Interconnect Length (µm) 2e+6 Fig 0. Critical area (r o =0.8µm) vs. total net length 5.4 Interconnect Yield The yield of the designs can be modeled by inserting equation (9) into yield equation (4): Y = exp K a A + b l A mean ()n i i i = net_weight ( p ) ( p 2) ( r o r )rp 2 (0) where r is half the minimum spacing between metal lines; r o is the defect radius at which a A and b A are measured in (9); and l mean is the mean net length for a given net weight i as calculated from structural attributes in (5). To assess the validity of model (0), the estimated yields of the ten designs in Table are plotted in Fig.. The yields of the ten designs as estimated by model (3) are also plotted in this figure. The former are calculated using the interconnect length model, the latter are calculated using the extracted critical areas. The proximity of the data points in Fig. shows that the interconnect model provides a good estimate of the yields of the designs (mean error = 0.8%). This in turn shows that yield can be well estimated by structural characteristics taken from a netlist. To further assess the validity of model (0) a second design environment with a different placement algorithm was used to generate layouts of the circuits in Table. Attributes were extracted from the netlists and layouts and the model parameters were re-tuned. Their values were a A = -200 and b A = The results showed a mean error for yield as estimated using models (3) and (0) of 0.75%. 5.5 Yield for Additional Interconnect Layers The yield model above, (0), was developed for the metal interconnect layer. However, as mentioned in Sec-

6 Yield Yield - Model 3 Yield - Model Design Number Fig. Estimated metal yield for designs in Table. tion 3.2, for a given defect radius a correlation exists between the critical areas of the metal layers (Fig. 2). Consequently the yield for metal layers other than metal can be modeled as a function of the yield of the metal layer. This is demonstrated in Fig. 2 where the metal2 yields of the ten designs in Table are plotted. The yields are calculated using models (3) and (0). Model (3) estimates the metal2 yield from the metal2 critical area extracted directly from the layout. Model (0) estimates the metal2 yield using equation (0) and the constant of proportionality between the critical areas of metal and metal2 layers. Again the proximity of the data points demonstrates the validity of the yield model (mean error = 0.37%). Yield Yield - Model 3 Yield - Model Design Number Fig 2. Estimated metal2 yield for designs in Table. 6.0 Conclusion Any manufacturability assessment of an IC requires an accurate yield estimate. In this paper a new yield model has been presented. The yield model takes as input a standard cell netlist and provides as output an estimate of the defectrelated yield of the interconnect layers. The yield model has been used successfully to model the interconnect yield of standard cell designs generated with two different place and route tools. This yield model differs from other yield models in that it does not rely on data taken from a design s layout, i.e., data available only in the latter stages of the design process. Instead the model relies on data extracted from a design s netlist. This is especially useful since it allows designers to determine early in the design process the impact of their design decisions on yield and hence on an IC s manufacturability. References [] W. Maly, Computer-aided design for VLSI circuit manufacturability, Proc. of the IEEE, vol. 78, no. 25, pp , Feb [2] R.M. Warner, Jr., Applying a composite model to the IC yield problem, IEEE J. Solid-State Circuits, vol. SC-9, no. 3, pp , June 974. [3] W. Maly, H.T. Heineken, and F. Agricola, A Simple New Yield Model, Semiconductor International, pp , July 994. [4] H.T. Heineken, J. Khare, and W. Maly, Yield Loss Forecasting in the Early Phases of the VLSI Design Process, Custom Integrated Circuits Conference, pp , May 996. [5] G. Zimmermann, A new area and shape function estimation technique for VLSI Layouts, 25th IEEE/ ACM Design Automation Conference, pp , June 988. [6] F.J. Kurdahi and A.C. Parker, Techniques for area estimation of VLSI layouts, IEEE Trans. Computer- Aided Design, vol. 8, no., pp. 8-92, Jan [7] M. Pedram and B. Preas, Accurate prediction of physical design characteristics for random logic, IEEE/ACM 989 International Conference on Computer Design, pp , Oct [8] J. Khare and W. Maly, Inductive Contamination Analysis (ICA) with SRAM Application, IEEE International Test Conference, pp , Oct [9] W. Maly and J. Deszczka, Yield estimation model for VLSI artwork evaluations, Electron. Lett., vol. 9, no. 6, pp , March 983. [0] C. H. Stapper, Modeling of defects in integrated circuit photolithographic patterns, IBM J. Res. Develop., vol. 28, no. 4, pp , July 984. [] A.V. Ferris-Prabhu, Modeling the critical area in yield forecasts, IEEE J. Solid-State Circuits, vol. SC- 20, no. 4, pp , Aug [2] T.L. Michalka, R.C. Varshney, J.D. Meindl, A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy, IEEE Transactions on Semiconductor Manufacturing, vol. 3, no. 3, pp. 6-27, Aug [3] J. Khare, D. Feltham, W. Maly, Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits, IEEE Journal of Solid-State Circuits, vol.28, no. 2, pp , Feb 993. [4] H.T. Heineken and W. Maly, Standard Cell Interconnect Length Prediction from Structural Circuit Attributes, Custom Integrated Circuits Conference, pp , May 996. [5] M. Pedram and B. Preas, Interconnection length estimation for optimized standard cell layouts, Int. Conference on Computer-Aided Design, pp , Nov. 989.