A Low-Error Statistical Fixed-Width Multiplier and Its Applications

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1 A Low-Error Statistical Fixed-Width Multiplier and Its Applications Yuan-Ho Chen 1, Chih-Wen Lu 1, Hsin-Chen Chiang, Tsin-Yuan Chang, and Chin Hsia 3 1 Department of Engineering and System Science, National Tsing Hua University, Taiwan. Department of Electrical Engineering, National Tsing Hua University, Taiwan. 3 Industrial Technology Research Institute, Taiwan. cwlu@mx.nthu.edu.tw (corresponding author Abstract In this paper, an error compensation method for fixed-width two s-complement multipliers is proposed. According to the statistical analysis for the truncation term, a general form for different word length compensation circuit is made up. For example, the proposed 8 8 fixed-width multiplier achieves 15.65% accuracy compared with direct-truncation multiplier. Also, the proposed multiplier has 41% savings compared with post-truncation multiplier when it is implemented in a 0.18-μm process. As the proposed multipliers applying to discrete cosine transform (DCT design to demonstrate the system performance, the results show the proposed core can save 15% area with 9. db peak signal-to-noise ratio (PSNR penalty. Therefore, the proposed multiplier has a low hardware cost achieving high accuracy designs. Index Terms Low-error, Fixed-width, Two s-complement Multipliers, Statistical compensation. Fig. 1. An 8 8 Modified Baugh-Wooley s-complement multiplier example. I. INTRODUCTION Multiplier is a widely used component in the application of digital signal processing (DSP systems, such as the discrete cosine transform (DCT and the fast Fourier transform (FFT. In general, we obtain a n-bit output with two n-bit input from the multiplication. However, it is desirable to remain the same bit-width for the basic arithmetic operations in many applications. For this reason and to reduce the area cost of the circuit, the least significant half part is truncated directly. A large error would be produced after truncating, therefore several compensation methods for fixed-width multipliers to alleviate the truncation error effects are presented [1]-[11]. On the other hand, there are some people working hard to raise the speed [1]-[13]. At first, the constant value compensation methods are proposed in [1]-[3]. In these methods, the compensation value is just obtained by some probabilistic computation and can not adjust to the different multiplier inputs. Afterwards, [4]-[11] present adaptive value compensation methods for adapting various multiplier inputs. In [4], the error compensation value is generated by the sum of the most significant column of the truncated part. Then, Van et al. [6] make a lot of exhaustive simulation to proof that the most significant column is important for the estimation of the truncated part and modify the compensation method of [4]. To compare with the constant compensation value, the adaptive compensation value decreases the error and achieves better performance. In this paper, we utilize the result proofed in [6] and propose a new low-error fixed-width multiplier. To achieve better performance, some mathematical analysis and simulation are made. We exclude the partial products which are not relevant to the estimation in our analysis. The error performance can be improved by the proposed method with the respect to the previous compensation method. By this way, we can acquire the compensation value in advance and make a truth table for the combinational circuit [8]. This paper is organized as follows. In Section II, the fixed-width two s compliment multiplier is briefly described. The derived compensation values and circuit implementation are showed in Section III. Section IV compares the error performance of the different compensation methods. Finally, we make a conclusion in Section V. II. FUNDAMENTAL FIXED-WIDTH TWO S-COMPLEMENT MULTIPLIERS The two n bits two s complement integer numbers can be represented as follows. A = a n 1 n 1 + a i i (1 i=0 B = b n 1 n 1 + b j j ( j=0

2 TABLE I THE MEAN AND VARIANCES OF δ BY SIMULATION n θ E {δ} Var{δ} E {δ} Var{δ} E {δ} Var{δ} E {δ} Var{δ} E {δ} Var{δ} where a i,b i follows. {0, 1}. The product P can be expressed as P = A B = y (n 1(n 1 + y ij i+j + n 1 i=0 j=0 n 1 + y (n 1j j +1 j=0 + ( n 1 n 1 + y i(n 1 i +1 i=0 where y ij = a i b j and y ij means the binary inversion of y ij. The partial products of the 8-point modified Baugh-Wooley multiplier are shown in Fig. 1. III. PROPOSED ERROR COMPENSATION CIRCUIT In Fig. 1, the product P can be divided into two parts: the main part (MP that includes n most significant bits (MSBs and the truncation part (TP that has n least significant bits (LSBs, where n =8for this example. The eqn. (3 can be rewritten as follows. (3 P = MP + TP (4 The product P can get the n-bit MSB using a rounding operation called post truncation (Post-T, which is used for high-accuracy applications. It truncates the least significant n bits after all of the calculation. However, hardware cost increases in the very-large-scale integration (VLSI design. In general, the TP is usually truncated to reduce hardware cost in multiplier design, known as the direct truncation (Direct-T method. It truncates the least significant n bits directly without any calculation. Thus, a large truncation error occurs due to the neglecting of carry propagation from the TP to MP. In the following subsection, a low-error compensation value and corresponding architecture are make up. A. Derivation of Compensation Value From Fig. 1, the product P can be approximated as P = P c = MP + σ n (5 Fig.. The diagram of θ and G(θ. where σ is the compensation value from the TP to the MP as listed in Eqs. (6-(8. ( TPmajor + TP minor (6 TP major = y (n 10 + y 0(n 1 + y i(n i 1 (7 TP minor = i=0 j=0 i (n i 1 y (i jj (8 where Round ( is rounded to the nearest integer. The product is effected by TP major much more then TP minor due to the weight of the position when contributing towards the σ. Therefore, the compensation value σ can be calculated by obtaining TP major and estimating TP minor. In this way, TP minor can be derived as the function of TP major in order to reduce the computation complexity. Therefore, TP minor is approximated to F 3 (TP major shown as follows. TP minor = F 1 (a i,b j i, j 0 (n = F ( y(n 10, y 0(n 1,y i(n i 1 i 0 (n

3 TABLE II THE COMPENSATION VALUES OF DIFFERENT LENGTH WIDTH AND θ n θ I D I D I D I D I D = F 3 (y (n 10 + y 0(n 1 + y i(n i 1 = F 3 (TP major (9 Furthermore, because y (n 10 and y 0(n 1, those consist of a n 1 and b n 1, are not relationship with TP minor exactly, TP minor can be simplified as function G (θ. ( TP minor = G y i(n i 1 = G (θ where θ = y i(n i 1, and the sum of TP major and TP minor is expressed in the following equation. TP major + TP minor = TPmajor + G (θ = y (n 10 + y 0(n 1 + K (θ (10 where function K (θ =θ+g (θ, and the compensation value σ is summarized in Eqn. (11. ( y(n 10 + y 0(n 1 + K (θ (11 B. Statistical Analysis for Compensation Value Define δ = 1 K (θ. The δ is computed with different θ. Round ( mean ( δ θ, y (n 10 + y 0(n 1 1 = Round (I.d=I + Round (d ( D = I + Round where I and d are the integer and fractional part of the mean of δ which is shown in Table I, respectively. D is a binary value (0 or 1 depending on if the value of d is greater than 0.5 or not. The values of I and D in different length are simulated and tabulated in Table II. The reason we keep the Round ( D to substitute equation (1 to equation (11 but not compute the rounding value directly is that the approximate value can be more accurate. In the other hand, we exclude the situation of y (n 10 + y 0(n 1 =1because D would be insignificant. ( y(n 10 + y 0(n 1 + K (θ ( y(n 10 + y 0(n 1 + D = Round + I (1 C. Architecture for 8 8 Two s Complement Multiplier The circuit is implemented by using full adders (FAs and combinational circuit as shown in Fig. 3. First, we execute a truth table between the value of different θ and σ. Then, we can utilize the table to implement a combinational circuit. After the computation of θ by the combinational circuit, I part can be added to the column of P 8 directly and D part for the P 7 column from the simulation result we shown in Table II. The 1 in the P 15 column can be easily implemented by an inverter. IV. DISCUSSION AND COMPARISONS A. Comparison with Other Multipliers To compare the performance of the accuracy, we introduce the formula of the absolute mean error and maximum absolute error to calculate as below: ε = Avg { P P q } (13 ε max = Max{ P P q } (14 where Avg {} and Max{} are the average and maximum operators, respectively. The comparison of ε in different methodologies are displayed in Table III, and the maximum absolute errors are shown in Table IV. Besides, the gate counts (G c are shown in Table V. The results show that the proposed statistical compensation circuit saves relatively much area for the Post-T and the accuracy is much better than Direct-T. To compare with the other two methods, the proposed method sacrifices a slightly area for the better performance of accuracy.

4 Fig. 3. Architecture for the proposed error compensation 8 8 multiplier. TABLE III COMPARISONS OF ABSOLUTE AVERAGE ERROR ε WITH OTHER METHODS Length n =8 n =10 n =1 n =14 n =16 Direct-T (576 (816 (1331 (61440 (7858 Post-T 11.06% 9.08% 7.69% 6.67% 5.88% J-K [4] 9.58% 6.16% 3.4% 0.84% 18.88% Van [6] 18.39% 16.0% 14.60% 13.38% 1.41% Proposed 15.65% 14.8% 1.54% 11.5% 11.68% TABLE IV COMPARISONS OF MAXIMUM ABSOLUTE ERROR ε max WITH OTHER METHODS Length n =8 n =10 n =1 n =14 n =16 Direct-T (1793 (917 (45057 (1993 ( Post-T 7.14% 5.55% 4.55% 3.85% 3.33% J-K [4] 8.7% 6.07% 4.37% 3.18%.31% Van [6] 4.60%.84% 1.7% 0.94% 0.37% Proposed 1.47% 18.46% 17.9% 16.56% 17.1% B. Application of DCT In order to verify the performance of the proposed multiplier in real application, the proposed multiplier is implemented in a two-dimensional (-D DCT [14]. Also, peak-to-noise TABLE V COMPARISONS OF GATE COUNTS G c WITH OTHER METHODS Length n =8 n =10 n =1 n =14 n =16 Post-T (506 (806 (1175 (1559 (10 Direct-T 44% 45% 46% 48% 47% J-K [4] 5% 5% 5% 53% 51% Van [6] 5% 5% 51% 53% 51% Proposed 59% 60% 58% 55% 53% ratio (PSNR is an important data for evaluating the accuracy performance of DCT core. We chose ten test images for the comparison. They are all comprised of pixels with 8-bit 56 gray level data in each pixel. Table VI shows the comparison results of the PSNR and the gate counts (G c. To compare with the Post-T multiplier, the proposed method saves 15% G c with 9. db penalty. Furthermore, there are only 14% G c overhead for the better performance of PSNR with 15.9 db larger than Direct-T multiplier. Furthermore, the -D DCT with four proposed 14-bit multipliers uses the Synopsys Design Compiler to synthesize the RTL design and the Cadence SOC Encounter is adopted for placement and routing (P&R. Implemented in a TSMC μm CMOS process, the -D DCT core operates in 55 MHz and consumes power 1.9 mw. The core layout and simulated characteristics are shown in Fig. 4. TABLE VI COMPARISONS OF ACCURACY AND GATE COUNTS G c IN DCT APPLICATIONS Post-T Direct-T Proposed Image Image Image Image Image PSNR Image Image Image Image Image Average K 16.4K 19.7K G c (100% (71% (85%

Fig. 4. μ μ μ The core layout and characteristics of -D DCT. V. CONCLUSION A low-error fixed-width array multiplier is proposed in this paper.

Then we can achieve better performance of accuracy by implementing a combinational circuit with the truth table. The multiplier is implemented in a 0.18-μm process.

Therefore, the proposed multiplier achieves not only higher accuracy but also lower area cost. [9] C. Y. Li, Y. H. Chen, T. Y. Chang, and J. N.

5 Fig. 4. μ μ μ The core layout and characteristics of -D DCT. V. CONCLUSION A low-error fixed-width array multiplier is proposed in this paper. The compensation value is derived by simulation in limit situation and filled into a truth table via different θ. Then we can achieve better performance of accuracy by implementing a combinational circuit with the truth table. The multiplier is implemented in a 0.18-μm process. The results have demonstrated that the proposed array multiplier can achieve higher accuracy comparison with Direct-T method and save areas with Post-T multiplier. Therefore, the proposed multiplier achieves not only higher accuracy but also lower area cost. [9] C. Y. Li, Y. H. Chen, T. Y. Chang, and J. N. Chen, A probabilistic estimation bias circuit for fixed-width Booth multiplier and its DCT applications, IEEE Trans. Circuits Syst. II, vol. 58, no. 4, pp , Apr [10] Y. H. Chen, C. Y. Li, and T. Y. Chang, Area-effective and powerefficient fixed-width Booth multipliers using generalized probabilistic estimation bias, IEEE J. Emerging Sel. Topics Circuits Syst., vol. 1, no. 3, pp , Sep [11] Y. H. Chen and T. Y. Chang, A high-accuracy adaptive conditionalprobability estimator for fixed-width Booth multipliers, IEEE Trans. Circuits Syst. I, vol. 59, no. 3, pp , Mar. 01. [1] A. G. M. Strollo, N. Petra, and D. DeCaro, Dual-tree error compensation for high performance fixed-width multipliers, IEEE Trans. Circuits Syst. II, vol. 5, no. 8, pp , Aug [13] J. Y. Kang and J. L. Gaudiot, A simple high-speed multiplier design, IEEE Trans. Comput., vol. 55, no. 10, pp , Oct [14] S. C. Hsia and S. H. Wang, Shift-register-based data transposition for cost-effective discrete cosine transform, IEEE Trans. VLSI Syst., vol. 15, no. 6, pp , Jun ACKNOWLEDGMENT The authors would like to thank the National Chip Implementation Center (CIC, Taiwan, for providing the electronic design automation tools. This work was supported in part by the National Science Council under project number NSC E and NSC E , and Industrial Technology Research Institute (ITRI, Taiwan, under project number B356AE110. REFERENCES [1] Y. C. Lim, Single-precision multiplier with reduced circuit complexity for signal processing applications, IEEE Trans. Comput., vol. 41, no. 10, pp , Oct [] M. J. Schulte and S. E. E. Jr., Truncated multiplication with correction constant, in Proc. IEEE Workshop VLSI Signal Process., Oct. 1993, pp [3] S. S. Kidambi, F. El-Guibaly, and A. Antoniou, Area-efficient multipliers for digital signal processing applications, IEEE Trans. Circuits Syst. II, vol. 43, no., pp , Feb [4] J. M. Jou, S. R. Kuang, and R. D. Chen, Design of low-error fixedwidth multipliers for DSP applications, IEEE Trans. Circuits Syst. II, vol. 46, no. 6, pp , Jun [5] S. E. E. Jr., Truncated multiplication with approximate rounding, in Proc. 33rd Asilomar Conf. Signals, Syst., and Computers, vol., 1999, pp [6] L. D. Van, S. S. Wang, and W. S. Feng, Design of the lower error fixed-width multiplier and its application, IEEE Trans. Circuits Syst. II, vol. 47, no. 10, pp , Oct [7] L. D. Van and C. C. Yang, Generalized low-error area-efficient fixedwidth multipliers, IEEE Trans. Circuits Syst. I, vol. 5, no. 8, pp , Aug [8] Y. H. Chen, T. Y. Chang, and R. Y. Jou, A statistical error-compensated Booth multiplier and its DCT applications, in Proc. IEEE Region 10 Conf., 010, pp

FIXED WIDTH BOOTH MULTIPLIER BASED ON PEB CIRCUIT

FIXED WIDTH BOOTH MULTIPLIER BASED ON PEB CIRCUIT Dr. V.Vidya Devi 1, GuruKumar.Lokku 2, A.Natarajan 3 1 Professor, Department of ECE, A. M.S. Engineering college, T.N., India vidyapeace@gmail.com 2 VLSI