U100. cgen_by BYPASS. cgen_cp CLK_FPGA_P (OUT0A) OUT0 CLK_FPGA_N (OUT0B) OUT0 (OUT1A) OUT1 (OUT1B) OUT1 (OUT2A) OUT2 U10 DS90LT012AH (OUT2B) OUT2
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- Hilda Hill
- 5 years ago
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1 9 0 TX nternal Reference loop filter for internal V vco_cp R.0 vco_vtune loop filter for VX vcxo_cp R0 0 vcxo_vtune V_TX: 0 0u VTX Vcc X UT /TU V_TX: R 0 0n p cgen_int_ref p vcxo_clk R 0 refer Ref ode (Ref TX) cgen_ext_ref 0 R vco_vtune cgen_int_ref 0 9 R (R) R (R) U00 YSS (UT0) UT0 (UT0) UT0 (UT) UT (UT) UT (UT) UT (UT) UT (UT) UT (UT) UT 0 0 cgen_by cgen_cp U0 S90T0 V: : _ V: cgen_by 0 0p 0 00p R. 0 0n 0 00p 0 0p 0p vcxo_cp cgen_cp vco_cp R. p ssume kz/volt kz loop bandwidth 0 kz compare frequency.m current (UT) UT (UT) UT cgen_clk_test 0 R R0, 0z xternal Reference T00 R0 9.9 cgen_clk_test R Test put.9 R cgen_ext_ref (UT) UT 9 (UT) UT (UT) UT (UT) UT (UT) UT (UT) UT (UT) UT (UT) UT (UT9) UT9 (UT9) UT9 (UT0) UT0 (UT0) UT0 (UT) UT RST RST (UT) UT clock_db_tx_p clock_db_tx_n clock_db_rx_p clock_db_rx_n vcxo_en vcxo_vtune vcxo_en X Vtrl / VX_ V / UT V_VX: vcxo_clk 0u S eader V_: cgen_spi_sen cgen_spi_sclk cgen_spi_mosi cgen_spi_miso cgen_st_refmon cgen_st_ld cgen_st_status S nput R U0 Y SUT S_ R. R. cgen_ref_sel cgen_sync_b R n R Vcc cgen_spi_sen cgen_spi_sclk cgen_spi_mosi S S/S S/S R_S SY U00 R STTUS cgen_st_refmon cgen_st_ld cgen_st_status cgen_spi_miso S 9 TR V_: R0 0 R00 _ S S ock UT 0 S UT U00 9X UT_ R9 UT_ R0 ake sure these resistors are close to U R R0 TT : clock.sch S0 S,S0 igh = S ode 0 S R igh = oad at power up R reset and power down: internal pullups, active low $ate$ USR mbedded lock eneration 0 RVS: RW Y: $Rev$ $uthor$ RST
2 9 0 _V_R: u ulseack 0 R0 0 R R0 9.9 R 9.9 R 9.9 U00 9 X00 VTX 0 T_ T+ XT/ UT Vcc T_T T_ T T+ XT /TU V_: V_: S/ S/ R_ R_T R_ T XRS 0 R0. R0. R0. U00 9 TR R0. V_: 0 S round Right athode Right node eft athode eft node 9 0 eth_led eth_led R 0 R 0 R00. % overo_gpio overo_gpio nrst R S n n n R0 eth_led eth_led R0 0 U0 9x S S n/c n/c 9 /S V_: : 0 TST X_ R0 0 U00 9 WR _V_R: VddR Vdd Vss _V_R: V_: _V_R: 9 Vdd Vdd VddR VddR Vdd VddVR VddVR 0 VddVR VddVR 0.0u 00 _V_R: 0.u _0 _9 _0 _ nr nwr ns _S 0 9 W _S 0 9 US U00.u 0.0u 0.0u 9 0.0u ecouple ore with.u cap near pin 9 0 USR mbedded thernet TT $ate$ : ethernet.sch RVS: $Rev$ 0 RW Y: $uthor$
3 9 0 0 UT_ UT_ R UT_ UT_ UX UX V_ 9 0 UX UX V_ UX R UX VR UX UX V_ 9 0 UX V_ UX UX UX UX UX R U00 9X UX UX UX UX UX UXR ST UX UX UX S UX UX UX V: V: 9 0 V: V: V: V: 9 0 V: V: S R0 00 R0 00 UX io_tx_00 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_09 io_tx_0 io_tx_ io_tx_ io_tx_ io_tx_ io_tx_ db_sen_tx db_mosi_tx db_miso_tx 9 0 db_sclk_tx 9 0 db_sda db_scl clock_db_tx_a 9 0 V: ddress db_sen_rx db_mosi_rx db_miso_rx db_sclk_rx clock_db_rx_a V: io_rx_00 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_09 io_rx_0 io_rx_ io_rx_ io_rx_ io_rx_ io_rx_ 09 or U R00 00 R 0 or U 0 u.0 9X TR S R 0 u U00 R_ R_ RT_ RT_ VR u 0u 0 0u VR R 00 U : R R U : R R R clock_db_tx_p clock_db_rx_p USR mbedded aughterboad nterface clock_db_tx_n clock_db_rx_n TT $ate$.9 n n n n.9 : dboard.sch RVS: $Rev$ orner freq 00z, d/octave 9 0 orner freq 00z, d/octave p p 0 RW Y: $uthor$ 9 0
4 : U io_rx_ io_rx_ Y _0_ W _0 _ U00 9X TX io_rx_ io_rx_ io_rx_ io_rx_0 io_rx_09 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 _ _ V _0_ W _0 0 0_ U9 _0_ V0 _0 W0 _ Y _ Y _ Y _/VR /VR /VR_ V _/VR_ W _/VR_ W9 _/VR_ W UT_ UT_ UT_ UT UT_ \\TX UT TXSY 0 _UT_ TX0 0 9 UT TX 9 TX TX TX TX TX TX TX TXSY TX00 TX0 TX0 TX0 TX0 TX0 TX0 TX0 _0_ aux_sdi_codec _0_ aux_sdo_codec _0_ aux_sclk_codec _0_ reset_codec _0_ sen_codec _0_ mosi_codec _0_ miso_codec _0_ sclk_codec _0_ U /VR /VR /VR 0_/VR /VR io_rx_0 io_rx_0 io_rx_0 io_rx_00 io_tx_ io_tx_ io_tx_ io_tx_ io_tx_ io_tx_0 io_tx_09 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_00 U /VR_ W V /VR_ Y Y9 Y 9_ XS00S _9_ U _0_ W Y U U 9 9 V U Y _9_ Y _9_ 0 _0_ V_ 9 V_ V_ V_ 0 _0_ V9 V_ V V_ V_ V_ V_ V_ TX TX9 TX0 0 TX 9 TX TX 9X RX U00 V 0 V 9 0 V 0 0 V TX0 TX09 TX0 TX TX TX RXSY TX _ R R R T _9_ T _9 U T _9_/VR 9_ Y XS00S 0 TX U _0_ 0 TX T _0_ TX0 R TX09 V 9 TX0 U RXSY 9 RXSY TX0 T 9X TR U00 TX0 TX0 R W S sclk_codec TX0 Y S miso_codec TX0 V S mosi_codec TX0 V S_ sen_codec TX0 W RST reset_codec TX00 W UXSdo 9 aux_sclk_codec TXSY U UXSclk 9 UXScsb 9 aux_sdo_codec aux_sdi_codec TX V_ U V_ V_ V_ V_ V V_ XS00S T U XS00S U Y0 / S / Y / /0 / _9_/RY/ / _9_/ UT_ V / _0_/ UT_ U /0 _0_/ / / /TRY/ TT $ate$ fpga_codec.sch USR mbedded and s RVS: $Rev$ RW Y: $uthor$
5 9 0 debug_led fpga_cfg_done slot= slot= R0 R09 convert fpga config outputs V_:.. R00 R0 overo_cfg_done_b 0 fpga_cfg_done R 0 0/U_ pullups enabled m[0:] = serial slave U _0_/0 _0_/ _0_/S 0_/ _0_/VS _0_/RWR 09_/VS0 _09_/VS / R R U R V W Y 9 fpga_txd fpga_rxd 0 / 0 XS00S / U0 convert fpga config inputs U0 V_: / _0_/S/S /UT V V overo_cfg_din 0 R09 R0 Y SUT Vcc U0 fpga_cfg_din overo_cfg_init. R0. R0 fpga_cfg_init_b /W R / /T / / / V9 SUS /0//S Y W Y9 Y V W debug_led fpga_cfg_init_b fpga_cfg_cclk fpga_cfg_din overo_cfg_cclk 0 R0 R0 Y SUT Vcc fpga_cfg_cclk fpga_cfg_done fpga_cfg_prog_b V_:. R0 overo_cfg_prog_b 0 R0 R0 U0 Y SUT Vcc fpga_cfg_prog_b 0 X T Vref/Vref R/TS /T one/t 9 in/t 0 TS T T T R0 R0 R0 R R0 0 R0 0 R00 0 XS00S T T T T TS U / T/ TT $ate$ USR mbedded onfig : fx.sch 0 9 RVS: RW Y: $Rev$ $uthor$ 0
6 : U debug connector cgen_ref_sel U9 _0_/ /VR_ T debug_clk0 0 0 debug_clk cgen_sync_b U _0_/ debug 0_/0 debug_0 Y _0_/ _0_/VR_ W0 _0_ W _0_/VR_ U debug_ [] [] debug_ debug_9 V0 _0_/ _0_ V debug_0 9 [] [] 0 debug_ debug_ W9 _0_/0 /VR_ cgen_st_refmon debug_9 [] [] debug_ debug_ T _0 R cgen_st_ld debug_ debug_ [] [] [] [] debug_ debug_ debug_ debug_ T _0_ Y _0 0 /VR_ R cgen_st_status debug_ [] [] debug_0 debug_ W _0 debug_ 9 [] [] 0 debug_09 debug_ R0 _0 /VR_ debug_ [0] TR [0] debug_0 debug_ R9 _0 debug_ [] 0[] debug_0 debug_ T0 _09 debug_ [] 0[] debug_0 debug_0 U0 _09 0 debug_ debug_0 debug_9 debug_ debug_ [] 9 [] [] [] [] 0[] 0[] 0 0[] 0[] 0[] debug_0 debug_0 debug_0 debug_0 debug_0 debug_9 R _0_ debug_ 9 _0_ debug_ U debug / debug / /VR 9 9_/VR_ debug_pb0 push button debug_pb0 S0. R00 debug_ [0] 9 0 0[0] debug_00 debug / debug_ R / debug_ 9 / debug_ 0 / debug_0 /9 debug_09 / debug_0 / debug_0 /0 XS00S debug_0 debug_0 9 debug leds 0 debug_0 0 / debug_0 0 / debug_0 / debug_led slot= R debug_0 / debug_00 debug_led0 debug_led _9_/ debug_led debug_led0 slot= slot= R09 R0 cgen_spi_sen cgen_spi_sclk cgen_spi_mosi cgen_spi_miso R R R R debug_led _9_/ 0 _0_/9 9 _0_/ cgen_sen_b 0 cgen_sclk 9 cgen_mosi cgen_miso db_sen_tx db_mosi_tx db_miso_tx 0 db_sclk_tx db_sen_rx 9 / db_mosi_rx 0 /0 db_miso_rx / db_sclk_rx /.. R0 R0 db_sda db_scl / 9 / V_ V_ V_ V_ V_ V V_ db_scl db_sda XS00S R U debug_clk /R debug_clk0 /R0 0 _9_/TRY/R _9_/R 0 _0_/R _0_/R /R /RY/R TT $ate$ fpga_debug.sch USR mbedded and ebug RVS: $Rev$ RW Y: $uthor$
7 : U S0 VX 0 vero 0 VX 0 vero _0 0 _0 9 _0_0 9 _0_0 _0_0/VR_0 _0_0/VR_0 0/VR_0 _U_RST 0 0 SR 9 SR VSYST VSYST _ 0 _ 9 9 _0_0 _0_0 0/VR_0 0/VR_0 _0 _ S VSYST S _S _S_T0 _WT0 _S _WT0 _S _0_0 _0_0 _0 0 _0 0 VSYST _S _S _S0 _S0 0_0 _0 0 WR WR _W _nw _0 _0 0_0 _0 0 _V V S _S _9 _0_0 _0 _ overo_gpio0 overo_gpio0 _TS_R 9 0_WU _ overo_gpio _ 9 _T_R _W _9 _W _9 _0 0_0 9 _0_0 _0 0 _0 _9 _0 _S 0 S 9 overo_gpio 0 _T0_RST _ 0 _0_0 _0 _S0 _ _0 0_0 _0 _S SYS 9 SYS _ 9 _0_0 _0 _S _S overo_gpio S _S_S 09_0 _09_0 _0 0 _0 _S _S _ 9 0 _0 _V 0_0 _0 overo_gpio _T W _T0_W overo_gpio _0 _0 _9 _9 0_0 _0/VR_0 SYS UST_VUS US_T_VUS _W 0 overo_gpio T9_W 9 VU VU _ _ 0 0 W 0 overo_gpio _T_W 0 _ 0 WT0 0 overo_gpio _R_TS 9 W 9 0 WR overo_gpio0 _ overo_txd _TX _ 9 _RX 0 W _ overo_rxd XS00S 0 UST_ US_T_ overo_gpio _T0_R 00 0 R_TX _R_TX 90 0 _0 0 _S_S overo_cfg_done_b 0 0 _9 9 9 _S_S0 _S_S overo_cfg_din 9 0 _9 _ S W0 _S overo_gpio _US_ 9 T _S S_S overo_cfg_cclk overo_cfg_prog_b overo_rxd overo_txd 0 0 _ 0 0 UXR R overo_gpio 0 T _S_R overo_cfg_init 9 0 R_RX _R_RX 0 0 overo_gpio0 0 _SU_ 9 _SU_ US_VUS US_VUS 0 9 overo_gpio0 9 0 VSY 0 UX UST US_T_ US_ US T T overo_gpio overo_gpio overo_gpio overo_gpio 0 0 _SY UST_ US_T_ US_ US_ 9 overo_gpio 0 overo_gpio 0 overo_gpio 0 overo_gpio 0 overo_gpio0 0 overo_gpio 0 overo_gpio 0 overo_gpio 0 overo_gpio _9_0 overo_gpio _9_0 overo_gpio _0_0 overo_gpio V_0 _0_0 0 V_0 V_0 V_0 9 V_0 V_0 V_: XS00S T U / 0/ 9 0/ 9 0/ _9_0/9 0 _9_0/ _0_0/ _0_0/0 TT $ate$ fpga_overo.sch USR mbedded and vero nterface RVS: $Rev$ RW Y: $uthor$
8 9 0 V_: R0 0 R0 0 _0 _9 _0 _9 _0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R9 0 R0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R9 0 R0 0 R 0 R 0 R 0 R 0 _S _VSY _SY R0 0 R0 0 R0. R0 0 R0 0 R09 0 R0 0 + T0 T T 0 T 9 T T T T T T9 T0 0 T T T T T T T T 0 T9 9 T0 T T T VSY SY VR 9 /T S/ 0 S/RST T// T// T// S/S S/S V driver V V V: V T0 0 T TV T TV: 9 TV T U900 T TX+ TX TX+ TX TX0+ TX0 TX+ TX T RSRV dvi_tx_p dvi_tx_n dvi_tx_p dvi_tx_n dvi_tx0_p dvi_tx0_n dvi_txc_p dvi_txc_n R 0 0 fpga_txd fpga_rxd _S _S TV: V+ Vcc V Tx n 0 Tx n S S U90 X + Rx Rx n Tx 9 Rx Rx n + Tx V_: Vref Vref dvi_tx_p dvi_tx_n dvi_tx_p dvi_tx_n dvi_tx0_p dvi_tx0_n dvi_txc_p dvi_txc_n _S_V _S_V evel Translate or, maybe V: 90 U90 S S 0 0 R 00 connector + S + S 0+ 0S S X S S +V 9 S RS S_TX. R _S_V _S_V S_RX R U90 xx 0 n/c S S 0 /S V_: : S _S. R isc vero eader (ic & ) V: _SU. R V_: U90 ain VU 0 V_: SYS WR VU attery ackup R9.u 0 V_: 0. R R R0. Use jumpers to select or ine in 0 R0 R 0 R ain_r R V: US_T_VUS V: 00 R00 0 V_: T_VUS T_ T_ T_RST TT : overo.sch V 9 V US US 9 RST US to serial URT S S ual udio ack (ine n/) Tip=eft Ring=Right Sleeve=round 0 US_VUS STS0 0 0u 0 0u USR mbedded vero eripherals $ate$ 0 RVS: RW Y: $Rev$ $uthor$ 0 0 TR 0 0.0u 0 TST SR S 0.0u 0 ain_r ain_ T TX RX RTS TS TR SR R US0 US US US US u u u u U US T US_T_ US_T_ US_T_ US ost 0 US_ US_ R_RX R_TX STX top_sleeve top_ring top_tip bot_sleeve bot_sleeve_s bot_ring bot_ring_s bot_tip
9 9 0 power supply v V: fpga internal.v V:. R9 90 V: p n 90 V: 90 00u V: U000 T9 900 usb host and hdmi connector v T ltc0_intvcc 9 R90 sync/mode=intvcc n 0 9 R90 0 R90 R90 R90. 0p V_: R R90 0 V: SY/ RT T V RU 9 TR/SS S V V T0 0 U00 TV ST SW SW 9 u 99 u ltc0_intvcc n 909 u u u V_: 9 00u slot= u n S R p 9.u R90.9 V: digital.v U00 T0. T9 V: analog.v U00 T0. T9 V: clock gen.v V_: V_: 90 V: clock.v V U00 T0. T9 V_: 9.u 9 9 u 9 9 0p 9.u 90 0p 90 V 90 u p 9 9 0p 9 9 0p 9 u 9.u 9 V 9 u p hdmi driver.v TV: 90 V: 9 9.u overo gpio.v n n S V_: U00 R90. R90 9 T9 0p 9.u V_: p tcxo.v 90 9 V_TX: 9 0p 9 u V_: 9 9 0p vcxo.v V_VX: 9 0p 9 u TT : power_gen.sch $ate$ 9 USR mbedded ower eneration RVS: RW Y: 9 $Rev$ $uthor$ 90 9
10 fan connector v 000 V: p 0p 0p 0p 0p 0p 0p 0p TT 0 USR mbedded ower pplication $ate$ : power.sch RVS: $Rev$ 0 0 RW Y: $uthor$ VUX VUX VUX VUX VUX VUX VUX 0 VUX VUX VUX VUX VUX VUX VUX VUX 9 VUX VUX VUX T9 VUX T VUX T VUX V VUX V VUX W VUX VT VT 9 VT p 0p 0p 0p 0 S power connector v V: XS00S WR U V_: VS VS VS VS VS VS 0 VS VS VS 9 VS VS VS 0 VS VS V U00 9 WR V_: p 0p 0p 0p 0p 0p 0p 0p 0p 0p p 0p 0p V_: VT VT VT VT 0 VT VT VT 9 VT VT VT VT VT 0 VT VT VT 9 VT VT VT VT VT 0 VT VT VT 9 VT VT VT VT R VT R0 VT R VT R VT T VT T VT R R R9 R R R R T T T0 T T T T9 T U U U W W W Y Y0 V_: 900 V: 0 u p 0p 0p 0p 0p 0p 0p 0p 0p 0p 0p U00 9X WR 9 V 99 V 0 V 0 V V V V V V 0 V V V V V V V V V V 9 V V 9 V 00 0p
Inverted Input A to make routing easier fix in FPGA U2 ADS62P4X LVDS ADC
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