Shandong Qingdao , China. Shandong Qingdao, , China

Transcription

1 2016 Inernainal Cnference n Maerials, Manufacuring and Mechanical Engineering (MMME 2016) ISB: Min Cnrl Sysem f C Turre Punch Feeding Mechanism Based n Min Cnrl Card Ai-xia CAO 1, Pei-si ZHOG 2, ing-ying HA 3, Shu-hui DIG 2 and i ZHEG 1,2 1 Cllege f Traffic and Ship Engineering, Qingda Huanghai Universiy, Shandng Qingda , China 2 Advanced Manufacuring Technlgy Cener, Shandng Universiy f Science and Technlgy, Shandng Qingda, , China 3 Feicheng. 6 Senir Middle Schl, Shandng Taian, , China Keywrds: C urre punch, Min cnrl, Feeding mechanism. Absrac. Accrding he characerisics and requiremens f C urre punch feeding mechanism, he pen C sysem archiecure is cnsruced based n he mde f PC and min cnrl card. The srucure f hardware sysem is buil wih DMC1410 min cnrl card. The mvemen paern f rapezidal velciy curve and S velciy curve are analyzed. The flw char and he sfware mdule f min cnrl sysem f C urre punch feeding mechanism are presened. Under he suppr f MFC prvided by VS2015 and mvemen funcin library prvided by DMC1410 min cnrl card, he sfware f min cnrl sysem is develped. Inrducin Min cnrl is he inerdisciplinary cmprehensive echnlgy and he cre f mechanrnics. The psiin cnrl is usually realized by usingl singlechip r micrcmpuer direcly, bu is peripheral circui srucure is cmplex and a lng develpmen cycle is needed. The requiremen f cnrl accuracy and speed becmes mre sric and higher, and he radiinal cnrl sysem can n mee he demand develp prduc quickly. Wih he develpmen f cnrl echnlgy, a grea variey f min cnrl cards n he marke mee he requiremen f quick speed and high precisin which are very suiable fr he develpmen f min cnrl sysem fr special C equipmen. The min cnrl sysem in he paper includes PCI-DMC1410 min cnrl card based n PCI bus funcin library, micrcmpuer, serv mrs and s n. Accrding he planning pah and min parameers, he able f C urre punch mves desired psiin [1, 2]. The abve min cnrl sysem has he characerisic f gd reliabiliy, pen and universaliy and can be explaned easily all kinds f develpmen f min cnrl sysem such as engrving machine, C machine l and s n. By using MFC f VS2015, he min cnrl sysem f C urre punch press feeding mechanism is develped. The Hardware f Min Cnrl Sysem f Feeding Mechanism Inrducin f DMC1410 Min Cnrl Card DMC1410 is a kind f pulse min cnrl card based n PCI bus which is made by Shenzhen Leadshine Technlgy C., ld. And he card can realize up fur sepper/serv mrs cnrl. The srucure f DMC1410 is shwn in fig.1. Is PCI bus is an advanced high-perfrmance reusable lcal bus 32/64 bi address bus wih plug and play hardware linear inerplain, S speed cnrl curve and her funcins. Is lcain insrucin can upu single channel pulse (pulse + direcin) r dual pulse (CW pulse + CCW pulse) mde wich is a differenial r single ype signal [3, 4]. DMC1410 min cnrl card has he characerisics f high inegrain, high reliabiliy and s n. 78

2 The DMC1410 min cnrl card can finish cninuus rajecry and pin mvemen. The speed cnrl and psiin cnrl are realized by pin mvemen. The psiin cnrl mde cnains w kinds f accelerain and decelerain mde: ladder curve accelerain and decelerain and S curve accelerain and decelerain. PCI bus Cnrl chip wih PCI bus Cnrl chip fr special min Rev. Sp he STA/STP a he same ime Exernal inpu +24V Islain n islain Figure 1. The srucure f DMC1410. The Srucure and Principle f Sysem Hardware The shee unsacking is he firs prcess f aumaic punching. When he shee is ranspred frm sck shp shee punching wrkshp, he shee is separaed wih he shee separain device f aumaic feeding mechanism, hen grabbed wih he shee grab device, and finally pu he designaed psiin. The shee feeding mechanism requires precise psiin and angle psiining in he prcess f shee crawl, unsacking and placemen. As high precisin and speed are needed in he prcess f shee meal grasping and placing, he radiinal cnrl sysem can n mee he higher requiremens. The hardware f he min cnrl sysem cnsiss f he fllwing fur pars: min cnrl card, PC, serv drive and serv mr as shwn in fig. 2. The min cnrl card uses DMC1410 fur axis min cnrl card. The mdel f serv drives is Kinc ED-430 and he mdel f small ineria hree phase serv mr is +60S XXX-4LG. PC and min cnrl card cnsiue he cnrl uni. The PC mainly manages he infrmain flw and daa flw, cnrls he real-ime sysem mniring and human-cmpuer ineracin. The dedicaed CPU n he min cnrl card and PC cnsiue a maser-slave cnrl srucure. The mvemen cnrl card cnrl aumaic lifing f feeding mechanism, upu f he pulse and direcin signals, deecin f rigin and limi signals and s n. The drivers are cnneced wih he inerface bard f he min cnrl card, he speed is cnrlled by he encder, and he pulse signal received frm he min cnrl card cnrls he perain f mrs hrugh he inernal circui. S a half clsed lp serv cnrl sysem is cnsiued. Min cnrl funin library PC CPU Operain and implemenain plafrm PC bus Inerface f PCI bus Mechanical inerface Min cnrl card General inpu Min cnrl micrprcessr Sae feedback cnl pulse/direcin upu ±EL ±SD ORG IPUT PULL/DIR/OUTPUT Three axis cnrl pulse inerface Digial signal inerface X axis driver axis driver Z axis driver Figure 2. The hardware srucure diagram f mvemen cnrl sysem. X axis serv mr axis serv mr Z axis serv mr Limi swiches, pical encder, ec The Min Mde f Trapezidal Velciy Curve Trapezidal velciy curve is shwn in fig. 3 which is used in general psiin cnrl. In he prcess f his min mde, he able accelerae in a cnsan accelerain, he sar mving a cnsan speed when he speed achieves a specified value, and deceleraes in a cnsan accelerain afer running a cerain disance. The rapezidal velciy curve includes hree sages: cnsan accelerain phase, unifrm phase and cnsan decelerain sage. 79

3 The running speed changes wih rapezidal curve as he ineria f he able. I is impssible ha he mr rr r he able achieve he specified speed in an insan, herefre, here mus be a cerain accelerain prcess. During he accelerain and decelerain prcess f he rapezidal curve, he speed urning and he crrespnding accelerain muain are shwn in fur mmens: saring up, reaching he se speed, slwing frm he maximum speed and spping. The main advanages f accelerain and decelerain accrding he rapezidal curve are ha he arge psiin and velciy can be aumaically mdified in he mvemen prcess, he cnrl mehd and he calculain are simple suiable fr real-ime perain, and he accelerain and decelerain ime is shrer. This mehd is applicable he cnrl sysem wih slw prcessing speed and less reqiremen accelerain and decelerain. The Min Mde f S Velciy Curve The accelerain f S ype velciy curve is a cninuus change prcess as shwn in fig. 4. As he accelerain r decelerain increases r decreases linearly, he mechanical min sainariy f S ype velciy curve is beer. v v Wrk speed Accelerain a Decelarain Accelerain Decelarain a Accelerain Decelarain Figure 3. Trapezidal velciy and accelerain curve. Figure 4. S velciy and accelerain curve. The prcesses f accelerain and decelerain in his min mde are symmerical, and he whle running prcess is divided in seven sages: increasing accelerain phase, unifrm accelerain phase, decreasing accelerain phase, unifrm speed phase, increasing decelerain phase, unifrm decelerain phase, decreasing decelerain phase. Frm he S velciy and accelerain curves, he cnclusin can be drawn ha he velciy and he accelerain are cninuus funcins f ime. This min mde has small impac and small nise, and he service life f mr and mechanical sysem can be prlnged. The psiin and velciy can be mdified a any ime during he running prcess wih he rapezidal curve, and he psiin can be mdified wih he S curve. In he case f equal accelerain, he accelerain and decelerain ime is shrer wih he rapezidal curve and he mvemen is mre smh wih S curve. S he accelerain and decelerain mde shuld be chsen accrding he specific applicain. The Sfware f Min Cnrl Sysem f Feeding Mechanism The Mdular Design f Min Cnrl Sysem The verall srucure f he sfware uses mdular design which is easy mainain and upgrade [5]. Accrding he idea f mdular design, he sfware f min cnrl sysem f feeding mechanism is divided in he fllwing mdules as shwn in Figure 5: (1) Iniializain mdule, iniialize he min cnrl sysem f feeding mechanism including he iniializain f inerface, min cnrl card and her parameers. (2) Parameer seing mdule, se he relevan velciy, accelerain, psiin f feeding mechanism. 80

4 (3) Min cnrl mdule, realize he min cnrl f he whle feeding mechanism, including he selecin f min mde, receiving signal f limi and swich, reurning zer, sending min cmmand min cnrl card and s n. (4) Saus display mdule, display all kinds f real-ime infmain including he display f mvemen saus, velciy, accelerain, ec. (5) Sysem managemen mdule, including he managemen f files, C prgrams, samping dies, faul and alarm infrmain, ec. main prgram Iniializain mdule Parameer seing mdule Min cnrl mdule Saus display mdule Sysem managemen mdule Figure 5. The mdule diagram f min cnrl sysem sfware. Accrding he demand f he peraing prcess f he Feeding Mechanism, he flw char f he min cnrl sysem is designed as shwn in fig. 6. When saring he sysem, he iniializain is dne and hen check if he iniializain is crrec. If i is errr, dispaly he errr message and he iniialize he bard again, and if i is crec, cninue se he min parameers including X,, Z axis min cnrl pulse upu and he speed f he pulse. Afer finishing he parameer Seings, sarup he min, implemen he cnrl prcedure, and saus display mdule displays he mn saus including speed, lcain and her infrmain. Each funcinal mdule f he min cnrl sysem f feeding mechanism is crdinaed and cnrlled by he main frame prgram cnsiue a cmplee crdinaed min cnrl sysem. Sar Iniialize he bard Parameer f inerface Parameer f min cnrl Seing f velciy Seing f accelerain Seing f psiin Selecin f min mde Receiving signal f limi and swich Sending min cmmand Display f mvemen saus Display f velciy Display f accelerain Managemen f files Managemen f C prgrams Managemen f samping dies Faul and alarm infrmain Crec? Min parameer seing Display errr message Sarup min Excepin handling Implemen cnrl prcedure Min saus display Saus crec? Min end? Clse bard End Figure 6. Sysem sfware flw char. 81

5 Implemenain VS2015 is a pwerful visual prgramming l and ne f he cmmnly used prgram develpmen plafrm. DMC1410 prvides relaed drivers and develpmen funcins. Under he suppr f MFC prvided by VS2015 and mvemen funcin library prvided by DMC1410 min cnrl card, he sfware f min cnrl sysem is develped. As he min cnrl sysem uses mdular apprach, i is easy mainain. And he min cnrl sysem has he characerisic f recnfigurabiliy and scalabiliy. The develpmen prcess f he mdular design is ha he main srucure and prcess f sfware are described such as main prgram, sub-prgram, sub-prcess and s n, he inpu, upu, link and her relains amng varius framewrks are defined and debugged, and hus a series f algrihms describing he funcin blcks are bained. I is necessary develp a cnvenien and friendly inerface fr he requiremens f he min cnrl sysem. The main funcin f he inerface is display he varius funcin infrmain f he sysem in varius ways, and ransfer he user's inpu and selecin in he crrespnding daa he cnrl sysem. Users can develp he inerface crrespnding he requiremens f he cnrl sysem, and call he crrespnding funcins prvided by he min cnrl card mee he develpmen requiremens f he min cnrl sysem. Accrding he design f he inerface and he funcin f he min cnrl sysem, he inerface can be achieved hrugh he respnse funcin, such as in dialg bx, here are hree buns f X,, Z axis, in rder se he crrespnding speed, accelerain, disance and min mde and selecively read he crrespnding parameer, he implemenain prcess is shwn as fllws: If he independence mvemen f hree axis is in a cninuus min mde, call respnse funcin f v_mve (axis, sr_vel max_vel, Tacc) in he library f he mvemen funcin. When he min ends, call he funcin f v_sp (axis, Tdec) sp he mvemen f each axis. Cnclusins The min cnrl sysem f feeding mechanism is develped including hardware and sfware wih DMC1410 min cnrl card. In rder easily mainain and upgrade he sfware, he idea f mdular design is used in he verall srucure f he sfware. The sfware is develpmen using MFC prvided by VS2015 and mvemen funcin library prvided by DMC1410 min cnrl card. The min cnrl sysem f feeding mechanism has he characerisics f high speed and high precisin and vercmes he defecs f he cmplex peripheral circui and slw calculain in he radiinal digial min cnrl device. In addiin, he sysem is universal and can be easily ransplaned in he develpmen f varius min cnrl sysems. Acknwledgemens This wrk is suppred by he aural Science Fundain f Shandng Prvince (ZR2015EM042) and he Science and Technlgy Prgram f Higher Educain f Shandng Prvince (J15LB55). References [1] K. Osakada, K. Mri, T. Alan, Mechanical serv press echnlgy fr meal frming. CIRP Annals-Manufacuring Technlgy. 60 (2011) [2] Jian Hua, Wen-he Lia, Ru-rng Zhu, The sudy f he several kinds f speed cnrl curve f he CC sysem and cmparisn, Jurnal f nanjing universiy f aernauics and asrnauics. 31(1999) [3] L. Zhu, J.L. uan, P. Ga, A new archiecure f pen CC sysem based n cmpiling mde, The Inernainal Jurnal f Advanced Manufacuring Technlgy. 73(2014) [4] Jiangu an, Unmanned aircraf fligh cnrl sysem based n DSP sfware mdular design, Cmpuer measuremen and cnrl. 29 (2009) [5] W.W. Lin, P.S. Zhng, X.D. Lv, Implemenain f wireless cmmunicain and real ime cnrl fr CC sysem f Embedded CC urre punch press, Machine Tl & Hydraulics. 42(2014)