Three-Phase High Power Factor Mains Interface Concepts for Electric Vehicle Battery Charging Systems

Transcription

1 1 EEE Proeedigs of the 7th Applied Power Eletrois Coferee d Expositio (APEC 1), Orldo Florid, USA, Febrry 5-9, 1 Three-Phse High Power Ftor Mis terfe Coepts for Eletri Vehile Bttery Chrgig Systems T. Soeiro, T. Friedli, J. W. Kolr This mteril is pblished i order to provide ess to reserh reslts of the Power Eletroi Systems Lbortory / D-TET / ETH Zrih. terl or persol se of this mteril is permitted. However, permissio to reprit/repblish this mteril for dvertisig or promotiol prposes or for retig ew olletive works for resle or redistribtio mst be obtied from the opyright holder. By hoosig to view this domet, yo gree to ll provisios of the opyright lws protetig it.

2 Three-Phse High Power Ftor Mis terfe Coepts for Eletri Vehile Bttery Chrgig Systems T. Soeiro, T. Friedli d J. W. Kolr Power Eletroi Systems Lbortory ETH Zrih, Switzerld Emil: soeiro@lem.ee.ethz.h Abstrt This pper dissses ovel three-phse high power ftor mis iterfes pproprite for Eletri Vehile (EV) bttery hrgig systems. itilly, highly effiiet twostge -d system, osistig of three-phse lie-ommted retifier ombied with three-phse sht oeted Ative Power Filter (APF) d grop of iterleved d-d bk overters opertig i Triglr Crret Mode (TCM), is preseted. order to reple the ostly APF irit of the froted overter, while mitiig PFC pbility t the ipt d llowig similr opertig oditios for the bk-ed d-d overter, retifier topology employig tive third hrmoi rret ijetio irit is proposed. dditio, ovel three-phse bk-type PFC retifier is itroded for EV hrgig systems. The hrteristis of the preseted EV systems, ildig the priiple of opertio, modltio strtegy, sitble otrol strtres, d dimesioig eqtios, re desribed i detil. Filly, omprehesive ompriso of the stdied overters rted to 1 kw is show.. TRODUCTO Chrgig of Eletri Vehile (EV) btteries iheretly reqires oversio of eergy from the mis ito dqtities. Severl hrgig voltge d power levels hve bee defied by differet stdrdiztio orgiztios (EC 61851, EC6196, SAE J177). Sigle-phse Power Ftor Corretor (PFC) mis iterfes re ommoly employed for low hrgig power levels (e.g. P < 5 kw), wheres for higher hrgig power levels, three-phse PFC mis iterfes hve to be employed [1]. The EV hrger, typilly implemeted s two-stge system, i.e. omprisig PFC retifier ipt stge followed by d-d overter, be either itegrted ito the r (o-bord hrgers) or ommodted i speilly desiged EV hrgig sttios (off-bord hrgers) []. Bsi reqiremets for sh systems re otrolled otpt voltge, high power ftor, d high effiiey. f the power eletrois hs to be ommodted o-bord the EV, low weight d high power desity re lso desirble [1]-[4]. Filly, if isoltio of the PFC otpt from the d-bs is eessry de to sfety resos, this old be provided by isolted d-d overter. Possible Power Eletrois (PE) ofigrtios for hrgig of EVs re give i Fig. 1. With respet to pbli high power hrgig ifrstrtres, lso lled semi- or ltr-fst hrgers, the erly empty bttery shold be re-hrged i the shortest time possible. These EV hrgers, spplied from three-phse lies t 11 / V (rms) d 5 / 6 Hz, typilly reqire pek power rgig from 1 kw to 15 kw i order to ijet diret rret ito the bttery sets t vrible voltge levels ordig to the vehile (5 V to 6 V) [5]. Bk-type three-phse PFC retifiers, lso kow s Crret Sore Retifiers (CSRs), re pproprite for these high power hrgers s diret oetio to the d-bs old be sed. Compred to the boost-type systems, bk-type topologies provide wider otpt voltge otrol rge, while mitiig PFC pbility t the ipt d potetilly eble diret strt-p, while llowig for dymi rret limittio []-[7]. dditio, three-phse boost-type retifiers geerte otpt voltge whih is too high to diretly feed the d-bs (typ. 7 V to 8 V), reqirig step-dow d-d overter t their otpt. Fig. 1: Power eletroi overter topologies for EV hrgig systems. Fig. : EV bttery hrger oepts employig ) three-phse tive power filter d d-d overter, tive rd hrmoi rret ijetio retifier s frot-ed overter d d-d overter, d ) sigle-stge -d overter /1/$6. 1 EEE 6

3 Fig. : EV bttery hrger employig three-phse two-level tive power filter d iterleved d-d bk overters. order to be omplit with EC hrmoi ijetio stdrds d lso hieve high power ftor opertio, oisolted three-phse mis iterfe oepts well sitble for semi- or ltr-fst hrgers re lysed d/or proposed i this pper (f. Fig. ). A remrkble two-stge -d system, osistig of three-phse fll-bridge lie-ommted retifier ombied with three-phse sht oeted Ative Power Filter (APF) d grop of iterleved d-d bk-type overters performig the hrgig proess, is lyzed i Setio [f. Fig. () d Fig. ]. Additiolly, to filitte the seletio of Voltge Sore Coverter (VSC) for the APF of the proposed EV hrger, effiiey ompriso betwee two- d three-level VSC topologies is preseted. The lyses re performed for 1 kvar, x4 V / 5 Hz overters i the swithig freqey rge of 5 khz to 48 khz d with d-lik voltge level of U = 8 V. The lyses show tht for highly effiiet 1 kvar / 48 khz APF system the three-level etrl-poit-lmped (PC) overter represets the trl soltio for implemettio. Setio, hybrid rd hrmoi ijetio PFC retifier irit bilt by the ombitio of tive-filter-type rd hrmoi ijetio retifier d series oeted d-d bktype overter is proposed for EV pplitios [f. Fig. (]. The bk stge to be otrolled s rret spply with otrollble dymi rret limittio be ssembled with sigle or iterleved d-d overters. The implemettio with sigle d-d bk-type overter is show i Fig. 4. Setio V itrodes sigle-stge EV hrger [f. Fig. ()] employig the ovel three-phse bk-type PFC retifier topology show i Fig. 5, kow s SWSS Retifier. The hrteristis of this ew topology, sitble otrol stge, d methods for lltig losses of ll ompoets re lso give. Filly, i Setio V, the proposed EV systems, rted to 1 kw d flly desiged for employig ommeril ompoets, re systemtilly ompred.. TWO-STAGE EV BATTERY CHARGG EMPLOYG ACTVE POWER FLTERS Fig. shows highly effiiet two-stge -d overter pproprite for EV hrgig pplitios. This system osists of three-phse fll-bridge lie-ommted retifier ombied with three-phse two-level sht oeted APF d grop of iterleved d-d bk overters. Oe dvtge of this pproh is the reltively smll power rtig of the APF, whih remis pproximtely 4% of the hrgig power demded by the bttery [6]. Additiolly, the system flly beefit from the high relibility of the lie-ommted retifier, s i se of APF filre, the EV hrger old remi i opertio, bt withot power ftor orretio pbility. Fig. 6, sitble sht tive filters, derived from the three-phse three-level T-type d three-level -type (PC) VSCs, re preseted. For low grid voltge levels, i.e. for rms lie-to-lie voltge betwee V to 5 V, the threelevel topologies re ot wide spred bese of the itrisilly lrge mber of ompoets d oseqetly the high osts. O the other hd, three-level APF bilt with T 1 D 1 L AF T T C AF+ b D D C AF- Fig. 4: Ative rd hrmoi rret ijetio retifier with sigle d-d bk overter for two-stge EV hrger pplitios. ) T 4 D 4 T 1 D 1 C AF+ b i AF1 T L AF D D 5 U, T D D 6 C AF- Fig. 5: Cirit topology of the bk-type SWSS Retifier. T 4 D 4 Fig. 6: Ative filters bsed o the ) Three-level T-type d Three-level -type (PC) voltge sore overter. 64

4 6 V semiodtors hieve lower losses th twolevel system bilt with 1 V devies if the osidered swithig freqey is high eogh (typ. > 1 khz) [7]. Coseqetly, -level APFs ostitte iterestig soltios for pplitios whih im for otstdig effiiey t low weight/volme. A effiiey ompriso betwee APFs derived from the two- d three-level topologies for 1 kvar power pbility is show i Fig. 7. The lyses re performed for overter opertio i the swithig freqey rge of 5 khz to 48 khz, 4 V lie-to-lie rms grid voltge, d 8 V dlik voltge level. The 6 V GBTs KW6T d the 1 V GBTs KW5T1 from fieo re seleted for the ssessmet d their loss hrteristis re determied with test set-p [f. Fig. 7()]. A Spe Vetor Modltio (SVM) sheme iorportig optiml lmpig of the phse is seleted for lysis. Whe ompred to simple rrier-bsed sisoidl plse-width modltio (SPWM), eve for low swithig freqeies, the SVM strtegy demostrtes better effiiey d loss distribtio fetres (f. [8]). De to the ft tht the 1 V devies i the T-type tive filter re mostly ommted t 4 V (hlf of the dlik voltge) isted of 8 V ompred to the two-level VSC, the swithig losses re osiderbly reded. Therefore, for low swithig freqey vles, the three-level T-type tive filter lredy shows sperior performe th the ovetiol two-level VSC. Compred to the three-level -type VSC, the T-type system hs lower odtio losses, bt higher swithig losses. For the osidered APF speifitio, the effiiey of the T-type overter is the best for swithig freqeies p to f P = khz. O the other hd, for higher swithig freqeies, the three-level -type APF is sperior. Therefore, for highly effiiet 1 kvar / 48 khz APF, the three-level -type overter is the trl soltio for implemettio. Fig. 8() shows desiged 1 kvar / 48 khz three-phse three-level PC APF prototype. t ses stom three-level bridge-leg modles employig SiC Shottky diodes to eble highly effiiet opertio [diodes D 1, D 4, D 5, d D 6 i Fig. 6(]. A digitl sigl proessig bord with T DSP d Lttie FPGA is sed to implemet dq-frme otrol strtegy d SVM sig lmpig of the phse odtig the highest rret. The power desity of this APF is.65 kvar/dm. The performe of the EV hrger employig the desiged APF is show i Fig. 8(. As be oted, the system effiietly ompeste the rret hrmois of the lod s the lie rrets hve sisoidl shpe (THD 4%). The reslts ttest the fesibility of this soltio. order to simlteosly hieve high power desity s well s high effiiey, while the EV hrger otpt rret ripple is kept smll, modlr ofigrtio of iterleved d-d overters is preseted i this pper. For 1 kw EV hrger speifitio, two prlleled 6 kw ltr-effiiet ( 99%) mlti-ell overters re desiged, eh osistig of three iterleved bk stges opertig i Triglr Crret Mode (TCM), whih fetres zero voltge swithig (ZVS) for the employed power MOSFETs (f. Fig. 9). The high TCM idtor rret ripple is ot trsferred to the EV bttery set s the sperpositio of ll bk ells rrets, i L1,,, reslts i smooth otpt rret wveform i L, with reltively low ripple. Additiolly, the reverse-reovery behvior of the MOSFET body diode beomes irrelevt, d oseqetly very low swithig losses re hieved. Fig. 9 shows the bsi ofigrtio of the proposed modlr d-d overter, ildig the otrol strtegy sed for sigle bk sb-ell. ote tht the ZVS swithig be hieved bese the idtor rret delies to zero d sbseqet osilltio betwee idtor d prsiti CM &DM EM filter bord Cotrol bord -lik pitors Boost idtors ) Effiiey [%] level VSC -level PC VSC -level T-type VSC Swithig freqey [khz] Fig. 7: ) Swithig loss mesremet set-p d effiiey ompriso betwee the differet topologies of 1 kvar APFs employig ommeril semiodtors. ) Het sik with fored ir oolig Fig. 8: ) Three-level APF prototype d mi experimetl wveforms. 65

5 P o p * o i* L L O- d Off- time lltio Modltor G L 1 L i L1 L i L p ) Fig. 9: ) Three iterleved d-d bk-type overters d proposed otrol sheme. C f C o o p G PWM i L1 i L i * i* L L t O t Off R L t i 1 * O L R p o L L t i 1 * Off L R o i L1 Referee Crret Step 5A 1A 5A i L,DSP G i L,DSP ) Fig. 1: ) 6 kw d-d -iterleved bk overter hrdwre prototype d mi wveforms (i L,DSP: A/div, i L1: 5 A/div, G: 1 A/div). G MOSFET pitors strts i whih the voltge ross the power semiodtors of the bridge-leg drops d ireses to d p, respetively. order to void Vlley Swithig (VS) oditio, where the prsiti pitors re ot flly hrged/dishrged (loss of ZVS swithig), the idtor rret is tively deresed below zero til it rehes speified vle R, whih sstis ZVS swithig. For more detils bot the TCM opertio of iterleved overters, see [9]. order to vlidte the preseted otrol method d lltios for the otpt stge of the retifier, 6 kw ltreffiiet ( 99%) high-power desity (1 kw/dm ) d-d overter prototype, s depited i Fig. 1(), hs bee bilt. Fig. 1(, mesremet reslts for opertio t V otpt voltge d lod step re show, whih ildes the totl iterleved otpt rret llted by the DSP i L,DSP ( A/div), the TCM opertio with ZVS swithig for sigle bk sb-ell i L1 (5 A/div), d gte sigl G (1 V/div). The reslts ofirm the proper opertio of the desiged overter, s eve drig lod trsiets, smooth otios totl otpt rret with low ripple old be hieved, while ZVS swithig for the MOSFETs is preserved.. TWO-STAGE EV BATTERY CHARGG EMPLOYG ACTVE RD HARMOC JECTO RECTFER Fig. 4 shows the bsi ofigrtio of three-phse high power ftor tive third hrmoi ijetio retifier d series oeted d-d bk-type overter pproprite for EV hrgig mis iterfes. The frot-ed overter osists of three-phse high-effiiey eletrolyti pitor-less lie-ommted retifier ombied with tive rret ijetio irit (f. [1]). The ltter irit effetively reple the APF system of the frot-ed overter depited i Fig., bese it llows to sisoidlly shpe the ipt rret of the lie- ommted system. The rret ijetio irit is formed oly by sigle fst-ommted hlf-bridge-leg, idtor, d three low freqey bidiretiol swithes. Advtgeosly, the egtive otpt voltge termil is lwys oeted to the mis vi diode of the lower hlf bridge of the diode retifier. Therefore, o otpt CM voltge with swithig freqey is geerted. The third hrmoi ijetio retifier of the proposed EV hrger shows reltively low implemettio effort, however, t the expese of missig otpt voltge otrol. The otpt voltge is ow determied diretly by the diode bridge retifier d hee exhibits six-plse shpe. Therefore, series oeted d-d overter is eessry to provide the hrgig reqiremets of the EV bttery. f the bk-ed overter, i.e. grop of iterleved d-d bktype overters, is otrolled to demd ostt power, rrets vryig i opposite phse to the six-plse retifier voltge will be impressed t the ipt of the retifier. As show i Fig. 11, this leds to sisoidl shpe of ll mis phse rrets fter overlyig with rd hrmoi otrolled ijetio rret i y. A sitble feedbk otrol strtre d the mi overter dimesioig eqtios, whih ilde the verge d rms rret vles of the power semiodtors, re give i Fig. 11(). The modltio of the rret ijetio irit is performed t low freqey followig the retifier ipt voltges,b, i sh wy tht the tive rret ijetio lwys ors ito oly oe mis phse s preseted i Tb. (f. Fig. 1). For proof of the sisoidl otrollbility of the mis rrets, the eqivlet irit of the proposed EV hrger for the mis itervl [, π/] ( > b > ), whih is depited i Fig. 11(, is osidered for lysis. delly, the retifier system opertes s symmetri three-phse lod of (fdmetl) phse odte G to the mis, therefore, 66

6 the vle of the rret to be ijeted ito phse b my be writte s iy ib Gb (1) The mis freqey voltge drop ross the idtor of the rret ijetio irit i first pproximtio be egleted for the formtio of i y,. () ) Dvg, ˆ Drms, ˆ * iy Uˆ pos eg ˆ 1 Dy, Sy 6 8 vg L ˆ * y pos eg Dy, rms Sy ˆ ˆ DF, rms l 8 4 Tvg, Trms, DF, vg ˆ 1 ˆ 1 l 4 ˆ 1 l Aordigly, the voltge formed t the otpt of the bridge-leg will be give by y b. () f the voltge t the termil Y is formed ordig the reltive o-time of the trsistor T + s k d T - s (1-k), it will reslt i L k 1k k. (4) For the dty yle k give by b k, (5) the rret i T + be llted s b i T ki y ki b kg b G. (6) b Cosiderig the fdmetl ipt rrets tht hve to be geerted t the ipt i G ; i b G b d i G, (7) the rret osmptio of the ostt power lod be llted vi P i i b b b b G. (8) Aordigly, the resltt low freqey rret drw from phse is proportiol to the mis voltge i i G. (9) T Additiolly, the low freqey rret for phse be determied sig (1), (9), i i i d s i b b G. (1) With this, the sisoidl shpe of ll phse rrets hs bee proved x 1 5 Fig. 1: Mis setors 1 to 1 defied by the differet reltios of the istteos vles of the mis phse voltges,b,. ) Fig. 11: ) Power irit, otrol strtre d semiodtors rret stresses of the tive-filter-type rd hrmoi rret ijetio retifier; eqivlet irit of the retifier for > b >. ) Mi wveforms of the EV hrger frot-ed overter for ostt otpt power osmptio P of the bk-ed overter. Û d Î re the mplitde of the phse voltge d rret, respetively. TABLE : Modltio of the rret ijetio irit (f. Fig. 1). Setor S y1 S y S y Setor S y1 S y S y

7 Fig. 1 presets 7.5 kw hrdwre implemettio of the proposed EV hrger depited i Fig. 4. This system ws desiged to eble opertio s the EV hrger depited i Fig. 5 (SWSS Retifier) by oly performig smll hges i the prototype irit. The overll dimesios of the system re 1 mm x 1 mm x 9 mm, hee givig power desity of.94 kw/dm. Fig. 1: 7.5 kw tive-filter-type rd hrmoi rret ijetio retifier hrdwre prototype to operte s overter ordig to Fig. 4 or Fig. 5. V. SGLE-STAGE EV BATTERY CHARGER EMPLOYG ACTVE RD HARMOC JECTO RECTFER A ovel three-phse PFC retifier soltio ombiig bk d-d overters d tive rd hrmoi ijetio retifier irit, med here s the SWSS Retifier, is show i Fig. 5. With this ew topology d reltively low omplexity otrol stge, ot oly otrolled otpt voltge be hieved, bt lso high power ftor opertio [11]. The ew retifier system llows the lol verge vles of rrets i the positive d egtive tive swithes, i T+ d i T-, to be formed proportiolly to the ipt voltges ivolved i the formtio of the otpt voltge of the diode bridge. f the differee betwee i T+ d i T- is fed bk ito the mis phse with the rretly smllest bsolte voltge vle vi rret ijetio etwork, formed by three forqdrt swithes ommded t twie the lie freqey, sisoidl ipt rret shpe be ssred for ll mis phses while the d-d overter grtees the otpt voltge regltio. The modltio of the rret ijetio irit is performed t low freqey followig the retifier ipt voltges C,,b, i sh wy tht the tive rret ijetio ors lwys ito oly oe mis phse s preseted i Tb. [f. Fig. 1]. Aordigly, i eh oe of the wide setors of the mis period, for differet odtio sttes be defied by the swithes T + d T - withi plse period T P, where the d rret, impressed by the d idtors, is distribted to two of the ipt phses or is kept i freewheelig stte. Fig. 14() presets the for odtio sttes of the SWSS Retifier for the itervl φ [, ]. For the swithig stte j = (O, O), where j = (T +, T - ) idites ombitio of the swithig ftios of the two fst swithes (T + d T - ) d O mes tht the respetive swith is tred o, while OFF idites off-stte of the swith, the retifier ipt rrets re i r, =, i r,b =, d i r, = -, therefore, the retifier ipt rret spe vetor for this swithig stte reslts i i e j 6 r,( O, O). (11) Alogosly, the three remiig spe vetors be llted s i e j 6 r,( O, OFF), (1) i e j r,( OFF, O), (1) i. (14) r,( OFF, OFF) With these for spe vetors, resltig ipt rret spe vetor i * r be formed [f. Fig. 14(] so tht it is i phse with the mis voltge vetor d hs the reqired mplitde ordig to the tl power demd. Proper seletio of the seqees of the swithig sttes llows otrol over the rret ripples ross the idtor L d the phse ijetio rret i y. Aordigly, the overter be modlted i order to miimize the rret ripple of i y, or tht of the d rret. For the first mis setor ( < φ < ), the SWSS Retifier operte with miiml i y rret ripple d oseqetly lower ripple vles of the ipt pitor voltges CF,,b, if vetor modltio with the swithig ) Fig. 14: ) Codtio sttes d ipt rret spe vetor digrm of the SWSS Retifier for φ [, ]. 68

8 seqee (O, O) - (O, OFF) - (OFF, OFF) - (O, OFF) - (O, O), rrged symmetrilly rod the middle of the plse itervl, is pplied. Therefore, the ipt phse rrets re formed by the d rret d the reltive o-times of the rret spe vetors k i i k k ; i k ; i k. (15) r, 1 r, b r, 1 The otpt voltge p is formed by the lie-to-lie voltges b d, rted by the reltive o-time of the respetive rret vetors s p k 1 kb. (16) ote tht the otpt voltge rge is limited by the miiml vle of the six-plse diode bridge otpt voltge p, l. l, rms (17) Filly, PFC opertio i the first mis setor be hieved with reltive o-times k i, depedet o the modltio idex M, the istteos vles of,b,, d the mplitde of the mis phse voltges Û give by p M, Uˆ (18) k1 M, k M, d k U ˆ U ˆb 4 1 M U. (19) ote tht the swith dty yles α + d α - for symmetri mis ( + b + = ) re defied s follows p p b k1 k Uˆ ˆ, () U p k 1 Uˆ. (1) Altertively, for the first mis setor ( < φ < ), the SWSS Retifier operte with miimized d rret ripple i ripple d oseqetly reded ripple vles of the otpt low-pss filterig if vetor modltio with the swithig seqee (O, OFF) - (O, O) -(OFF, O) - (O, O) - (O, OFF), rrged symmetrilly rod the middle of the plse itervl, is pplied. The ipt phse rrets formed by the d rret d the reltive otimes of the rret spe vetors k i reslt s ir, k1k ; ir, b kk ; ir, k1 k. () The otpt voltge p is formed by the lie-to-lie voltges b, b, d rted by the reltive o-time of the respetive rret vetors p 1 b b ˆ k k k. () Filly, PFC opertio i the first mis setor be hieved with reltive o-times k i, depedet o the modltio idex M, istteos vles,b, d the mplitde of the phse voltges Û give by k 1 M, k 1M U U ˆ ˆ k 1k k M 1 U ˆ. (4), 1 A possible implemettio of otrol irit for the SWSS Retifier d the mi overter dimesioig eqtios, ildig the verge d rms rret vles of the power semiodtors, re give i Fig. 15. This feedbk PWM otrol strtre omprises sperimposed otpt voltge otroller R(s) d sbordite otpt rret otroller G(s). A feed-forwrd loop dds the ormlized modltio ftios defied by the positive d egtive diode bridge otpt voltge d the system otpt voltge referee vle * p to the d rret otrollers i order to diretly geerte the ipt rret formig voltge. the proposed feedbk otrol, by settig the PWM modltor for T + d T - to operte with i-phse rriers, the rret ripple i y is reded while the d rret ripple i is mximized. For iterleved opertio of these rriers, the opposite will or. A omplete desriptio of the hrteristis of the SWSS Retifier, ildig the priiples of opertio, modltio strtegy, otrol strtre lysis, EM modellig d dimesioig eqtios, is give i [1]. b D, vg M D, rms Dy, vg M Sy Dy, M rms Sy L F, i i r, CF, L F,b L F, C F, M i b i r,b i C F,b C F, Tvg, M Trms, M i r, -1 p * Û p * Û i T+ D + D - i T- T + T - PWM + D F+ Sy1 Sy Sy PWM - D F- i y G(s) p L p - R(s) + p * C p DF, vg 1 M DF, rms 1 M L Fig. 15: Cotrol strtre d semiodtors rret stresses for the SWSS Retifier (bk-type PFC retifier). V. COMPARATVE EVALUATO order to evlte d ompre the ew three-phse high-power-ftor mis iterfe oepts for EV hrgig pplitios disssed i this pper, severl ormlized performe idies re defied. The mi ompriso fetres re: the power ftor λ, the totl rret hrmoi distortio THD, the reltive totl swithig losses τ S for trsistors d diodes (δ S ), the reltive totl odtio losses τ C for trsistors d diodes (δ C ), the mgeti rted power P L (rret ripple Δi L,pp,mx is limited to 5% of ), d the pitors rret stress C,rms. For y system, these hrteristis give iformtio bot size/volme, ost of the ompoets, d the bility to meet power qlity stdrds. Bsed o these performe metris, ompriso of the proposed systems is performed grphilly, s illstrted i Fig. 16. A dvtgeos system wold preferbly over smll re i the grphil represettio. The ompriso reslts for the 1 kw/x4 V/48 khz two-stge systems, desribed i Setio d employig i totl six iterleved bk-type d-d overters, re depited i Fig. 16(). The reqiremet for smll d-lik pitors d the ft tht oly sigle idtor is eessry 69

9 to shpe the lie rrets mke the tive-filter-type rd hrmoi ijetio overter dvtgeos i terms of size, weight d ost of hrdwre over the soltio employig dedited APF. The possibility of sig film d-bs pitors over eletrolyti pitors is beefiil for the system relibility. evertheless, this system llows sisoidl regltio of the mis rrets oly i the se tht the bk-ed overter is demdig ostt power d o smoothig pitor (of higher pite) is oeted to the d-bs. Lod vritios re ths pssed o diretly to the mis. Additiolly, the bsee of eergy storge t the ipt of the d-d overter mkes it diffilt to spply power to the bttery drig short ipt voltge iterrptio. Advtgeosly, the EV system employig APF flly beefit from the high relibility of the lie-ommted retifier, s i se of APF filre the EV hrger old remi i opertio, bt withot PFC pbility. The ompriso reslts for the 1 kw / x4 V / 6 khz SWSS Retifier d tive-filter-type rd hrmoi rret ijetio retifier with sigle d-d bk overter oeted i series re ompiled i Fig. 16(. The mi dvtges of the tive-filter-type rd hrmoi rret ijetio retifier with sigle d-d bk overter over the SWSS Retifier is tht oly oe trsistor is lyig i the mi rret pth, i.e. i prtilr t high otpt voltges with reltively short freewheelig itervl, low odtio losses or. dditio, the egtive otpt voltge termil is lwys oeted to the mis vi diode of the lower hlf bridge of the diode retifier. Therefore, o otpt CM voltge with swithig freqey is geerted. The mi dvtges of the SWSS Retifier re the better lie power qlity d tht the system bsilly be otrolled like d-d overter. Aordigly, bsi kowledge of the ftio of pssive diode retifier t the ipt stge of the system is sffiiet to implemet three-phse PFC retifier with sisoidl ipt rret d otrolled otpt voltge. Filly, mog the stdied systems the SWSS Retifier is the soltio ombiig the best fetres for EV hrger, d provides good ompromise betwee relibility, simpliity, d reltively low ost, volme, d weight. V. COCLUSO This pper proposes three-phse high power ftor mis iterfes pproprite ot oly for high power EV bttery hrgig systems, bt lso for power spplies for teleommitio, ftre more eletri irrft, vrible speed drivers, d high power lightig systems. The reqiremets for power overters i EV bttery hrgig pplitios hve bee desribed. Frthermore, the hrteristis of the preseted EV systems, ildig the priiples of opertio, modltio strtegy, sitble otrol strtres, d dimesioig eqtios, hve bee smmrized. Filly, ompriso of the stdied overters rted for otpt power of 1 kw hs bee show, whih idetify the SWSS Retifier d the tive-filter-type rd hrmoi ijetio retifier with series oeted bk overters s most dvtgeos soltios. REFERECES [1] J. J. Che, F.-C. Yg, C.-C. Li, Y.-S. Hwg d R.-G. Lee, A High Effiiey Mltimode Li-o Bttery Chrger with Vrible Crret Sore d Cotrollig Previos Stge Spply Voltge, EEE Trs. d. Ele., vol. 56(7), pp , 9. [] M. Che d G. Rio-Mor, Arte, Compt, d Power- Effiiet Li-o bttery Chrger Cirit, EEE Trs. Cir. Sys. : Expr. Briefs, vol. 5(11), pp , 6. [] R. Gitzeder, F. Pgli, C. Mrti, D. Crme, E. Joes d S. Eves, High Power d High Eergy Lithim-o Btteries for Uderwter Vehiles, J. Pow. Sores, vol. 16, pp , 4. [4] B. Keedy, D. Ptterso d S. Cmilleri, Use of Lithim-o Btteries i Eletri Vehiles, J. Pow. Sores, vol. 9,. [5] D. Aggeler, F. Cles, H. Zely, A. Coi,. Bther, d O. Apeldoor, Ultr-Fst -Chrger frstrtres for EV-Mobility d Ftre Smrt Grids, Pro. Smrt Grid Cof. (SGT), 1. [6] A. Kperm, U. Levy, J. Gore, A. Zfrski d A. Sveri, High Power Li-o Bttery Chrger for Eletri Vehile, Pro. 7th t. Cof. Workshop Comptib. d Power Eletro. (CPE), 11. [7] T. Soeiro, M. Shweizer, J. Lier, P. Rstd, d J. W. Kolr, Compriso of - d -level Ative Filters with Ehed Bridge- Leg Loss Distribtio, Pro. 8th ter. Cof. o Power Eletro. (ECCE Asi), 11. [8] B. Kk,. Miyshit, d S. Soe, Swithig Loss Miimized Spe Vetor PWM Method for GBT Three-Level verter, EE Proeedigs. Eletri Power Appl., vol. 144, pp , My [9] C. Mrxgt, J. Biel, J. W. Kolr, terleved Triglr Crret Mode (TCM) Resot Trsitio, Sigle Phse PFC Retifier with High Effiiey d High Power Desity, Pro. EEE/EEJ t. Power Eletr. Cof. (ECCE Asi), Je 1-4, 1. [1] H. Yoo S.-K. Sl, "A ew Cirit Desig d Cotrol to Rede pt Hrmoi Crret for Three-Phse AC Mhie Drive System Hvig very Smll -lik Cpitor, Pro. 5th A. EEE Appl. Power Eletro. Cof. d Exp. (APEC), pp , 1. [11] J. W. Kolr, M. Hrtm, T. Friedli, Hybrider Dreiphsiger AC/- Koverter d Verfhre z desse Steerg. CH98/11, 11. [1] T. Soeiro, T. Friedli d J. W. Kolr, SWSS Retifier A ovel Three-Phse Bk-Type PFC Topology for Eletri Bttery Chrgig, Pro. 6th EEE Appl. Power Eletro. Cof. d Exp. (APEC), 1. APF + terl. 1-λ [%] - Cov. Cpitor Crret Stress..5 Crms,,.4..5 o..15 Rted dtor Power LLLpkpk, fs Po.4 δ C THDi[%] AFT rd Hrm. Ret.+ terl. - Cov..4.5 τ S U Tvg,, Bvg,, P τ Trms,, Trms,, C Drms,,. Drms,, D, vg, B, vg, δ U S U Dvg,, Bvg,, P ) P Fig. 16: Comprtive evltio of three-phse PFC bk-type retifier topologies for EV hrgig systems. T,vg d D,vg re the verged swithed rret d U B,vg is the verged swithed voltge ross the power semiodtors. T,rms, D,rms, L d C,rms re the rms rret vle of the speifi ompoet. Crms,, o LLLpkpk, fs Po U Tvg,, Bvg,, P 61