New Directions in Interconnect Performance Optimization

Transcription

1 New Diretion in Interonnet Performane Optimization Antoine ourtay 1,2, Johann Laurent, Nathalie Julien 1 Lab-STI - Univerity of South Brittany rue de aint maudé Lorient, Frane {firt name}.{lat name}@univ-ub.fr Olivier Sentiey 2 IRISA - Univerity of Renne 1 (ENSSAT) 6, rue de Kerampont Lannion, Frane {lat name}@iria.fr Abtrat It i now admitted that interonnet repreent a bottlenek for delay, power onumption and area on hip. To fae thee problem ome work have been realized around performane optimization. However reult, preented in thi paper, how that optimization tehnique do not alway fae good riteria for interonnet performane optimization. We therefore have developed a high-level etimation tool baed on tranitor-level haraterization, whih provide uer fat and preie reult for time and power onumption etimation. Etimation reult allowed u to determine a new interonnet onumption model and alo enabled to find ome new key iue that have to be pointed out for future performane optimization. I. INTRODUTION Today, nomad appliation are more and more omplex and require many omputation reoure, implying a trong volume of data to be tored or ommuniated. To ommuniate thee data from memorie to omputation unit or from a omputation unit to another one, interonnet network or bue have to be ued. Interonnet onumption and area an repreent up to 50% of the overall onumption a well a hip area [1-2]. Indeed, the tranitor and wire dimenion evolution reult in a modifiation of the iruit behavior, motly of the propagation time; the propagation time for a wire beome higher than in a gate [2]. Part of thi inreae i due to the evolution of wire reitane. Indeed, between two tehnologie, the dimenion of a wire dereae, and onequently the reitane inreae. With the evolution of the manufaturing proee [3], interonnet are now made up of opper whoe ondutivity i greater than the aluminum ued in older tehnologie (over 250nm). Together with thi replaement of aluminum by opper, inulator with weak permittivity appeared. With thee hange, propagation time on interonnet ha trongly dereaed. Uing weak permittivity inulator allow to redue the rotalk phenomena and wire-to-ubtrate apaitane. Depite of thee tehnologial evolution, interonnet are now known to be one of the bottlenek of the ytem. Thu, it i eential to take interonnet power onumption and delay into aount during the deign phae of a ytem-on-hip. In thi paper, we propoe, after the preentation of power onumption model of bue, a new etimation tool that allow the uer to obtain different kind of reult about the power onumption of hi interonnet network. Furthermore, we propoe a new tranition laifiation from the power onumption point of view; thi laifiation i very different than the previou one defined from a propagation time point of view. Then, baed on thi new laifiation and on other tatitial metri, we propoe ome new way to optimize the interonnet performane (delay, power onumption). Thi paper i organized a follow; Setion II preent phyial parameter that have to be taken into aount for bu modeling. The etimation flow a well a our etimation tool i alo introdued. In Setion III, our tool i ued to analyze riteria ued by performane optimization tehnique; ome new way for optimization are alo diued. Lat etion onlude thi paper. II. BUS POWER ONSUMPTION MODELLING AND ESTIMATION The firt tep for interonnet modeling, i to repreent a bet a poible interonnet behavior. In order to obtain the bet preiion in time and power onumption, experiment mut be realized at phyial level. Therefore we deided to model interonnet with a tranitor-level haraterization uing a SPIE imulator. Firtly, thi etion introdue phyial modeling from wire to the omplete bu ytem with all paraiti phenomena. A. The wire Phyial parameter whih allow wire modeling are the following: R, wire reitane, expreed in Ohm [Ω];, wire apaitane, expreed in Farad [F]; L, wire indutane, expreed in Henry [H]. Their variation depend on the wire harateriti (metal ompoition, wiring level) a well a dimenion. Indutane ha an impat only for very deep ubmiron tehnologie (underneath 45nm) and for extremely long wire [4]. Furthermore, it i an important phenomenon when peak of urrent or trong voltage variation our (typially the lok tree and the power line); o indutane will not be taken into aount in our model dediated for interonnet bue. Thu we have hoen to onider only R model for the wire. It i poible to haraterize the wire with elementary parameter whih an be found in manufaturer Deign Kit. Thee parameter are the following:

2 W L Rq = ρ / T, reitane by quare, expreed in Ohm by quare [Ω/quare] with ρ the metal reitivity and T the wire thikne; q, wire lower fae to ubtrate elementary apaitane, expreed in Farad per meter [F/m];, wire edge to ubtrate elementary apaitane, e expreed in Farad per meter [F/m]. Uing thee three parameter, it i poible to ompute the wire reitane and apaitane aording to it dimenion (ee Fig. 1.): length (L) and width (W) expreed in meter [m]. Note that and q depend on the height (H) between e the wire and the ubtrate and thu depend on the metal level ued. The total reitane of the wire i given by the following equation: R = Rq L W (1) The total apaitane of the wire i, in fat, the um of two apaitane: the total wire lower fae to ubtrate apaitane (parallel-plate apaitane) noted pp, and the total wire ide to ubtrate apaitane (fringing apaitane) noted. pp f = WL (2) q = 2 L (3) Fator 2 in equation (3) i intended to inlude the fat that the two ide of the wire ontribute to f. The total wire apaitane to ubtrate an then be expreed a: = L qw + 2 e (4) Now, we diu about the ditribution of R and on the wire in order to model it behavior a aurate a poible. The lumped model i a imple interonnet model; it onit in putting end-to-end value of R and found previouly. However, it preiion i muh le reliable in term of propagation time than a model where R and are ditributed. For the Π 3 model, whih onit in ditributing the wire reitane on three reitane and the wire apaitane on four apaitane, the value obtained in term of time are loe to experimental value. In thi manner, R and value an be plit indefinitely. We have retained Π 3 model for our experiment beaue of it impliity and it preiion (etimation error le than 5%) [5]. B. The bu We onider a n bit bu whih onit of n wire of the ame length in parallel and at leat 2n buffer (n input buffer, n output buffer and maybe other buffer if bufferization i ued) and allow propagating data between two ell. The fat of uing everal wire reveal a new apaitive oupling whih i the oupling between wire. The oupling apaitane e f T H A1 V A2 Figure 1. A vitim wire (V) and it two agreor (A1, A2) between two adjaent wire, known a rotalk apaitane, depend on the area faing eah other; o it depend on the following dimenion: wire thikne (T), wire length (L) and wire paing (S). = ε 0 TL S where 0 ε repreent SiO permittivity (5) 2 When tranition our on adjaent wire, there i a generation of an unwanted noie due to the oupling apaitane. The noie due to the rotalk i relatively loalized. In general, a ytem with rotalk i modeled by negleting higher-order effet on non-adjaent wire; thu, we only onider the effet on three wire a repreented in Fig. 1. The oupling apaitane between wire are alo be ditributed on the node of the ditributed Π3R model defined previouly a repreented in Fig. 2. We explain in more detail the rotalk phenomenon and effet aoiated to it in the next paragraph. Effet, due to rotalk, an be ummarized into three ategorie. The firt one i that rotalk indue noie; indeed the oupling apaitane between adjaent wire introdue a permanent link between them. When a tranition our on a wire (aggreor), it neighbor (vitim) are affeted beaue a voltage peak i generated on them [6]. With tehnology hrinking, noie due to rotalk ompared to the overall noie inreae ine the oupling apaitane alo rie between two tehnology tep. A a reult, the voltage peak generated by the oupling apaitane i more and more important, ompared to the voltage wing on the bu. Figure 2. A Π3 R wire bu with rotalk apaitane

3 TABLE I. EFFETIVE APAITANE AND DELAY FATOR eff g OF THE VITIM WIRE AND THE ORREPONDING TRANSITION PATTERNS eff Tranition Pattern g (,, ) (,, ) 1 + (-,, ) (-,, ) (,,-) (,,-) 1+r + 2 (-,,-) (-,,-) (,, ) (,, ) A eond iue i the inreae in propagation time. A tranition laifiation ha been arried out aording to propagation time on the vitim: thi laifiation i preented in Table I. g repreent the delay fator and r the ratio of rotalk apaitane ompared to wire apaitane to ubtrate. Here, repreent a riing tranition, repreent a falling one and - mean that there i no tranition on the wire. In the bet ae, when wire are withing in the ame diretion, the delay i the delay without rotalk (i.e. g=1). However, data tranmiion on the bu mut be loked regarding the wort propagation time ae (i.e. g=1+4r). While onidering a real ae, where =, the propagation time an be multiplied by five or more [7]. Finally, the lat iue i an inreae in power onumption. Indeed, power onumption depend linearly of the apaitane preented by a devie. Sine the wire apaitane depend on the rotalk apaitane value eff (f. Table I), rotalk ontribute to inreae dynami power onumption [8]. The lat parameter that have to be defined for bu modeling are reitane, input and output buffer apaitane. Thee parameter an be eaily found by uing tranitor dimenion and paraiti parameter provided in tehnology librarie and by uing formula deribed in [9].. Bu power onumption modeling Knowing phyial parameter that ompoe the entire bu, we are able to model propagation time and power onumption. The firt tep of the modeling proe i to identify whih parameter impat delay and power onumption. The firt parameter i the tehnology and it aoiated number of metal layer. Eah metal layer ha it own phyial harateriti (dimenion) and finality. The lowet metal layer are ued for very hort wire (inide ell), intermediate layer for bue (between ell), and finally the highet layer are ued for lok tree and power line. The eond parameter i the metal layer ued in the onidered tehnology. It i well known that wire reitane and apaitane vary with the metal layer, ine dimenion (thikne, paing, high and width) are different with the layer ued. The third parameter i the wire length ine thi parameter impat apaitane and reitane. When interonnet are quite long or when time i ritial, it i neeary to inert (,, ) (,, ) 1+2r + 3 (-,, ) (-,, ) (,,-) (,,-) 1+3r + 4 (,, ) (,, ) 1+4r repeater along wire [10-12], thu, repeated and non repeated line have to be modeled. rotalk apaitane have effet on power onumption and propagation time, a hown in Table I, thu the different kind of tranition will be alo parameter for modeling. A aid before, the rotalk apaitane are pitted on the wire by uing the Π 3 model. Uing thee parameter, power onumption and delay modeling an be realized at the iruit level uing SPIE imulation (we ued ELDO v5.7 in thi paper). Thee imulation have been aomplihed for three different tehnologie (130, 90 and 65nm). The reult obtained with SPIE, in term of time and energy onumption, have been ummarized in multi-input table for the different parameter. Thee table are ued by the high-level etimation tool preented in the next etion. D. Bu power onumption etimation A tool, alled Interonnet Explorer, ha been developed for high-level etimation of interonnet performane. Thi tool i baed on the energy and timing tranitor-level haraterization reult table. The etimation flow ued by Interonnet Explorer i explained in Fig. 3 and detailed hereafter. When uing Interonnet Explorer, uer have to hooe their bu onfiguration by etting the following parameter in the tool onfiguration window: tehnology, metal layer, bu length, bu width, frequeny and bufferization type. Uer have alo to provide an input file; thi file ontain the appliation data that are roing over the bu. Some additional plugin have been inluded in thi tool to ompute ommutation rate per bit on the bu and alo the probability of appearane of eah tranition la (defined in Table I). ommutation rate per bit are obtained by uing the data input file. We ompute the ativity on eah wire by realizing the ratio between the number of tranition on the wire ompared to the total number of data. Input File (Appliation data) INTERONNET EXPLORER Energy & Timing table iued from SPIE imulation Reult Output window onfiguration window Uer Parameter Additionnal plugin ommutation rate omputation Tranition la appearane omputation Figure 3. Etimation flow ued for bu omputation reult

4 By the ame way, the probability of appearane of eah tranition la i obtained by omputing the ratio between the ourrene number of eah tranition la ompared to the total number of tranition ourrene. When onfiguration i done, Interonnet Explorer provide to the uer, in the output window, reult in term of: energy onumption, tati power onumption, average dynami power onumption, maximum dynami power onumption, intantaneou dynami power onumption, maximum frequeny allowed on bu (determined by wort ae tranition), area on the bu (determined by wire and buffer), ommutation rate per bit (ueful to evaluate performane optimization tehnique), and perentage of appearane of eah tranition la of Table I (ame remark a above). III. TEMPORAL LASSIFIATION VS ONSUMPTION LASSIFIATION In the tate of the art on performane optimization for interonnet, mot of the propoed tehnique ue the elimination of mot tediou tranition lae of Table I (i.e. 1+3r and 1+4r). For intane, we an ite hielding [13-14], kewing [15] and temporal oding [16] tehnique. A thee tehnique aume that the tranition that are the mot tediou for delay are the ame for onumption, we heked thee reult uing Interonnet Explorer. A. Tranition table validity Experiment have been arried out uing our tool on metal layer reerved for bue with a typial length of 1mm in a 65nm tehnology (let u note that reult are the ame for other tehnologie and metal layer). Table II how propagation time and power onumption for different tranition pattern of bu data. Reult are given for imple bufferization ae of Fig. 4.a. Reult of Table II (tranition are laified from the weaket value to the tronget) how that the temporal tranition laifiation, aording to the importane of the apaitane een by the vitim wire, i the ame that the one preented in Table I. In a eond time, it i important to note that the tranition laifiation, in onumption point of view, i not imilar to the time laifiation. Table II, for it onumption etion, an be divided into two part: In the high part of the table, tranition are exluively riing and are laified from thoe having the lowet apaitane to thoe having the tronget. In the low part of the table, tranition are exluively falling and are laified in the ame manner. It i very important to note that the power onumption ued by riing tranition i alway imilar, wherea for falling one the power onumption inreae with the growth of the apaitane. TABLE II. TEMPORAL AND ONSUMPTION LASSIFIATION OF TABLE I TRANSITION PATTERNS Temporal laifiation onumption laifiation (-, -, -) 0 0 p (-, -, -) fj (,, ) 49 p (,, ) fj (,, ) 49 p (-,, ) fj (-,, ) + 67 p (-,,-) fj (-,, ) + 67 p (,, ) fj (,, ) p (-,, ) fj (-,,-) p (,, ) fj (-,,-) p (,, ) fj (,, ) p (-,, ) fj (-,, ) p (-,,-) fj (-,, ) p (,, ) fj (,, ) p (-,, ) fj (,, ) p (,, ) fj In order to undertand why falling tranition onume more than riing one, it i neeary to know when the urrent i extrated from the power upply. Two ae an be onidered. Interonnet line an be imply bufferized (one input buffer and one at the end of the line, Fig. 4.a) or full bufferized (Fig. 4.b) aording to the deired performane. Depending on tranition type (riing or falling), line apaitane (or line egment in a full bufferization ae) are harged or not, a illutrated by Fig. 4. For imple bufferization (f. Fig. 4.a), when a riing tranition our the NMOS tranitor i ativated, and thu the line apaitane i not harged through the power upply. In the other ae, when a falling tranition our, it i the PMOS tranitor whih i ativated, and thu the line apaitane i harged by the urrent oming from the power upply. For full bufferization (f. Fig. 4.b), buffer whih are inerted on the line mut be even o that ignal at the output of the line i the ame a at the input. Thu, there i alway an additional egment to be harged with falling tranition ompared to riing one. onequently, falling tranition are more penalizing in term of power onumption than riing one. To um up, experiment allow u to onlude that, temporal wort ae tranition are not equal to onumption wort ae tranition, ine riing tranition onume more energy than falling one (all laified aording to the importane of the apaitane preented by the line). In the riing ae, power onumption varie from only 5.6% around the average value, and all tranition an be laified in the ame ategory. In fat, power onumption for riing tranition i due to hortut path between the power upply and the ground during output withing. A performane optimization tehnique are motly applied to the entire bu, we have etimated where the major part of power onumption i loated.

5 MSB LSB P tranitor i ative Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 N tranitor i ative Wire tranition a) 3.5% 11.5% 22.9% 33.9% 44.3% 48.9% 49.9% 50.0% Ativity onumption(bit0 + Bit1 + Bit2) = 55% onumption(bit0 + Bit1 +Bit2 + Bit3) = 71% onumption(bit0 + Bit1 + Bit2 +Bit3 + Bit4) =84% b) Total onumption ratio Figure 4. Line or egment harged (in bold) aording to bufferization tate B. Where i power onumption? Bu power onumption i eentially dynami and mainly depend on the apaitane preented by the wire and on it data ativity. Fig. 5 preent at the top the ativity of eah wire on a bu for image data. The power onumption of leat ignifiant bit i given ompared to the overall power onumption. A an example, the four leat ignifiant bit onume 84% of the total power for image data. Finally the perentage of time that eah tranition la appear i given at the bottom of Fig. 5. It an be notied that power onumption i primarily loated on the leat ignifiant bit (more than 50% power onumption for the lat three bit). So, optimization tehnique, whih try to redue power onumption on all bit, will have very redued effet on mot ignifiant bit ine their ativity i weak [18]. It i important to note that other data flow uh a piture, mui, talking follow the ame behaviour. Fig. 6 illutrate, for Bu Invert [17] and ode 2 [16], the energy bu ratio of oded and non-oded data a a funtion of the number of bit on whih the tehnique are applied. For our example, the optimal ae i when the tehnique i applied on 9 bit. Another intereting reult i that, tehnique whih have for aim to remove the wort ae of Table I (i.e. 1+3r and/or 1+4r), remove only a negligible part of the total tranition. For example, 1+4r tranition type appear only 1% of time. Eliminating thi wort ae tranition will therefore have a negligible impat on the global power onumption. Therefore removing thee tranition will dereae bu propagation time, but will not ytematially dereae power onumption. Indeed, 1+3r and 1+4r tranition are replaed by other oded tranition whoe onumption an be more ignifiant (a riing tranition an be tranformed into a falling one for intane). g = % g = 1 2.4% g = 1+r 6.2% g = 1+2r 12.7% g = 1+3r 10.8% g = 1+4r 1.0% Tranition la appearane ratio Figure 5. Ativity / onumption / Tranition la appearane Moreover, we notied that, when reult of power onumption optimization tehnique are preented, author do not alway take the overhead power onumption introdued by ode into aount.. What about ode power overhead? Muh of the propoed tehnique have a oniderable hardware and thu power onumption overhead to arry out the data oding. To be effiient, it i eential that the power onumption overhead, due to the ode, i lower than the gain generated by thee optimization method. Thi i unfortunately not anymore the ae for mot of method already developed, beaue ode omplexity i often important (regiter file, adder, multiplexer and o on). In [19], author how that, in order to be effiient, tehnique mut be applied on bue with extremely long wire, whih i in ontradition with wire length that an be found in ytem-on-hip. Figure 6. Perentage of bu redution energy in omparion with number of bit where tehnique are applied

6 IV. ONLUSION Thi paper ha firt preented the phyial parameter for wire and a bu modeling onidering rotalk apaitane. rotalk problem have been diued and how that delay and power onumption on interonnet mut take thi phenomenon into aount. Our delay and power onumption modeling methodology baed on SPIE imulation and haraterization ha been preented a well a our developed etimation tool alled Interonnet Explorer. Some analyi on tranition pattern laifiation from a power onumption point of view allowed u to underline the fat that the laial tranition pattern laifiation an not be ued in the ae of power onumption. When looking at the energy bu redution effiieny, reult have hown that tate-of-the-art optimization tehnique hould be applied where ativity i the tronget on bue (i.e. on leat ignifiant bit). To onlude, our future work on time and power onumption optimization tehnique will addre the four key iue: Do not only optimize wort-ae (1+3r and 1+4r) tranition. Fou on the line where data ativity i the mot important of the bu (i.e. LSB). Try to avoid falling tranition a muh a poible. Try to have a ode power overhead the weaket poible and o fou on a imple a poible tehnique. [9] J.M. Rabaey, A. handrakaan, and B. Nikoli, Digital Integrated iruit : A deign perpetive. Pearon Eduation, hapter 5, pp , [10] H.B. Bakoglu, and J.D. Meindl, Optimal interonnetion iruit for VLSI IEEE Tran. on Eletron. Devie, Vol. 32, No. 5, pp , 1985 [11] A. Nalamalpu and W.P. Burleon, Optimal wire izing and buffer inertion for low power and a generalized delay model, Proeeding of the IEEE international onferene on ASI/SO, [12] G. hen and E.G. Friedman, Low-power repeater driving R and RL interonnet with delay and bandwidth ontraint, IEEE Tran. on VLSI, Vol. 14, No.2, pp , 2006 [13] S.P. Khatri, R.K. Brayton, and A.L. Sangiovanni-Vinentelli, rotalk Noie Immune VLSI Deign Regular Layout Fabri, Kluwer Aademi Publiher, [14].N. Taylor, S. Dey, and Y. Zhao, Modeling and minimization of interonnet energy diipation in nanometer tehnologie, Proeeding of the 38th onferene on Deign automation, pp , [15] K. Hiroe and H. Yauura, A bu delay redution tehnique onidering rotalk, Proeeding of the onferene on Deign, automation and tet in Europe, pp , [16] J.M. Philippe, S. Pillement, and O. Sentiey, Area effiient temporal oding heme reduing rotalk effet, Proeeding of the International Sympoium on Quality Eletroni Deign, pp , [17] M.R. Stan and W.P. Burleon, Bu-invert oding for low-power I/O, IEEE Tran. on Very Large Sale Integration Sytem, Vol. 3, pp , [18] P. E. Landman, and J. M. Rabaey, Arhitetural power analyi: the dual bit type method IEEE Tran. on Very Large Sale Integration Sytem, Vol. 3, No. 2, pp , 1995 [19]. Kretzhmar, A.K. Nieuwland, and D. Muller, Why tranition oding for power minimization of on-hip bue doe not work, Proeeding of the onferene on Deign, automation and tet in Europe, pp , AKNOWLEDGMENT Thi work ha been upported by the European Union and the Brittany region in the ontext of Programme Objetif 2 Bretagne REFERENES [1] N. Magen, A. Kolodny, U. Weier and N. Shamir, Interonnet-power diipation in a miroproeor, Proeeding of the international workhop on Sytem level interonnet predition, pp. 7-13, [2] R. Ho, K. Mai and M. Horowitz, The future of wire, Proeeding of the IEEE, Vol 89, No 4, pp , [3] ITRS Tehnial report. International Tehnology Roadmap for Semiondutor, [4] W.J. Dally and J.W. Poulton, Digital Sytem Engineering, ambridge Univerity Pre, [5] J.M. Rabaey, A. handrakaan, and B. Nikoli, Digital Integrated iruit : A deign perpetive, Pearon Eduation, hapter 4, pp , [6] A. Devgan, Effiient oupled noie etimation for on-hip interonnet Proeeding of the IEEE/AM International onferene on omputer Aided Deign, pp , 1997 [7] J.M. Rabaey, A. handrakaan, and B. Nikoli, Digital Integrated iruit : A deign perpetive, Pearon Eduation, hapter 9, pp , [8]. Duan and S. P. Khatri, Exploiting rotalk to peed up on-hip bue, Proeeding of the onferene on Deign,automation and tet in Europe, Vol. 2, pp , 2004.