A Markov Decision Approach for the Computation of Testability of RTL Constructs

Transcription

1 A Makov Decision Appoach fo the Computation of Testability of RTL Constucts José Miguel Fenandes Abstact In the analysis of digital cicuits, to study testability estimation measues, dissipated powe and electomagnetic infeence,it is cucial to obtain with pecision the switching pobability of the cicuit intenal nodes. By solving the Chapman-Kolmogoov equations that descibe the steady state behaviou of the cicuit, we can calculate the pobability associated with each state of the MC that epesents the undelying FSM [6][7]. By supevising the behaviou of the MC, the allowed events, associated with a tansition pobability, will conduct the MC to the states whee we obtain highe levels of contollability/obsevability fo the intenal vaiables. If we model the poblem as a Makov decision pocess (Contolled Makov Chain), we can solve it using Dynamic Pogamming Methods (DP). This way, the tansition pobability between states will follow, not a fied distibution, but instead some contollable distibution using a set of contol actions.. Intoduction Validation of RTL desciptions emains one of the pincipal bottlenecks in the cicuit design pocess. The steady gowth in compleity of integated cicuits and the need to educe the time to maket of poducts has contibuted to incease the pecentage of time spent in cicuit veification. This veification is impotant both in the design phase (functional veification) and in the post- manufactuing test phase (defect testing). In both cases, the eistence of appopiate test vectos is citical to ensue defect fee cicuits and to avoid the need fo costly e-design cycles. Thee ae essentially two appoaches fo the veification of RTL desciptions: simulation based methods and fomal veification methods. Simulation based methods ty to eecise all pats of the cicuits by using a high numbe of vectos, obtained eithe by using knowledge of the design o by using some pseudo-andom test vecto geneato. Fomal based methods can be used to veify RTL desciptions against oiginal specifications of the cicuit, sometimes obtained fom behavioual desciptions. Simulation based method equie the eistence of appopiate test vectos. Regettably, automatic geneation of test vectos at highe abstaction levels [2] fo comple designs emains an open poblem, although significant advances have been made in this field [3][4]. The key poblem is that andom vectos don t eecise adequately the had to each conditions that lead to the eecution of the dak spots in the design, and efficient algoithms fo sequential test patten geneation ae unlikely to eist since the poblem is known to be PSPACE-complete.[5] Veification based appoaches, on the othe hand, equie the eistence of fomal highe level specifications that ae not always available. Futhemoe, algoithms fo fomal veification of sequential cicuits ae also inheently comple, although advances in heuistics have made them applicable in a wide ange of designs [8]. The pesent wok addesses this poblem by poposing an appoimate statistic modeling appoach that obtains accuate estimates of the contollability/obsevability of RTL constucts. These estimates can be used to impove the design and test pocesses in a numbe of ways. In the design phase, they can be used to infom the designe that a given constuct is not being adequately tested and that it may equie changes o some othe manual intevention. Ou appoach is specially appopiate fo this type of intevention, since thee is a vey close connection between the RTL constucts and the intenal model signals whose testability is being evaluated. At this level, it can also be used to bias the geneation of andomized tests, in ode to achieve adequate functional coveage of had to test constucts. Ou appoach is based on a statistical modeling and addesses the contollability/obsevability of stuctues diectly at the RTL level. In this way, the feedback given to the designe is easie to use, since testability esults ae given in tems of RTL constucts and not in tems of post-synthesis logic nodes. This wok solve the Chapman-Kolmogoov equations that descibe the steady state behaviou of the cicuit, which can be used to compute the pobability associated with each state of the MC. The events allowed by the supeviso ae associated with a tansition pobability. By contolling these pobabilities is possible to conduct the MC to the states whee we obtain

2 highe levels of contollability/obsevability fo the intenal vaiables[7]. Using DP methods we model the system as a Makov Decision Pocess. Fo that pupose, the tansition pobability between states will follow a contollable distibution, using a set of contol actions. 2. Poblem Fomulation Duing the design pocess seveal abstaction levels ae nomally used to achieve apid development of digital cicuits. Fom the algoithmic to the physical level, design testability assessment is an impotant issue. Accuate assessment of the testability of a given pat of a design is impotant not only because it avoids poblems in the poduction testing phase, but also because it makes sue that the design is being popely tested fom a functional point of view. In paticula, the eistence of dak spots in the design, i.e., blocks o constucts that ae not being popely eecised is to be avoided in an agile development pocess. In this wok, we model the behavio o the RTL desciption of a cicuit using a discete time Makov chain. Fo the most geneic case, that of sequential cicuits, we ae inteested in the cicuit behavio in the steady-state. This is impotant because, fo sequential cicuits (e.g., countes, shift-egistes, contol systems), many constucts only become active and eecisable when a given set of conditions is met. By computing the steady-state behavio of a cicuit, we make sue that the pobabilities of occuence of events ae calculated with pecision, even if the events ae ae o depend on vey specific input conditions. The method descibed hee solves the Chapman-Kolmogoov equations that descibe the steady state behavio of the cicuit, and calculates the pobability associated with each state of the Makov chain. To educe the computation effot and cope with lage designs we use symbolic epesentation methods that descibe the cicuit function using Binay Decision Diagams (BDD). Figue epesents the geneal scheme of a geneic synchonous sequential cicuit. Its behavio can be epesented by a tansition gaph, modeled by a tuple ( Σ,, χ,, δ, λ) whee Σ is a finite set of input symbols, is a finite set of output symbols, χ is a finite set of states, χ is the initial eset state, δ : χ Σ χ is the tansition function, and λ : χ Σ is the output function. Fig. : Scheme of a geneic synchonous sequential cicuit Unde athe geneal assumptions, the FSM associated with any synchonous sequential cicuit can be modeled by a Makov chain and the equations that descibe the steady state pobabilities of each state in the tansition gaph (the Chapman-Kolmogoov equations) have a unique solution. Moe pecisely, attaching to each out-going edge of each state in the taget FSM a tansition pobability that coesponds to a paticula tansition, one actually obtains a MC. As an eample on how to model the behaviou of an RTL desciption, lets considee the following FSM, that epesents an hadwae cicuit to validate a BCD wod with 4 bits: A B Fig. : FSM of the BCD validation cicuit The used alphabet Σ is the following: C Symbol Desciption Logic zeo Logic one Don t cae Reset signal F D G E Table : Alphabet fo the BCD validation cicuit Σ = χ = = {,,, } { A, B, C, D, E, F, G} A

3 As can be obseved in fig., the open loop ealization of the poposed hadwae cicuit will geneate a language L(G) with the following stings: uncontollable event is the (Reset) signal. All the othes ae contollable and obsevable. Evey fou input symbols, the system gives a validation signal fo the BDC wod. Sting Valid Y/N Y Y Y Y Y Y Y Y Y Y N N N N N N Table 2: L(G) fo the BCD validation cicuit As showed in table 2, thee ae some stings geneated by the open loop FSM that ae not allowed (not valid BDC wods). 3. Supeviso ealization To implement the supeviso, a PN has been chosen: The objective is to design a supeviso S fo the admissible language L a (G) given a set of uncontollable events E uc. In closed loop the system is epesented in Fig. 3: S s S G L( S / G) Fig.2: Closed loop epesentation of the cicuit Validation We ae using the concepts of supevisoy contol applied to an hadwae design cicuit, to implement a supeviso that foces the cicuit to comply with a set of specifications. The events ae followed by the supeviso that, knowing the system cuent state, decides on the symbols allowed to be visualized by the system (policy ). The only S s Fig. 3: PN ealization fo the supeviso With this supeviso ealization, the invalid stings and ae not allowed in the L( S / G) language. The symbol (don t cae) may epesent a o a. Rule: IF (bit 2= OR bit 3=) => bit Makov Chain As showed in fig. 2, the closed loop epesentation fo the system is composed by a single seve with an infinite queue fo the aival symbols. The seve can only pocess a symbol at a time. The symbol aival can be epesented by a Poisson distibution with aveage value λ. Symbols ae pocessed following an eponential distibution with aveage value µ. As stated befoe, the tansition pobability between states will follow a contollable distibution, using a set of contol actions. The goal is to each the maked state following an event sequence that minimize a given cost function ove a specified inteval. 4. CTMC

4 Makov pocesses have the memoyless popety. Knowing the cuent state fo the system, the futue state only depends on epessed as k k and not on the past histoy []. This can be P[ X ( t ) X ( t ) =, X ( t ) =,..., X t = ]= k+ = k+ k k k k ( [ X t ) X ( t ] P ( k+ = k+ k ) = k () fo any t t... t k tk +. The MC epessed this way is called a lag-one MC. The conditional pobabilities P [ X ( tk+ ) = k+ X ( tk ) = k ] ae called single-step tansition pobabilities and epesent the conditional pobabilities of making a tansition fom state X ( t k ) to state X ( t k+ ) at time step k. In homogeneous MC these pobabilities ae independent of k and consequently witten as P = P( X + = j X fo all k=,2, k k = To calculate the tansition pobabilities [], we must geneate a tansition ate mati Q. The ate associated with a state tansition is epesented in this mati. Then, a tansition pobability mati P can be deived. As eplained in [], a GSMP with a Poisson clock stuctue educes to a MC and inheits the memoyless popety of the Poisson pocess. The state holding time V ( at state i has an eponential distibution Λ( t [ ] P V ( t = e, t (2) with Λ( = λ (3) e Γ( Λ( is the sum of the Poisson ates of all active events at state i, e is a feasible event at state i, and Γ( is the set of all feasible events at state i. To obtain the tems fo the Q mati, afte futhe manipulation [] we obtain the esults: and q ii = Λ( q P (4) = λ (5) Consideing a cicuit with N egistes. The state space χ = {,,..., M } to eploe has, in the wost case, N M = 2 possible states. Assume that the system is in state i. Unde the Makov assumption, the tansition between state i and j occus with pobability P, unde some specific, time invaiant, input distibution. Then, in steady state, the pobability of state i is given by: P ( j ) = π P( i ) (7) i with P ( j ) =. j Let s associate ates to the tansitions of diagam epesented in Fig.. Tansitions with events, o, have the same ate of. Tansition associated with the eset signal have a ate of µ. 4.2 DTMC Thee ae applications wee discete time models ae moe convenient to model the systems unde study, because geneally ae easie to set up and simple to analyse. Having specified the tansition ate mati Q of the CTMC, we can obtain the equivalent DTMC using a unifomization pocess based on the choice of a unifom tansition ate defined by the following elation ma { } q ii i χ with tansition pobabilities U P q = qii +, i j, i = j Fo ou eample, we can choose a unifom ate of and obtain fo the U P = µ + 2 mati (8) (9) - q ii epesents the total event ate chaacteizing state i, q is the instantaneous ate at which a state tansition fom i to j takes place. Fo a GSMP with Poisson clock stuctue, being at state i the pobability of a tansition e to state j is P q =, j i (6) q ii

5 U P µ + µ µ µ = µ µ µ 5. Optimal Contol Policy Vk+ ( = min C( i, u) + P ( u) Vk ( j) u U i j (2) consideing a N step finite vesion of the poblem, with V ( = fo all i, k =,..., N. Fo the specific eample poposed, because the system has to validate a 4 bits BCD wod, we conside N=4. As defined befoe, ou goal is to to conduct the MC to the states whee we obtain highe levels of contollability/obsevability fo the intenal vaiables. In this eample we have only one maked state (E). Then we can define the following contol action: = at states D o G othewise The closed loop system eliminates fom L(S/G) the fobidden stings of the L(G) language. Addicionaly, by using dynamic pogamming techniques is possible, with the automaton epesentation of the system (o the equivalent state tansition diagam of the implicit FSM), to obtain the optimal sequence of actions that minimizes a given cost function ove a specified time inteval. Having the pobability tansition mati P and the set of possible contol actions fo each state, is possible to find the policy that minimizes the cost associated with the optimal opeation of the system. Consideing the poblem of finding an optimal policy π unde an infinite undiscounted hoizon, if at a time t the state is X (t) then a specific action t) is taken which depends on (t), and the esulting cost is C X ( t), t). Then we have fo the total epected undiscounted cost ove an infinite hoizon X [ ] Vπ ( ) = Eπ [ ] () C X ( t), t) dt whee is the initial state. Having a DTMC with unifom tansition ate, equation () is conveted to the equivalent one E π [ C X k, u k ] () K = Unde the assumption that the cost is bounded ( C( j, u) K ) fo all states j and all contol actions u U j, we can define () ecusively and fo the cost function: [ i ] 2 C( i, u) = C + ) C with C 2 > C. Many cicuits of inteest descibed at the egiste tansfe level ehibit stuctues that lead to vey deep state tansition gaphs. Fo instance, a 6 bit counte with a eset signal cannot be easonably tested by andom pattens, since the eset signal needs to be held inactive fo a long peiod in ode to let the count poceed. This is also the case of ou eample, as showed in the net chapte. Fo instance, in this case, the validate signal at state E, and any pats of the RTL code that depend on the activation of this signal, will be not be well tested unless the eset signal is actuated with vey low pobability. This means a low ate µ, and a bigge ate, which is in accodance with the U mati P. A possible algoithm that can solve this poblem is pesented:. Geneate CDFG of each FSM 2. Fo each CDFG { 3. Geneate espective MC (steady state) 4. Calculate the pobabilities to contol/obseve the vaiables 5. Identify citical vas v i to contol/obseve 6. Fo each v i { 7. Identify the states of the espective MC 8. Find the inputs vectos (event sequence) that will eecise these states 9. Establish the Optimal Contol Policy fo enteing these states with minimal cost. }. }

6 6. Results Ou tool calculates the pobability of contolling/obseving intenal egiste signals, togethe with pimay inputs, fo diffeent eset pobability values.. These esults ae pesented in the net tables. Reset pobability input,5,5,5,5,5 state(),437,4366,4355,4325,4228 state(),3695,364,3527,3297,288 state(2),4396,454,4322,36,3252 validate,495,429,34,73,694 Table 3: Vaiable Contollability esults The contollability deceases fo the validate signal, when the eset pobability inceases. Reset pobability input,,,,, state(),2655,2537,239,89,22 state(),237,2247,24,6,966 state(2),889,24,224,2556,2988 validate,,,,, Table 4: Vaiable Obsevability esults Obseving the validate signal is also moe difficult fo a bigge eset pobability. Reset pobability A,33,3,323,75,252 B,255,253,256,267,27 C,242,234,26,78,84 D,63,6,578,53,434 E,54,466,372,92,867 F,242,234,26,78,84 G,84,84,733,59,3 In this wok we pesented a method to conduct the MC, that models the tansition pobabilities of a FSM associated with an hadwae cicuit, to the states whee we obtain highe levels of contollability/obsevability of intenal vaiables. Using Dynamic Pogamming methods we model the system as a Makov Decision Pocess. Fo that pupose, the tansition pobability between states will follow a contollable distibution, using a contol action. Refeences [] Chistos Cassandas, Stéphane Lafotune, Intoduction to Discete Event Systems, Kluwe Academic Publishes, Massachusetts, 999. [2] Cho C. H., Amstong J. R., B-Algoithm: A Behavioal Test Geneation Algoithm, Poc. IEEE Intenational Test Confeence (ITC), pp , 994. [3] Feandi F., Fummi F., Sciuto D., Implicit Test Geneation fo Behavioal VHDL Models. Poc. IEEE Intenational Test Confeence (ITC), pp , 998. [4] Feaa G., Feandi F., Fin A., Fummy F., Sciuto D., Functional Test Geneation fo Behavioally Sequential Models, Poc. of the Design Automation and Test in Euope Confeence (DATE), pp. 43-4, Mach 2. [5] Feitas A. T., Neto H. C. and Oliveia A. L.. On the compleity of powe estimation poblems. In Intenational Wokshop on Logic Synthesis (ILWS), pages , June 2. [6] J.M. Fenandes, M.B. Santos, A. Oliveia, J.P. Teieia, "A Pobabilistic Method fo the Computation of Testability of RTL Constucts", Poc. of the Design Automation and Test in Euope (DATE) Conf., pp. 76-8, 24. [7] Santos M.B., Fenandes J.M., Teieia I.C., Teieia J.P., RTL Test Patten Geneation fo High Quality Loosely Deteministic BIST, Poc. of the Design Automation and Test in Euope Confeence (DATE), pp , Mach 23. [8] Ken C., Geensteet M.R., Fomal Veification In Hadwae Design: A Suvey, ACM Tansactions on Design Automation of Electonic Systems, 4:2, pp , 999. Table 5: State pobability esults Also fo state E, the only maked state whee the validate signal is activated, its pobability deceases when eset pobability inceases. The same happens to states D and G, which ae the pedecessos of state E. 7. Conclusions