A Deep Convolutional Neural Network Based on Nested Residue Number System

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1 A Deep Convolutional Neual Netwok Based on Nested Residue Numbe System Hioki Nakahaa Ehime Univesity, Japan Tsutomu Sasao Meiji Univesity, Japan Abstact A pe-tained deep convolutional neual netwok (DCNN) is the feed-fowad computation pespective which is widely used fo the embedded vision systems. In the DCNN, the D convolutional opeation occupies moe than 9% of the computation time. Since the D convolutional opeation pefoms massive multiply-accumulation (MAC) opeations, conventional ealizations could not implement a fully paallel DCNN. The RNS decomposes an intege into a tuple of L integes by esidues of moduli set. Since no pai of modulus have a common facto with any othe, the conventional RNS decomposes the MAC unit into cicuits with diffeent sizes. It means that the RNS could not utilize esouces of an FPGA with unifom size. In this pape, we popose the nested RNS (NRNS), which ecusively decompose the RNS. It can decompose the MAC unit into cicuits with small sizes. In the DCNN using the NRNS, a 48-bit MAC unit is decomposed into 4-bit ones ealized by look-up tables of the FPGA. In the system, we also use binay to NRNS convetes and NRNS to binay convetes. The binay to NRNS convete is ealized by on-chip BRAMs, while the NRNS to binay one is ealized by DSP blocks and BRAMs. Thus, a balanced usage of FPGA esouces leads to a high clock fequency with less hadwae. The ImageNet DCNN using the NRNS is implemented on a Xilinx Vitex VC77 evaluation boad. As fo the pefomance pe aea GOPS (Giga opeations pe second) pe a slice, the poposed one is 5.86 times bette than the existing best ealization. I. INTRODUCTION A. Deep Convolutional Neual Netwok (DCNN) A deep neual netwok (DNN) consists of multi-laye neuon model. A deep convolutional neual netwok (DCNN) is a combination of the D convolutional layes and the DNN. Since the DCNN emulates the human vision, it has a high accuacy fo an image ecognition. The DCNN is widely used fo embedded vision systems including a hand-witten ecognition [4], a face detecto [9], a scene detemination [8], and an object ecognition []. In the embedded vision system, since the leaning is done by off-line, we can only conside the execution of pe-tained DCNN fo the un-time envionment. With the incease of the numbe of layes, the DCNN can incease ecognition accuacy. Thus, a lage scale DCNN is desied. Since the existing system using a CPU is too slow, the acceleation of the DCNN is necessay fo the eal-time equiement of the embedded vision systems [4]. Most of the softwaebased DCNNs use the GPUs [3], [8], [3], [4]. Unfotunately, since the GPU consumes high powe, they ae unsuitable fo the embedded system [9]. Thus, the FPGA-based DCNN is equied fo low-powe and eal-time embedded vision system. As fo the ecognition accuacy, the DCNN using a fixed point epesentation is almost the same as one using a floating point epesentation []. The FPGA can use an appopiate low pecision epesentation which educes the hadwae esouces and inceases the clock fequency, while the GPU cannot do it. Anothe meit of the FPGA is a lowe powe consumption than the GPU. A pevious wok [9] showed that, as fo the pefomance pe powe, the FPGA-based DCNN is about times moe efficient than the GPU-based one. Recently, the Micosoft implemented a high pefomance pe powe DCNN by using the FPGA cluste (Catapult) [6]. In the DCNN, the D convolution occupies moe than 9% of computation time [7]. Thus, in this pape, we conside the acceleation of the D convolution, which can be ealized by massive MAC (multiply-accumulation) opeations. Although the moden FPGA has DSP blocks (DSP48E fo the Xilinx FPGA) fo the MAC opeations, a lage scale DCNN equies O(n n ) DSP48Es, whee n is the pecision of the fixed point epesentation. Thus, a DCNN with a high pefomance pe aea is desied. B. Related Wok The leaning and pedict by an atificial neual netwok was implemented on the FPGA [5]. The basic D convolutional cicuits wee epoted in [], [9]. The efficient utilization of both on-chip and off-chip memoies was discussed in []. The geneal classifie including the DCNN was consideed in []. Vaious optimization techniques fo the DCNN on the FPGA wee poposed: Reduction of multiplies by dynamic econfiguation [4]; optimization of the memoy bandwidth [8], and selection of optimal paametes fo the high-level synthesis design [6]. C. Poposed Method In this pape, we popose an aea-pefomance efficient DCNN by educing MAC units. Fist, we use a esidue numbe system (RNS) [], [5] to decompose n-input MAC units into smalle ones. Then, we ealize the small MAC units by LUTs on an FPGA. The RNS decomposes an intege into a tuple of L integes by esidues of moduli set. In the conventional RNS, since no pai of modulus have a common facto with any othe, the esulting MAC unit have diffeent sizes. This means that even if we used the RNS, we cannot utilize the FPGA esouces of unifom size. In this pape, we popose the nested RNS (NRNS), which ecusively decompose the numbes in RNS. By using the NRNS, we can decompose the MAC unit into smalle ones with unifom sizes. In the DCNN, since the NRNS decomposes the 48-bit fixed point MAC units into 4- bit ones, they can be implemented by 8-input 4-output LUTs.

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3 implementation [4]. In this case, the D convolution woks with log = 3 bits epesentation. Afte convolution, the output is ounded to 48 bits. Since it equies excessive MAC units (DSP48Es), implementation of a fully paallel D convolutional cicuit is had. In this pape, we decompose the n-input MAC unit by the nested esidue numbe system (NRNS). III. A. Definition RESIDUE NUMBER SYSTEM (RNS) A esidue numbe system (RNS) [], [5], is defined by a set of L intege constants m,m,...,m L, whee no pai of modulus have a common facto with any othe. An abitay intege Z can be uniquely epesented by the RNS as a tuple of L integes (Z,Z,...,Z L ), whee Z i Z (mod m i ). M = L i= m i is a dynamic ange of the RNS. In the RNS, the addition, the subtaction, and the multiplication can be pefomed in digit-wise. Let X and Y be integes, x i and y i be integes in the RNS defined by m i ( i L), includes + (addition), (subtaction), and (multiplication). Then Z = X Y satisfies Z =(Z,Z,...,Z L ), whee Z i = (X i Y i ) mod m i. Note that, the division is not included in the opeations. Example 3.: Let m,m,m 3 = 3, 4, 5 be the moduli set. Conside the multiplication X Y, whee X =8and Y =. Since X Y =6, it is epesented by (,, ) in the RNS. X and Y is epesented by (,, 3) and (,, ) in the RNS, espectively. Thus, X Y in the RNS is computed as follows: X Y = (4 mod 3, mod 4, 6 mod 5) = (,, ). In the RNS, the aithmetic opeation is pefomed in digitwise. This means that a lage multiplie can be decomposed into smalle ones. In this pape, we ealize them by LUTs on an FPGA. The multiplie on the RNS equies additional esouces: A binay to RNS (BinRNS) convete and an RNS to binay (RNSBin) one. The moden FPGA has BRAMs and DSP48Es in addition to Slices. The usage of both BRAMs and DSP48Es fo the convetes hides the aea ovehead. In this pape, we implement the BinRNS convete by a cascade of BRAMs, while the RNSBin convete by the DSP48Es and BRAMs []. B. Realization of BinRNS Convete Let X =(x,x,...,x n ), whee x i = {, }. Conside the RNS m,m,...,m L fo X. The single ROM ealization of the BinRNS convete equies n L i= log m i bits, which is too lage to ealize fo a lage n. By applying functional decompositions [5], we can educe the total amount of memoy. Conside a function F (X) :B n {,,...m }, whee B = {, } and X =(x,x,...,x n ).Let(X L,X H ) be a patition of X into two pats. A decomposition chat of F is the two-dimensional matix, whee each column label has distinct assignment of elements in X L, and each ow label has x x Functional decompo- Fig. 6. BinRNS convete by paallel LUT cascades. Fig. 5. sition. H F(X) x = log G μ x n LUT cascade fo X mod m LUT cascade fo X mod m BRAM pipeline egistes k BRAM = log BRAM LUT cascade fo X mod m L x x x 3 x 4 x k k Fig. 7. Example of decomposition Fig. 8. chat (X mod 3). mod 3. m L x x x x 3 x 4 f An LUT cascade fo X distinct assignment of elements in X H, and the coesponding matix value is F (X L,X H ). The numbe of diffeent column pattens in the decomposition chat is the column multiplicity μ. X L denotes the bound vaiables, and X H denotes the fee vaiables. Fig. 5 shows the functional decomposition. Connections with adjacent LUTs ae called ails, whee = log μ. Let X L = n and X H = n. In this case, the total amount of memoy fo the functional decomposition is n + +n bits. By applying the functional decomposition ecusively, we have an LUT cascade []. Fig. 6 shows the BinRNS convete implemented by paallel LUT cascades. Fom the popety of modulo opeations, the column multiplicity fo each modulo m i is at most m i.lets be the numbe of 8Kb BRAMs with k inputs. As fo the LUT cascade fo modulo m i, fom Fig. 6, we have the following equation []: k +(s )(k ) n, whee = log m i and k> log m i. Then, we have n log m i s =. k log m i Example 3.: Assume that X = (x,x,x,x 3,x 4 ), X L = (x,x,x ) and X H = (x 3,x 4 ). Fig. 7 shows the decomposition chat fo Xmod3, and Fig. 8 shows its LUT cascade. Fig. 7 shows that the column multiplicity μ is 3, and the numbe of ails is log 3 =. The single ROM ealization fo the BinRNS convete equies 5 =64bits, while the LUT cascade ealization equies =48bits. C. Realization of RNSBin Convete To ealize the RNSBin convete, we use a fomula X i = x i M i mi M i, whee M i = M/m i, M i M i =

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