Defects and Faults in Quantum Cellular Automata at Nano Scale

Transcription

1 Defects an aults in Quantum ellular utomata at Nano Scale Mehi araaran Tahoori, Mariam Momenzaeh, Jing Huang, abrizio Lombari Department of Electrical an omputer Engineering, Northeastern University, oston, M, mtahoori, mmomenza, hjing, bstract There has been consierable research on quantum ot cellular automata (Q) as a new computing scheme in the nano-scale regimes. The basic logic element of this technology is majority voter. In this paper, a etaile simulation-base characterization of Q efects an stuy of their effects at logic-level are presente. Testing of these evices is investigate an compare with conventional MOS-base esigns. Unique testing features of esigns base on this technology are presente an interesting properties have been ientifie. 1. Introuction s the MOS technology approach it s funamental physical limits, there has been extensive research in recent years in nanotechnology for future generation I. It is anticipate that these technologies can achieve a ensity of evices/ an operate at THZ frequencies. mong these new evices, quantum ot cellular automata (Q) not only gives a solution at nano scale, but also it offers a new metho of computation an information transformation [15]. In terms of feature size, it is projecte that a Q cell of few nanometer size can be fabricate through molecular implementation by a self-assembly process. One of the funamental issues in the testing community is the raical shift in computation an fabrication technology an its effect on the test flow. Since the manufacturing process for nano evices is illefine, it is extremely ifficult to aress manufacturing testing problems. However, it woul be inappropriate to ignore testing of these evice till manufacturing state.this paper tries to aress this issue for one of the propose trens in nanometer era. or Q, the cells must be aligne precisely at nano scales to provie correct functionality, so proper testing of these evices for manufacturing efects an plays a major role for quality of Q base circuits. The basic logic element in this technology is the majority voter. Since the basic logic elements of Q-base esigns are ifferent from conventional MOS esigns, they nee ifferent testing schemes. In this paper, the efect characterization of these evices has been extensively stuie; effects of efects are investigate at logic-level. lso, testing of Q is compare with testing of conventional MOS implementations. Defect injection is exploite to stuy the behavior of Q-base circuits in the presence of efects an to measure the effectiveness of ifferent test sets in etecting them. The approach propose in this work is base on simulating ifferent manufacturing s, investigating their effects at logic level an ientifying the test vectors for etection of all faults. Different fabrication schemes of the majority voter at cell level are stuie; these ifferent implementations are compare in terms of efect tolerance an testability. lthough in the current MOS process only a small portion of the actual efects behaves like stuck-at faults, the stuck-at fault moel is still wiely use as the test sets generate base on this moel are quite acceptable. So it is possible to investigate effectiveness of stuck-at test sets for Q efects even though Q efect mechanisms cannot be moele by the stuck-at moel. This is aresse in this paper. The rest of this paper is organize as follows. In Sec. 2, a review of Q is presente. In Sec. 3, testing of Qbase esign at logic level is iscusse. In Sec. 4, the efect characterization of Q is presente. In Sec. 5, test set, efect an fault coverage are iscusse. inally, Sec. 6 conclues the paper. 2. Review Q is a novel nano evice that stores logic states not as voltage levels but rather base on the position of iniviual electrons. quantum cell can be viewe as a set of four charge containers or ots, positione at the corners of a square. The cell contains two extra mobile electrons which can quantum mechanically tunnel between ots, but not cells. The electrons are force to the corner positions by oulomb repulsion. The two possible polarization states represent logic 0 an logic 1, as shown in ig 1. Unlike conventional logic in which information is transferre from one evice to another by electrical current, Q oes so by oulomb interaction which connects the state of one cell to the state of its neighbors. This results in a technology in which information transfer (interconnection) is the same as information transformation (logic manipulation). igure 1 illustrates the cellcell response function, where the polarization P1 is inuce in cell 1 by the fixe polarization of its neighbor P2 [18]. P an P states inicate logic values 1 an 0 respectively. Power issipation in Q circuits is ultra low compare with conventional MOS circuits [15][18][19]. quantum cell 0.5 ot P1 0.0 cell 1 cell 2 "0" "1" 0.5 Polarization 1 Polarization +1 cell 1 cell P2 ig. 1. Q ell an ell-cell response [18] The basic logic gate in Q is the majority voter (MV). The 1.0

2 majority voter with logic function MV(,, ), can be realize by only 5 Q cells (compare to a MOS implementation which requires 16 transistors), as shown in ig. 2(b). Logic ND an logic OR functions can be implemente from a majority voter by setting one input permanently to 0 an 1, respectively. The Q Inverter is shown in ig. 2(a). Unlike conventional MOS in which it is the simplest block, it consumes consierable area in Q. The binary wire (as interconnect) an the inverter chain are shown in ig. 2(c)(). ig. 3. The Q implementation of logic networks using majority voters (implementing ND an OR) an Inverters (a) Inverter testing features which cannot be achieve in conventional MOS implementations. (c) inary Wire (b) Majority Voter () Inverter hain ig. 2. Q evices The concept of clocking for Qs has been introuce in [5]. Some esigns base on Qs incluing microprocessors, PG an memories have been propose [13][14][20][22][7]. stuy of the fault tolerant properties of the majority voter uner some manufacturing s [3][4][6] show that MV is more vulnerable to in the vertical irection than in the horizontal irection. (at least equal to half a cell with in the vertical irection) causes the MV to malfunction. ase on this simulation-base stuy, a fault tolerant MV block has been propose. urrently, micro-size Q evices have been fabricate with metal cells which operates at 50mK [15][1]. In [15], an experimental emonstration of a basic Q cell compose of four metal ots, connecte with tunnel junctions an capacitors is presente. In [2], builing of basic logic elements with these cells is emonstrate. It is anticipate that molecular scale ( 2nm) yiels operation of Q at room-temperature. In [11], some possible molecular realizations of Q have been propose. It escribes the progress towar making Q molecules an avances for surface attachment chemistry compatible with Q. 3. Logic-Level Testing The overall structure of the Q implementation of (combinational) logic esigns is shown in ig. 3. The block consists of an interconnection of majority voters an inverters. There are two system-level control lines, an, which are connecte to majority voters. is connecte to logic 0 an sets some majority voters as the ND function, whereas is connecte to logic 1 an sets other majority voters as the OR function. simple example is shown in ig. 4. These control lines can provie more controllability since these lines can be seen as extra input lines uring test time. This unique feature of Q can be exploite to achieve better testability. Since logic esigns are implemente as a network of majority voters an inverters (as the universal logic set) in Q technology, it is important to investigate the properties of these network, especially for test execution. s shown through the following statements, these networks have unique an interesting ig. 4. (a) a simple ND-OR logic (b) MV-base implementation onsier a majority voter with input lines,, an, an the output line ( ). Property 1. onsier a majority voter with input values a, b, an c, (for lines,, an, respectively) an output z. If the all inputs are flippe,, the output will be also flippe,. Note that this is not the case for other logic functions such as ND, NOR, etc. or example, consier a three input ND gate with inputs 100 an output 0. If the inputs are flippe to 011, the output will remain 0. Property 2. If there is inversion at any input an/or the output of the majority voter, property 1 still hols. Property 3. onsier a majority voter with input pattern (for lines,, an, respectively). The stuck-at-v fault on any input or output line of the voter is etectable (fault effect appears at output line) by if an only if the stuck-at- fault on that line is etectable by. Proof. onsier stuck-at- fault. If is an input line, consier the is, without loss of generality. The fault is etecte if an only if the value of is an the other inputs, an, have opposite values. s a result, is an an, have opposite values. Hence, etects the stuck-at-. gain, this property oes not hol for other logic functions. s an example, consier an ND gate with test vector 11 which etects stuck-at-0 at the top input (an the bottom input too). The complement of this vector, 00, oes not etect any single stuck-at-1 on the inputs. Property 4. If there are some inversions at any inputs an/or the output of the majority voter, property 3 still hols.

3 The interesting property of majority voters is that the above properties hol for any arbitrary network of majority voters (incluing inverters). Property 5. onsier an arbitrary network of majority voters (an inverters) with primary input vector V. If all bits of V are flippe,, all noes in the network will be flippe. Proof. The proof is base on inuction on the level (istance) of each majority voter in the network from the primary inputs, by forming a topological orer of the majority voters in the network. The step of inuction is property 2. Property 6. onsier an arbitrary network of majority voters (an inverters) with primary input vector. or any noe in the network, stuck-at- is etecte by, if an only if stuck-at- is etecte by. Proof. The proof is similar to the proof of property 5. The step of inuction is property 4. Property 5 an 6 are very interesting an prove unique features of a network of MVs (an inverters). ase on property 5, the test vector pair, where is any arbitrary vector, causes a transition on all noes of the network. lso, the three vectors cause both fall an rise transitions on all noes in the network. Hence, a 100% toggle fault coverage test set is applicable. ase on property 6, the fault list for any network of majority voters (an inverters) can be ivie into two parts: just one fault per each noe, because if a vector etects one stuck-at fault on that noe, will etect the other stuck-at fault on that noe. s a corollary, this feature can be exploite to reuce the size of the fault list, an hence TPG execution, for the control inputs (to be generate by TPG) into half. To generate tests for stuck-at faults in a network of MVs an inverters, conventional (combinational) TPG tools can be exploite. The network of MVs an inverters is first transforme into a hierarchical gate-level netlist. Each MV is replace by a hierarchical cell implementing the majority function. We only consier pin faults on the inputs of these hierarchical cells which correspon to the inputs of MVs. s explaine above, only half of the pin faults must be consiere for the test generation. 4. Defect haracterization In this section, the robustness of the Q majority voters an binary wires, as well as some Q circuits is investigate. The basic functionality of a Q evice is base on the oulombic interaction among neighboring Q cells (epening on the accuracy an geometry of its implementation). Various configurations of Q evices have been stuie using the QDesigner 1 v1.20 simulation tool. or accuracy, the bistable moel is employe. This is a quantum mechanical engine using the Jacobi algorithm to calculate the eigenvalues/vectors of the Hamiltonian matrix Defect an ailure Moes To perform a efect characterization of Q evices an circuits an stuy their effects at logic-level, appropriate efect 1 QDesigner is the prouct of an ongoing collaboration between the University of algary TIPS Laboratory an the University of Notre Dame. mechanisms an moels must be consiere which 1) can be simulate using the available simulation tool an 2) be realistic for manufacturing an fabrication efects. ccoring to [10], in the present stage of Q manufacturing, efects are possible in both synthesis phase an eposition phase. Manufacturing efects may cause a cell to have missing or extra ots or/an electrons. This will be fatal to the correct operation of the cell. However, efects are much more likely to occur in the eposition part than in the synthesis part which will result in cell misplacement. missing ot (or aitional ot) is very unlikely ue to the ease of purification of small inorganic molecules [10]. or example, Nuclear Magnetic Resonance (NMR) has an estimate minimum purity of 99% for moel compouns such as the reutz-taube Ion (a 2-ot cell moel). Moreover, electrochemical measurements for the T Ion show that fewer than one molecule in are in the incorrect charge state. Yet placing the iniviual cells in specific locations uring the eposition part is ifficult, various types of cell misplacement faults may occur such as cell, rotate cells, etc. Therefore in this paper we assume that all the cells are perfectly manufacture an operate correctly an stuy the effects of following types of cell misplacement faults: cell isplacement is a efect in which the efective cell is misplace from its original irection. Several cell isplacement efects are shown in ig. 5. In a cell efect, the irection of the efective cell is misplace. Some examples of cell s are shown in ig.6. In a cell omission efect, a particular cell is missing as compare to the original (efect-free) arrangement. The electron missing efect where the efective cell have no electrons can be moele by this type of efects. In this work, the following efects are consiere an simulate for Q evices: all possible combinations of isplacement of cells with respect to the central cell uner ifferent istances, of cells in ifferent irections. or Q circuits, cell omission efects are also simulate Majority Voter Defect nalysis efect free majority voter which has a ot size, a cell size, with a cell istance is consiere, as shown in ig. 5(a). Different efects in the majority voter, incluing cell isplacement an have been consiere an simulate. The results for cell isplacement an are shown in Table 1 an Table 2, respectively. Only faulty entries are shown in the tables, in the form of (faultfree/faulty) values. The ata shows that in most cases the horizontal input cell (i.e. cell ) is ominant; this cell seems to have a bigger impact on the center cell than an. or, any single cell greater or equal to half a cell causes malfunction (fault at logic-level). In some cases the fault margin is smaller. MM:please check the following: comparison between an isplacement efects illustrates that the efects have more catastrophic effects on the functionality of a majority voter, with the same efectiveistance as the isplacement efect.

4 (a) fault free () isplace all inputs an output ig. 5. (b) isplace (e) isplace all inputs (c) isplace (f) isplace an Displacement in Majority Voter Table 1 Results for Displacement in Majority Voter isplace cell : fig 5(2) Normal Operation, = isplace cell : fig 5(3) Normal Operation 001 Z (no polarization) 011 Z( no polarization) 100 Z (no polarization) 110 Z (no polarization) isplace all input/output cells: fig 5(4) or Normal Operation 010 0/1 =Z (no polarization) 101 1/0 isplace all input cells: fig 5(5) or Normal Operation =Z (no polarization) or 010 0/ / / / / /0 isplace cells an : fig 5(6) Normal Operation, = Table 2 Results for Misalignment in Majority Voter move towar west: fig 6(1) Normal Operation, = move towar east: fig 6(2) or Normal Operation 001 0/ / /0 = 110 1/0 move towar west: fig 6(3) Normal Operation = move towar east: fig 6(4) or Normal Operation 010 0/ / /1 = 101 1/0 move, towar west: fig 6(5) =, move, towar east: fig 6(6) = 000 0/1 Normal Operation 010 0/ / /0 move towar south/north: fig 6(7) Normal Operation 001 0/ / / /0 (a) (e), ig. 6. (b) (f), (c) () (g) Misalignment in Majority Voter 4.3. inary Wires an Inverter hains The effect of cell isplacement efects on two parallel binary wires as well as two parallel inverter chains have been investigate Double inary Wires: Two efect-free binary wires are shown in igure 7(a); these wires are enote as the upper wire ( to ) an the lower wire ( to ). The cells use in this simulation have a size of, an the ot iameter is. In the efect-free case, the cells in the same wire are separate by. The istance between the wires is. The isplacement efects are simulate by moving one or two cells in the lower wire towar the upper wire (by a isplacement ) as shown in igure 7(b). The simulation results are shown in Table 3. These results show that in most cases the lower wire is ominate by the upper wire. an are either equal to or, epening on which cell(s) are isplace an the value of the isplacement,. In most cases, the upper wire functions normally, i.e.. However, it can be observe that in some cases the upper wire behaves as an inverter. learly, unlike MOS esigns, the coupling efects at Q evice-level o not behave as the wire briging fault moel. However, these efects manifest themselves as a ominant moel (at logic level) in which the output of a wire is etermine by the value of the couple wire. i2 i1 i2 o2 cell 1 cell 2 cell 3 cell 4 (a) aultfree Double Wire i1 o1 i1 o1 cell 1 ig nm 60nm o2 i2 cell 1 (b) Defects in Double Wire o1 cell 3 Displacment in inary Double Wire Double Inverter hains: The ouble inverter chain is shown in igure 8(a). The simulation results for moving one of the cells in the bottom wire towar the upper wire, with isplacement, (as shown in igure 8(b)) are presente in Table 4. The isplacement efects behave as accoring to o2

5 Table 3 Results for Double inary Wires move cell1 OR cell2 Normal move cell3 OR cell4 Normal move cell1 ND cell2 Normal move cell1 ND cell4; OR move cell 2 ND cell 3; OR move cell3 ND cell4 Normal move cell1 ND cell3 Normal move cell2 ND cell4 =20-2 =30-3 Normal =40-4 Table 4 Results for Double Inverter hains ault ree: move cell1 OR cell2 OR cell3 Normal move cell4 Normal the ominating briging fault moel at logic level. Moreover, a comparison with the binary wires shows that the binary wires are more efect tolerant than inverter chains in the case of isplacement coupling efects. i1 i2 1 (a) ault ree Inverter hain o1 60nm 20nm ell1 ell2 ell3 ell4 o2 ig. 8. i1 i2 ell2 (b) Single ell Displacement Displacment in Double Inverter hains 4.4. Defects an aults in a ull-er Q implementation of a full aer using three majority voters an two inverters is shown in ig.9. The corresponing Q layout is shown in ig.10 which contains 145 cells. The cells are 18nm 18nm with ot size of. 40 ifferent single cell omission efects have been simulate in this circuit. n1 n2 n3 in ig. 9. n10 n12 n13 n9 n14 n15 n16 n4 M M n6 n11 n5 n17 M n8 out Sum One-bit Q full aer Defects in Wires an Inverter hain: Removing a single cell from a binary wire oes not affect its functionality at logic-level although it may result in some elay faults. However, a single cell omission in a wire implemente as an inverter chain results in an unwante complementation at the output of the chain. Those binary wires which change irection in the layout n7 o1 o2 (e.g. L shape) are very sensitive to the efects on the corner cells. ell omission efect at the corner cell is equivalent to unwante complementation fault at logic-level. ig. 10. One-bit Q full aer layout Defects in Wire rossing: In Q implementation, two ifferent wires (horizontal an vertical) can cross each other in the same layer (co-planar wire crossing). In this case, one of them is implemente as a binary wire, while the other one is implemente as an inverter chain (i.e. the cells in the other wire are rotate). In the fault-free case, the wires are unaffecte by each other an can carry ifferent signal values. However, this structure is very vulnerable to cell omission efects at or near to the crossing point. The cell omission efect at the cross point results in an unwante complementation on the inverter chain an the binary wire is ominate by the faulty value of the inverter chain (ominating briging fault). ell omission efects for the cells ajacent to the crossing point have similar effects, i.e. the value of the binary wire is ominate by the faulty value of the inverter chain Defects in the Majority Voter: The results of efects in a majority voter of the full-aer is consistent with the efect characterization results for a single majority voter: the horizontal input has more impact on the output than the vertical inputs. ell omission efect on the horizontal input cell oes not affect the functionality. However, a cell omission efect on any of vertical inputs causes the output to be ominate only by the horizontal input, i.e. the output is shorte to the horizontal input. The cell omission efect on the center cell of a majority voter with vertical input values an, an horizontal input changes the function to be the majority of,, an. This can be interprete as unwante complementation faults on both vertical inputs. 5. Test Sets overage an ault Moel Despite the fact that stuck-at fault oes not accurately moel a large portion of the efects foun in the moern MOS process, it seems to be the most effective fault moel in terms of the etection of the efective parts [12]. Therefore although from our simulation results we see that Q efects o not behave like stuck-at faults, it is still interesting to evaluate the effectiveness of ifferent stuck-at test sets for the simulate efects on a single majority voter. The main results of this evaluation are as follow: In all simulations, super exhaustive input patterns (i.e. all possible input transitions) are use. The results show that

6 there is no sequence epenent behavior at logic level; i.e. none of the manufacturing s introuces a state epenency at logic level. Except for a single case (i.e. the isplacement of all inputs an output cells) faults are etecte using a subset of some 100% stuck-at fault test sets. Note that not all of these 100% stuck-at test sets are equal. particular 100% 2-etect stuck-at test set (each fault is etecte by two vectors) can etect all manufacturing efects, except for one case, i.e. the simultaneous isplacement of the top an left inputs. Moreover, a particular 100% single stuck-at test set (001,010,011,101) can etect all simulate efects. The results for the full-aer circuit shows that none of the efects behave as stuck-at faults at logic-level. However, cell omission efects in wires implemente as inverter chains mainly result in unwante complementation faults in which at extra inverter is present in the faulty wire. ell omission efects at corner cells in the binary wires also behave this way. We also consiere stuck-at test sets for the full-aer (ig.9) an compute the corresponing efect coverage with respect to cell omission efects. Note that for a full-aer, any two vectors will result in 100% stuck-at coverage for pin faults, e.g.. However, this test set can etect only 17 out of 28 cell omission efects (Note that 12 of 40 simulate cell omission efects o not affect its functionality). y consiering all internal noes (n1 to n17 in ig.9), is a 100% single stuck-at test set. This test set can etect all 28 etectable efects. This shows that the specific Q implementation must be consiere for test generation to achieve a high efect coverage. 6. onclusion Quantum cellular automata (Q) are novel evices which are promising in the era of nano scale computing. In this paper, testing of Q base esigns has been investigate. etaile efect characterization for Q logic evices an some representative circuits has been presente. s shown in this paper, the coupling mechanisms an behavior of efects at logic-level (i.e. the faults) are not similar to those in a conventional MOS. or example, an unwante complementation fault at logic-level has been observe for a consierable number of cases of cell omission efects. Hence, appropriate fault moels for Q must be evelope an use for test generation. Some interesting an unique properties of Q implementation of logic networks have been investigate. s shown in this paper, a network of majority voters (an inverters) has unique testing properties: ny test set achieves 100% toggle fault coverage. n etects stuck-at- if an only if etects stuck-at-. The effectiveness of ifferent stuck-at test sets in etecting Q efects has been stuie. Our results show that to achieve high efect coverage, the specific Q implementations of each function must be consiere for test generation. References [1]I. mlani,.o. Orlov, G.L. Snier, an.s. Lent, Demonstration of a Six-ot Quantum ellular utomata System, pplie Physics Letters, vol 72, pp , [2]I. mlani,.o. Orlov, G. Toth,.S. Lent, G.H. ernstein, an G.L. Snier, Digital Logic Gate Using Quantum-Dot ellular utomata, Science 284, pp , [3].D.rmstrong, W.M.Humphreys,.ijany, The Design of ault Tolerant Quantum Dot ellular utomata ase Logic, 11th NS Symposium on VLSI Design, 2003 [4].D.rmstrong, W.M.Humphreys, The Development of Design Tools for ault Tolerant Quantum Dot ellular utomata ase Logic, 2n International Workshop on Quantum Dots for Quantum omputing an lassical Size Effect ircuits, [5]R. ompano, L. Molenkamp, D.J. Paul, Technology Roamap for Nanoelectroincs, European ommission IST programme, uture an Emerging Technologies. [6]. ijany an. N. Toomarian, New esign for quantum ots cellular automata to obtain fault tolerant logic gates, Journal of Nanoparticle Research, vol. 3, pp , [7]S.E. rost,.. Rorigues,.W. Janiszewski,R.T. Rausch, P.M. Kogge, Memory in Motion: Stuy of Storage Structures in Q, 1st Workshop on Non-Silicon omputation, [8]M. Governale, M. Macucci, G. Iannaccone,. Ungarelli, Moeling an Manufacturability ssessment of istable Quantum-Dot ells, Journal of pplie Physics vol 85, pp. 2962, [9]K. Hennessy,.S. Lent, locking of Molecular Quantum-Dot ellular utomata, Journal of Vaccum Science an Technology, vol 19(5), pp , [10]Personal communication with Professor Marya Lieberman, Department of hemistry an iochemistry, University of Notre Dame, IN, US. [11]M. Lieberman, S. hellamma,. Varughese, Y. Wang,.S. Lent, G.H. ernstein, G. Snier,. Peiris, Quantum-Dot ellular utomata at a Molecular Scale, nnals of the New York caemy of Sciences, vol 960, pp , [12]E.J. Mclusky an.w. Tseng, Stuck-ault Tests vs. ctual Defects, Proceeings of International Test onference, pp , [13]M.T. Niemier,.. Rorigues, P.M. Kogge, Potentially Implementable PG for Quantum Dot ellular utomata, 1st Workshop on Non-Silicon omputation, [14]M.T. Niemier, P.M. Kogge, Logic-in-Wire: Using Quantum Dots to Implement a Microprocessor, International onference on Electronics, ircuits, an Systems (IES 99),1999. [15].O. Orlov, I. mlani, G.H. ernstein,.s. Lent, G.L. Snier, Realization of a unctional ell for Quantum-Dot ellular utomata, Science, vol 277, pp , [16]QDesigner Home Page: [17].G. Smith, omputation Without urrent, Science, vol 284, pp. 274, [18]P.D. Tougaw an.s. Lent, Logical Devices Implemente Using Quantum ellular utomata, Journal of pplie Physics, vol 75(3), pp , [19]P.D. Tougaw an.s. Lent, Dynamic ehavior of Quantum ellular utomata, Journal of pplie Physics, vol 80(8), pp , [20]V.S. Dimitrov, G.. Jullien, K. Walus, Quantum-Dot ellular utomata arry-look-hea er an arrel Shifter, IEEE Emerging Telecommunications Technologies onference, [21]K. Walus, R.. uiman, an G.. Jullien, Effects of morphological variations of self-assemble nanostructures on quantum-ot cellular automata (Q) circuits, rontiers of Integration, n International Workshop on Integrating Nanotechnologies, [22]K. Walus,. Vetteth, G.. Jullien, V.S. Dimitrov, RM Design Using Quantum-Dot ellular utomata, NanoTechnology onference,vol 2, pp , 2003.