Worst Case Analysis of the Analog Circuits

Transcription

1 Proceedings of the 11th WSEAS Internationa Conference on CIRCUITS, Agios Nikoaos, Crete Isand, Greece, Juy 3-5, 7 9 Worst Case Anaysis of the Anaog Circuits ELENA NICULESCU*, DORINA-MIOARA PURCARU* and MARIUS- CRISTIAN NICULESCU** Eectronics and Instrumentation Department* and Mechatronics and Robotics Department** University of Craiova, Craiova, C.P. 585, A. I. Cuza Street, No. 13, ROMANIA enicuescu@eectronics.ucv.ro; dpurcaru@eectronics.ucv.ro Abstract: - An approach of the worst case anaysis of the anaog eectronic circuits based on the circuit description in parameter space is proposed. A DC, AC or transient worst-case anaysis can be performed ony testing the circuit for the vertices of a poytope in conjunction with a circuit simuator or computationa environment. In order to vaidate and show the effectiveness of this approach, DC worst-case anayses of anaog eectronic circuits with symmetrica and asymmetrica toerances in conjunction with a generapurpose circuit simuator are presented and discussed. Key-Words: - Toerance, Anaog eectronic circuit, Worst case anaysis. 1 Introduction The behaviour of a circuit is affected when certain parameters in specific components change. Circuit simuators ike SPICE can perform many anayses of the anaog and digita circuits that highight the change effects of the parameter vaues on the circuit performance. The worst case anaysis ets us expore the worst possibe effects of variations in component parameters on the performance of a circuit. Simuators ike SPICE perform the Worst Case Anaysis in conjunction with a DC or AC anaysis. The worst case anaysis resuts refer to the worst case vaues at the circuit outputs and performance specifications produced when a circuit component or device mode change its parameter vaue [1]-[3]. Such an anaysis is based on the sensitivity anaysis [4]. Some circuit simuators perform the sensitivity anaysis for the mode parameters of the active devices such as BTJs, FETs and integrated ampifiers meanwhie others do not. Automated faut detection for anaog circuits is subject to specific probems, such as the unknown deviation in toerances of nonfauty component vaues, the ocation of soft fauts and the presence of noise. The techniques for soft faut diagnosis in anaog eectronic circuits are based on the simuation before test, approach where a faut dictionary is a priori generated by coecting signatures of different faut conditions [5]-[8]. Worst case anaysis can be considered as a step in the stress anaysis or in the soft-faut diagnosis aowing us to find out the bound outputs or performance specifications of a circuit. A method for studying the worst case of the outputs and performance specifications of the anaog circuits that is not based on sensitivity anaysis can be derived utiizing the circuit description in parameter space. The paper is organized as foows. The anaog circuit description in the parameter space by a poytope is given in Section. In Section 3, the probem formuation of the worst-case anaysis based on aforementioned circuit description is presented. Then, in Section 4, we show how to impement and vaidate the proposed procedure using a circuit simuator where the sensitivity anaysis for the mode parameters of the active devices is not avaiabe. Two case studies are presented and discussed using a sma-signa ampifier with JFET as exampe, in order to iustrate the proposed procedure and to demonstrate its effectiveness. Section 5 concudes the paper. Circuit Description.1 Circuits with symmetrica toerances The concept of the circuit design approach and toerance seection, based on the foating and expanding poytope, has been proposed by Bander for an optima design of the nomina parameter vaues of the circuit and toerances [9]. This concept is appiabe to the circuits with symmetrica toerances such as those of the passive components [8]. Briefy, we resume this theorem ooking for the circuit description as foows. Let us consider Φ = [Φ 1 Φ... Φ k ] T a vector with k eements that

2 Proceedings of the 11th WSEAS Internationa Conference on CIRCUITS, Agios Nikoaos, Crete Isand, Greece, Juy 3-5, 7 93 correspond to the parameter circuit vaues. This vector has a correspondent point P(Φ 1 Φ... Φ k ) in the k-dimensiona space of parameters. The nomina Φ Φ.. Φ corresponds to point P = ( 1 k ) = [ Φ Φ.. Φ ] T Φ 1 k the vector of the parameter nomina vaues) and is associated with a non-negative toerance set ε = [ ε ε.. ε ] T 1 k. The toerance region R t, in the parameter space, is given as Rt = { P Φ i εi Φ i Φ i + εi,i I Φ } (1) where I Φ = { 1,,...k}. The toerance region R t is a k-dimensiona convex reguar poytope, centered at P, in the k- dimensiona space of parameters, and εi, i I Φ, is the ength of the i side of this poytope. The poytope has k vertices, which are the extreme points of R t. Then, the set of vertices can be defined as Rv = { P Φ i = Φ i + ε iµ i, µ i = ± 1,i I Φ }. () The number of points contained by R v is k : k 1 R v = { P P.. P }. These points are indexed by P i, i I v, I { k v = 1,,..., }. Looking for an optima design of circuit, an accepted region R a is defined and it is demonstrated that if R v Ra, then R t R a. According to this theorem, ony the poytope vertices must be tested to be sure that R. t R a 1. Circuits with asymmetrica toerances The operating characteristics of active devices and anaog integrated circuits are often unpredictabe because of their interna geometric dependence. We can create component modes that more cosey represent actua rea word devices by converting measurement or cataog data into mode parameters by means of various toos type parameter extractor. Usuay, the mode parameter range of a device ot is not centered at nomina vaues of the mode parameters of a given device sampe. The spread of the parameter vaues due to the manufacturing process and temperature effects are generating sources of asymmetrica toerances of the parameters. Aso, the deviations of the suppy votages can be asymmetrica with rapport to their nomina vaues. This probem of the anaog circuits with asymmetrica toerances becomes easy to sove if the asymmetrica toerance case can be reduced to that of the symmetrica toerance case. In order to sove this kind probem, the poytope with averagednomina point was defined and its equivaence with the poytope with symmetrica toerance was demonstrated [1]. We supposed that the nomina point is {Φ i } with i I Φ, the positive toerances ε pi and ε ni are op-sided, i.e. there is i I Φ for which ε pi ε pi. Some toerances can be symmetrica. Now, the toerance region is Rt = { P Φ i ε ni Φ i Φ i + ε pi,i I Φ }. (3) The toerance region R t is a k-dimensiona poytope with side i of ( ε + ε ) ength, i I Φ, and with k pi ni vertices. We repaced the nomina point Φ of the poytope R t with the averaged-nomina point Φ mi, where ε pi ε ni Φ mi = Φ i +, (4) and we denote the mean vaues of toerances, i.e. the symmetrica toerances, ε pi + ε ni ε mi = for a i I Φ. (5) Then, we demonstrated P Φ mi ε mi Φ i Φ mi + ε mi, R mt = = Rt. (6) for a i I Φ Repacing the poytope with asymmetrica toerances with its equivaent poytope with symmetrica toerances aows us to appy the Bander s theorem to an anaog circuit with asymmetrica toerances. 3 Worst Case Anaysis An anaog circuit can be described in the parameter space by a poytope, i.e. R t or R mt, of which vertices represent the extreme vaues of parameters. A DC, AC or transient anaysis performed for the vertices of the poytope R t wi produce corresponding vaue bands of the circuit outputs or performance specifications. The bounds of these vaue bands represent the worst case vaues of the circuit outputs or performance specifications. Consider a circuit of k parameters, P = [p 1, p,,p k ], where p i may be the resistance of a resistor, the capacitance of a capacitor, the β transconductance parameter or W/L ratio of a FET, the V th threshod votage, the λ channe ength i

3 Proceedings of the 11th WSEAS Internationa Conference on CIRCUITS, Agios Nikoaos, Crete Isand, Greece, Juy 3-5, 7 94 moduation coefficient etc. The circuit parameters have the nomina vaues P = [p 1, p,,p k ] and the toerances ε = [ε p1, ε n1, ε p, ε n, ε pk, ε nk ]. Some toerances can be symmetrica, i.e. ε pj = ε nj = ε j. Let be the poytope R mt with the averaged nomina point Pmi = pi + ( ε pi ε ni )/ (7) and the toerances ε = ε + ε /, with i = 1,, k. (8) mi ( pi ni ) The vertices of the set = { } R mt P m, where = 1,., k, are denoted as foows: p ε p + ε 1 pm ε m P = m, pm ε m P m =, ε mk ε mk p ε p + ε 3 pm + ε m P = m,.., pm + ε m P k m =. (9) ε mk + ε mk We suppose that the behaviour of the circuit is characterized by m circuit outputs y = [y 1, y,, y m ] and n performance specifications, S = [s 1, s,, s n ]. The circuit DC outputs Y = [Y 1, Y,, Y m ] are DC votages of nodes or DC currents through circuit branches that describe the DC operating point of circuit. A transient anaysis yieds the circuit outputs y(t) = [y 1 (t), y (t),, y m (t)]. A circuit output, for exampe the r-th output, or a performance specification, for exampe the t-th output, can be represented as a function of a parameters, i.e. y r = f(p 1, p,,p k ) and s t = f(p 1, p,,p k ). (1) Regardess of symmetrica or asymmetrica toerance case, the circuit outputs and performance specifications at nomina vaues of parameters wi be y = [y 1 (P ), y (P ),, y m (P )] and S = [s 1 (P ), s (P ),, s n (P )]. Each output and performance specification of a circuit is expressed by a vaue or a curve at nomina point in parameter space. Considering the variations in the parameter space and testing the circuit for the poytope vertices, there wi correspondingy be variation in the circuit outputs and specifications: y( P m ) = [y 1 ( P m ), y ( P m ),, y m ( P m )], (11) S( P m ) = [s 1 ( P m ), s ( P m ),, s n ( P m )]. (1) The reationships between a circuit output or performance specification and the parameters wi become a band instead of a singe curve. So, the circuit output y r is bounded by y rmin and y rmax, the performance specification s t is bounded by s tmin and s tmax : y rmin y r y rmax and s tmin s t s tmax. The bounds y rmin and y rmax, s tmin and s tmax are the worst vaues of circuit outputs and performance specifications for a worst-case anaysis. For a faut detection probem, the same bounds deimit the operation of the faut-free circuit. The upper bound of a circuit output can be ooked as stress anaysis resut. This procedure is not based on the sensitivity anaysis and it can be impemented in conjunction with a circuit simuator or computationa environment (Matab, Mathcad, Mathematica etc.) when an appropriate mode of the device/circuit is avaiabe. As it wi shown in the foowing, this procedure can be appied for the worst case anaysis of the anaog circuits with symmetrica and/or asymmetrica toerances. 4 Procedure Vaidation. Case Studies Using a genera-purpose circuit simuator, we wi show how to impement and vaidate the proposed procedure. The circuit simuator is used to perform the DC Operating Point Anaysis of the circuit for the poytope vertices. In order to verify the proposed procedure for the worst-case anaysis of an anaog circuit, its resuts wi be compared with those produced by the DC worst case anaysis aowed by the circuit simuator and an experimenta setup. For this purpose, we consider a sma-signa ampifier with a NJFET type BFW11. The circuit diagram of the test circuit is shown in Fig. 1. Fig. 1. Circuit diagram of the sma-signa ampifier with JFET type BFW11_Mod Firsty, we consider the circuit with symmetrica toerances of two resistors in circuit and perform the

4 Proceedings of the 11th WSEAS Internationa Conference on CIRCUITS, Agios Nikoaos, Crete Isand, Greece, Juy 3-5, 7 95 DC worst case anaysis based on the dedicated menu of simuator and our procedure. Secondy, the bounds of the parameter dispersion of the transistor at constant temperature are taken into account as asymmetrica toerances of circuit with rapport to a JFET sampe. Our NJFET sampe type BFW11 was chosen from a ot of ten transistors for which the characteristic curves were measured. We extracted the threshod votage, nomina saturation current and output conductance of each transistor from its characteristic curves. Then, converting the measurement data, we created a device mode. Such a mode has been created for three devices namey: NJFET sampe and two NJFETs of which characteristic curves represent the ot dispersion. For the NJFET sampe mode, we find out the foowing parameters: V T (V) = - (threshod votage), β (ma/v ) = (transconductance parameter) and λ (V 1 ) =.46 (channe ength moduation coefficient). The rest of mode parameters hods the vaues set for the NJFET type BFW11 contained by the Master Database of the circuit simuator. The new device with its mode was saved in User Database as a component named BFW11_Mod. The bias circuit was designed to set the DC operating point into the active forward region with the foowing nomina coordinates: I DQ 1.5 ma, V GSQ -1 V and V DSQ 6 V. Consequenty, we obtain the foowing vaues of resistances: R 1 = MΩ, R = 6 Ω and R 3 = 3.9 kω. The toerance of a the passive components have a toerance of ±5%. We consider a constant temperature (7 o C), for the sake of brevity and a better match of the measurement and simuation conditions. 4.1 Worst case anaysis of an anaog circuit with symmetrica toerances At this point, the effects of the mode parameter toerances are not considered. Looking for DC worst case anaysis of the given circuit, we consider ony the effects of variations of two resistive parameters on the votages of drain and source nodes (Y1 = V9 and Y = V1) and the suppy branch current (Y3 = vv1#branch = I D ) are taken into account. So, the circuit parameters are as foows: p 1 = R, p 1 = 6 Ω, ε 1 = 31 Ω; p = R 3, p = 3.9 kω, ε = 195 Ω. The verification process of proposed procedure has four steps as foows: 1. The circuit from the Fig. 1 is simuated for the DC worst case anaysis using the aforementioned toerances, i.e. ε 1 and ε. The anaysis resuts are shown in Tabe 1.. In order to find out the bounds of the specified circuit outputs, the R and R 3 parameter vaues are modified according to each vertex of poytope. Then, the new circuit is simuated for perfoming the DC Operating Point Anaysis. The poytope with symmetrica toerances are four vertices: P = ; P = ; P = ; P =. 495 The anaysis resuts are aso given in Tabe 1. Tabe 1. The resuts of the worst case anaysis performed with the dedicated menu of a circuit simuator, proposed technique and experimenta setup Approach DC circuit outputs Y 1 (V) Y (V) Y 3 (ma) DC WCA menu Poytope P vertices P P Experimenta P P P P P The three DC outputs of the circuit constructed with the NJFET sampe for the four pairs of vaues of resistances R and R 3 are measured. The experimenta resuts are given in Tabe 1 too. 4. Comparison between the resuts of the worst case anaysis performed with the dedicated menu of a circuit simuator, proposed technique based on the testing of the poytope vertices, and experimenta setup show the foowing: a. The worst case anaysis performed by means of the dedicated menu of simuator provides an ony vaue for each DC output of circuit: Y 1w.c.a (V) = , Y w.c.a. (V) =.9759, Y 3w.c.a. (ma) = The suppementary index marks the worst case vaue (w.c.a.) of DC outputs. b. The proposed technique provides a vaue band for each DC output of circuit. The minimum and maximum vaues of each band (boded in Tabe 1) represent the resuts of the worst case anaysis based on testing the circuit for the poytope vertices.

5 Proceedings of the 11th WSEAS Internationa Conference on CIRCUITS, Agios Nikoaos, Crete Isand, Greece, Juy 3-5, 7 96 c. The worst case vaues of the DC circuit outputs suppied by dedicated menu of the simuator are neary recovered for the P vertex of poytope. d. The two vaue bands of the DC outputs and their bounds from the experimenta resuts are neary the same as that obtained utiizing the proposed procedure. 4. Worst case anaysis of an anaog circuit with asymmetrica toerances In this section, we wi iustrate how to appy the proposed procedure on a circuit with some asymmetrica toerances by means of a circuit simuator. The asymmetrica toerances describe the NJFET ot dispersion with rapport to NJFET sampe. In our circuit simuator version, the sensitivity anaysis and consequenty the worst case anaysis with rapport with the mode parameters of active devices is not possibe. For this purpose, we construct the component mode for the two transistors of which characteristic curves represent the ot dispersion. Let be BFW11_Mod_a the device for which we extracted from measured curves the foowing parameters: V t (V) = , I DSS (ma) = and λ(v -1 ) =.591. The other transistor named BFW11_Mod_b is characterized by the parameter vaues: V t (V) = -.385, I DSS (ma) = and λ(v -1 ) =.317. The user modes characterizing the ot dispersion are constructed and saved with the same names as the devices. The main parameters of the two modes are summarized in Tabe. As for previous case, the rest of the mode parameters have the same vaues as they of BFW11 mode in Master Database of simuator. Tabe. Main parameters of the BFW11_Mod_a and BFW11_Mod_b modes BFW11_Mod_a BFW11_Mod_b V T (V) β (ma/v ) λ (V -1 ) Now, we consider the effects of five circuit parameters on the same DC outputs as in previous case. Among these, we have two component parameters with symmetrica toerances, i.e. R and R 3, and three device parameters with asymmetrica toerances, i.e. V th, β and λ. The nomina vaue and toerance of these five parameters are as foows: p 1 = R, p 1 (Ω) = 6, ε 1 (Ω) = 31; p = R 3, p (kω) = 3.9, ε (Ω) = 195; p 3 = V T, p 3 (V) = -, ε p3 (V) =.9314, ε n3 (V) =.385; p 4 = β, p 4 (ma/v ) = , ε p4 (ma/v ) =.48386, ε n4 (ma/v ) =.1564; p 5 = λ, p 5 (V -1 ) =.4645, ε p5 (V -1 ) =.1311, ε n5 (V -1 ) =.149. The nomina vaues p 3, p 4 and p 5 correspond to the mode parameter vaues of BFW11_mod device. Their asymmetrica toerances associated to these nomina vaues, i.e. ε p3, ε n3, ε p4, ε n4, ε p5, ε n5, represent the differences between the vaues of the homonym parameters of BFW11_Mod mode and BFW11_Mod_a mode, respectivey BFW11_Mod_b mode. According to the proposed procedure, the poytope with averaged nomina point has 5 vertices corresponding to the five considered parameters of circuit. The hypothesis of the constant temperature introduces some constraints concerning the combination of toerances assigned to the mode parameters of JFET. This means that the mean vaues of toerances associated to the two mode parameters wi be simutaneousy added or subtracted from the averaged nomina vaues for a three parameters. Consequenty, ony 3 vertices of poytope rest to be tested. Next, we have to cacuate the averaged nomina vaues and mean toerances of the parameters according to (7) and (8). These agebraic cacuations yied the foowing data: p = p 1 (Ω) = 6, ε = ε 1 (Ω) = 31; p m = p (kω) = 3.9, ε m = ε (Ω) = 195; p m3 (V) = , ε m3 (V) = m ;.313; p m5 (V -1 ) =.4545, ε m5 (V -1 ) =.137. Now, appying (9) we can write the vertices of the poytope with averaged nomina point as foows: p (ma/v ) = , ε m4 (ma/v ) = P m = ; P m = ; P m = ; P m =. 385 ; P m 6 P m = =

6 Proceedings of the 11th WSEAS Internationa Conference on CIRCUITS, Agios Nikoaos, Crete Isand, Greece, Juy 3-5, P m =. 385 ; P m = To find out the DC worst case outputs of the circuit, we have to run eight times the DC Operating Point Anaysis from the circuit simuator for the eight specified vertices. Each poytope vertex means a particuar circuit concerning the active device, i.e. either BFW11_Mod_a or BFW11_Mod_b, and extreme vaues of the two resistances. The simuation resuts are shown in Tabe 3. Tabe 3. The resuts of the DC worst case anaysis based on the poytope vertex test. Poytope DC circuit outputs vertices Y 1 (V) Y (V) Y 3 (ma) P P P P P P P P The minimum and maximum vaues of each band (boded in Tabe 3) represent the resuts of the worst case anaysis based on the poytope vertex test. The parameter vaue dispersion of active device highighted by the differences of the band bounds of each DC outputs of the circuits in Tabe 1 and 3 has a critica impact on meeting the design specifications. 5 Concusion In this paper, a procedure to perform the worst case anaysis of an anaog circuit with symmetrica and/or asymmetrica toerance is presented. The proposed procedure is different to that used in circuit simuator, because it is not based on the sensitivity anaysis. The worst case vaues of the circuit outputs or performance specifications are obtained by performing DC or AC or transient anaysis for the extreme vaues of parameters given by the vertices of a poytope. The number of vertices increases with the number of circuit parameters taken into account. When the worst case anaysis is performed in conjunction with a circuit simuator for a arge number of parameters such a procedure becomes heavy. Each poytope vertex requiers the modification and resimuation of the circuit. This drawnback disappears when the procedure is appied in conjunction with a computationa environment. The resuts obtained utiizing the proposed procedure are neary the same as the experimenta resuts. This means that the proposed procedure can be an aternative means to perform the worst case anaysis of an anaog circuit. References: [1] B. Vinnakota, Anaog and Mixed-Signa Test. Prentice Ha, [] R. R. Boyd, Toerance Anaysis of Eectronic Circuit Using Mathcad, CRC Press LLC,. [3] W. K. A-Assadi and P. Chandrasekhar, Issues in Testing Anaog Devices, Proc. of the 1 th NASA Symposium on VLSI Design, 5 [4] M. W. Tian and C.-J.R. Shi, Worst-case anaysis of inear anaog circuits using sensitivity bands, IEEE Trans. on Circuits and Systems: Fundamenta Theory and Appications, vo. 47, no. 8,, pp [5] M. Worsman and M.W.T. Wong, Non-inear anaog circuit faut diagnosis with arge change sensitivity. Internationa Journa of Circuit Theory and Appications,No. 8,, pp [6] C. Marcantonio and A. Fort,Soft Faut Detection and Isoation in Anaog Circuits: Some Resuts and a Comparison Between a Fuzzy Approach and Radia Basis Function Networks, IEEE Trans. on Instrumentation and Measurement, Vo. 51, No.,, pp [7] S-J. Chang, C-L. Lee and J. E. Chen, Structurebased specification-constrained Test frequency generation for Linear Anaog Circuits, Journa of Information Science and Engineering, Vo. 19, 3, pp [8] V. C. Prasad and N. C. S. Babu, Seection of test nodes for anaog faut diagnosis in dictionary approach. IEEE Trans. on Instrumentation and Measurement, Vo. 49,, pp [9] J. W. Bander, Worst Case Network Toerance Optimization", IEEE Trans. on Microwave Theory, Vo. MTT-3, Aug. 1975, pp [1] E. Nicuescu and I. Vadimirescu, The Poytope with averaged nomina point, Annas of the University of Craiova, Eectrica Engineering Series, no. 1, 1997, pp