8 Digifl'.11 Cth:uits and devices

Transcription

1 8 Digif'. Cth:uits and devices 8. Introduction In anaog eectronics, votage is a continuous variabe. This is usefu because most physica quantities we encounter are continuous: sound eves, ight intensity, temperature, pressure, etc. Digita eectronics, in contrast, is characterized by ony two distinguishabe votages. These two states are caed by various names: on/off, true/fase, high/ow, and /. In practice, these two states are defined by the circuit votage being above or beow a certain vaue. Fbr exampe, in TTL ogic circuits, a high state corresponds to a votage above 2. V, whie a ow state is defined as a votage beow.8 V. 2 The virtue of this system is iustrated in Fig. 8.. We pot the votage eve versus time for some eectronic signa. If this was part of an anaog circuit, we woud say that the votage was averaging about 3 V, but that it had, roughy, a 2% noise eve, rather arge for most appications and thus unacceptabe. For a TTL digita circuit, however, this signa is aways above 2. V and is thus aways in the high state. There is no uncertainty about the digita state of this votage, SC' the digita sig'a has zero noise. This is the primary advantage of digita eectronic8: it is reativey immune to the noise that is ubiquitous in eech onic circuits. Of comse, if the fuctuations in Fig. 8. became so arge that the votage dipped beow 2. V, then even a digita circuit woud have probems. 8.2 inary numbers though digita circuits have exceent noise immunity, they aso are imited to producing ony two eves. This does not appear to be very hepfu in representing the continuous signas we so frequenty encounter. The soution starts with the This hods for most macroscopic quantities. On the atomic eve, many physica quantities are quantized. 2 If the votage is between these threshods, we say the state is undetermined, which means the circuit behavior cannot be insured.

2 ' 8.2 inary numbers Tabe 8. The first tweve counting numbers in binary ase ase ase ase 2 ) t Figure 8. noisy anaog signa is noise-free in digita. reaization that we can represent a signa eve by a number that ony uses two digits. For these binary numbers, the two digits used are and L inary numbers are aso ca, bas~ 2 numbers, and can be understood by abstractin~ the rues we a know for the numbers we cominony use (base numbers): W\e'n we write down a base number, each digit can have possibe vaues, to 9, and each digit corresponds to raised to a power. For exampe, when I write 24 o, this is equa to.. 24 = x 3 + x x +4 x (8.) where we use the subscript on 24 to make expicit the base of the number. naogousy, for binary numbers, each digit can have ony 2 possibe vaues, or, and each digit of the number corresponds to 2 raised to a power. Thus 2 = x2 4 + x x x 2 + x 2 = 22. (8.2) The first tweve base numbers and their binary equivaents are given in Tabe 8.. In a simiar manner, the rues for base addition and subtraction can be mapped over to binary arithmetic. Some exampes are shown in Tabe 8.2. In base, when we add the rightmost coumn, 9 pus 5 equas 4. Since this resut cannot be expressed in a singe digit with the ten avaiabe digits ( to 9), we write down the 4 and carry the to the next coumn. Simiary, when we add the and of the rightmost coumn of the binary number, we get 2. Since this cannot be expressed

3 Digita circuits and devices Tabe 8.2 dding and subtracting in binary ddition Subtraction ase ase 2 ase ase in a singe binary digit, we write down the and carry the to the next coumn. We repeat the process as we work through the coumns from right to eft. In the base subtraction, we try to take 9 from 4, but need to borrow from the next coumn to the eft. This gives us 4 which aows the subtraction to proceed, but we must remember to decrease the number in the coumn by one. In ike manner, for the binary number, we try to take one from zero in the first coumn. To progress, we need to borrow from the next coumn (the 2 coumn), carefuy decreasing that coumn's digit by one. We then continue as with the base number unti we reach the eftmost coumn. Note from Eq. (8.2) and Tabes 8. and 8.2 that binary numbers tend to be ong (i.e., have many digits) compared to base numbers. s we wi see, this has a direct impact on the compexity of digita circuits. 8.3 Representing binary numbers in a circuit In the ast section we saw that numbers can be expressed in base 2 just as they can in the more famiiar base. ase 2 is particuary suitabe for expressing a number digitay since digita eectronics has ony two eves, high and ow, and these can be taken to represent the two digits ( and ) in a binary number. ut a binary number typicay consists of severa digits. 3 How can we express a of these digits eectronicay? There are two basic methods, known as parae and seria representation. In parae expression of a binary number, each digit or bit of the number is represented simutaneousy by a votage in the circuit. This is represented schematicay in Fig Each output ine has a high or ow votage reative to ground. These ines are assigned to represent a particuar bit of the number. In this exampe, 3 binary digit is often referred to as a bit.

4 8.3 Representing binary numbers in a circuit ( 73 puts: 23 ~ Digita Circuit ~ - - Figure 8.2 Parae representation of a four-bit number. v bit: ]~~~D- t Figure 8.3 Seria representation of a four-bit number. the bottom ine represents the 2 bit, the next ine up represents the 2 bit, and so on. ecause we have four independent ines, the entire four-bit number can be expressed at a point in time, so parae communication of information is very fast. The price we pay for this speed is the increased number of ines in our circuit. The more precision we want in our number, the more significant figures we need, and the more ines are required. n aternative way of expressing a binary number is by a seria representation. In this method, the various bits are communicated by sending a time sequence of high/ow votage eves on a singe ine. n exampe of this is shown in Fig The pot shows the votage eve on a seria ine. The votage switches between high and ow eves, with each eve asting for a certain time interva. The first interva corresponds to the 2 bit of our number, the next interva represents the 2 bit, and so on. We are thus abe to communicate the binary number on a singe ine, rather than the mutipe ines required for parae communications, but the communication is no onger instantaneous; we must wait for severa intervas before we receive a the bits of our transmitted number. In order for seria transmission of information to work, both the sender and receiver need to agree about severa things. Some of these are: () how many bits of data are going to be sent, (2) what digita eve (high or ow) corresponds to the bit, (3) what is the time interva between bits, and ( 4) how wi the start of a number be recognized?

5 Digita circuits and devices 8.4 ogic gates The basic circuit eement for manipuating digita signas is the ogic gate. There are severa types of ogic gate, and each performs a particuar ogica operation on the input signas. The ogica operation of the gate is defined by its truth tabe which gives the output state for a possibe combinations of the inputs. The first ogic gate we wi consider is the ND gate. The output of an ND gate is high ony when a of the inputs are high. ecause this definition is cear for any number of inputs, this type of gate can, in principe, have as many inputs as you ike. In Fig. 8.4 we show a two-input ND gate aong with its truth tabe. s we wi see beow, there is a specia agebra, caed ooean agebra, for ogic operations. The symboic representation of the ND operation for two inputs and is, pronounced " and " or " NDed with." Note that it is not " times." The output of an OR gate is high when any input is high. gain, this operation is defined for any number of inputs. two-input OR gate is shown in Fig. 8.5 aong with its truth tabe and ogica expression +. +is pronounced " or " or " ORed with." It is not " pus." third gate is caed the excusive-or gate, or simpy the XOR gate. The ogic here is that the output wi be high when either input is high, but not when both inputs are high. Note that this definition assumes there are ony two inputs. This device is shown in Fig The circuit symbo is ike the OR gate symbo; the curved ine across the inputs denotes the excusion described in the definition. The circe around the + in the ooean expression E distinguishes this expression from the OR function. This is pronounced "x or." ~=[)-out= Figure 8.4 Circuit symbo, agebraic expression, and truth tabe for the ND gate. ~=[)-out=+ Figure 8.5 Circuit symbo, agebraic expression, and truth tabe for the OR gate.

6 T i I j! I j I 4 i I j i I ~~D-=E -t>-- = ~ L /' = ~ - ~=+ 8.4 Logic gates Figure 8.6 Circuit symbo, agebraic expression, and truth tabe for the XOR gate. Figure 8.7 Circuit symbo, agebraic expression, and truth tabe for the buffer gate. Figure 8.8 Circuit symbo, agebraic expression, and truth tabe for the NNO gate. Figure 8.9 Circuit symbo, agebraic expression, and truth tabe for the NOR gate. The buffer gate, shown in Fig. 8.7, seems to be superfuous. It has ony one input, and the output is the same as the input. What good is this? This gate is used to regenerate ogic signas. ogica high signa may start out at 5 V, say, but after being transmitted on conductors with non-zero resistance or after driving severa other ogic gates, the votage eve may fa and become periousy cose to the defining threshod for a high ogic eve. The buffer is then used to boost the eve up to a heathier eve, thus maintaining the desirabe noise immunity and extending the range for the transmission of the signa. Each of the gates discussed so far has a corresponding negated version: the ND, OR, XOR, and buffer gates have the NND, NOR, XNOR, and inverter gates as compements. The truth tabes for these negated gates are the same as for the origina gates except the output states are reversed. Thus the output states,,, for the ND gate become,,,. The circuit symbo is the same except for a sma circe on the output which indicates the inversion of the eve. Finay, the ooean symbo is changed by pacing a bar over the origina expression: thus becomes, and so on. These negated gates are shown in Figs. 8.8, 8.9, 8., and 8..

7 ' Digita circuits and devices Figure 8. O Circuit symbo, agebraic expression, and truth tabe for the XNOR gate. ---{:>o- = Figure 8. Circuit symbo, agebraic expression, and truth tabe for the inverter gate. s = (L + R) S Figure 8.2 Soution of the car aarm probem. 8.5 Impementing ogica functions The impementation of simpe ogica functions can usuay be determined after a itte thought. For exampe, suppose you are designing a safety system for a two-door car. You want to sound an aarm (activated by a high eve) when either door is ajar (this condition being indicated by a high ogic eve), but ony if the driver is seated (again, indicated by a high eve). Such a ogic function is produced by the circuit in Fig The state of the eft and right doors is represented by inputs L and R, whie input S tes the circuit if the driver is seated. Thus if L or R is high (or both), and S is high, the output is high and the aarm sounds, as required. With more compicated ogic probems, the soution is ess obvious. For such probems the Karnaugh map provides a method of soution. This method works for ogic circuits having either three or four inputs. The first step in the method is to make a truth tabe for the probem. This foows from anayzing the requirements of our probem: under what conditions do we require a high output? s an exampe, suppose our anaysis gives us the truth tabe shown in Fig For this exampe, we have three inputs,,, and C giving the output eves indicated. The next step is to construct a Kamaugh map from the data in our truth tabe. This is iustrated in Fig The input states are isted aong the top and eft side of the map. For this exampe, with three inputs, we ist the possibe combinations aong the top and the two C states aong the eft side. 4 When we 4 For four inputs, the possibe CD combinations woud be isted aong the eft side as in Fig. 8.6.

8 8.5 Impementing ogica functions C Figure 8.3 Truth tabe for the Karnaugh map exampe. c o~ C C Figure 8.4 The Karnaugh map corresponding to Fig ist the combinations, we must foow a convention: ony one digit at a time is changed as we write down the various combinations. In this exampe, we start (arbitrariy) with, and then change the second digit to get. To get another combination not yet isted, we change the first digit and get, and finay change the second digit obtaining. We then fi in the map with the data from the truth tabe. The fina steps are to identify groups of ones and then read the required ogic from the map. The rue is to ook for horizonta and/or vertica groups of 2, 4, 8, or 6. Diagona groups are not aowed. In our exampe, there are two groups each containing two members. These are circed in Fig Now we identify the ogic describing each group. To be a member of the group on the eft, both and C must be high, so the ogic is C. To be in the group on the right, both and C must be high, so the ogic is C. Since a high output is obtained if we are a member of either group, the fu ogic describing our truth tabe is ( C) + ( C). The impementation of this is shown in Fig. 8.5.

9 Digita circuits and devices c = ( C) + ( C) Figure 8. 5 The ogic circuit impementation of Fig Figure 8.6 Karnaugh map exampe showing how edges connect. ->o-\ -----= v C ~ = C Figure 8.7 Circuit for the negated version of Fig When ooking for groups in the Kamaugh map, the edges of the map connect. This is iustrated in the map shown in Fig ecause we can connect the right and eft edges of the map, the ones in this map form a group of four, as indicated. To be a member of this group, C must be high and must be ow. Thus the ogic for this group is C. This is much simper ogic than we woud obtain if we instead identified two groups of two in our map. nother simpification resuts in cases where the map has many ones and few zeros. In such cases, we can identify groups of zeros, find the ogic for being a member of these groups, and appy an inversion to the resut. For exampe, if the ones and zeros of the centra portion of the map in Fig. 8.6 were reversed, we woud find one group of four zeros. s we have seen, the ogic for this group is C, but now we invert the resut, obtaining C. This fina inversion coud be done by using a NND gate, as shown in Fig ooean agebra n agebra is a statement of rues for manipuating members of a set. You have, no doubt, earned in the past rues for doing mathematica manipuations with

10 8.6 ooean agebra Tabe 8.3 The ooean agebra t Defining OR Defining ND Defining NOT Commutation ssociation Distribution bsorption DeMorgan's. DeMorgan's 2 O+ = += += += O = = = = = +=+ = + ( + C) = ( + ) + C ( C) = ( ). C ( + C) = ( ) + ( C) + ( C) = ( + ) ( + C) + ( ) = ( +) = += =+ integers, rea numbers, and compex numbers. There is aso a specia agebra for ogica operations. It is caed ooean agebra. The rues for ooean agebra are shown in Tabe 8.3. They consist of definitions for the ND, OR, and NOT (or inversion) operations, and severa theorems. In the tabe,,, and C are ogica variabes that can have vaues of or. Once the definitions are accepted, the theorems can be proved by brute force by pugging in a the possibe cases; since the variabes have ony two vaues, this is not too trying, ooean agebra can be used to find aternative ways of expressing a ogica function. Consider the XOR function defined in Fig To get a high output, this function requires either high whie is ow, or high whie is ow. In agebraic terms, E = ( ) + ( ). (8.3) This equation shows us a way of producing the excusive-or function (other than buying an XOR gate). The resuting circuit is shown in Fig Note that in this figure (as in other figures in this chapter) we use the convention that crossing ines are not connected uness a dot is shown at the intersection point. This aows for more compact circuit drawings.

11 Digita circuits and devices Figure 8.8 n aternative way of making an XOR gate ! Figure 8.9 nother way of making an XOR gate. Now we empoy some agebraic manipuations to find another (and simper) way to express the XOR function. In the first ine of Eq. (8.4), we use the fact that = and + = (for any ) to rewrite Eq. (8.3). The next ine uses the Distribution Theorem to group terms together. The third ine uses the second DeMorgan Theorem and the ast ine again uses the Distribution Theorem. The resuting ogic is impemented in Fig Note that this way of making an XOR gate is simper than that in Fig. 8.8 because it uses fewer gates: ffi = (. ) + ( ) + ( ) + ( ) = (+ ) + ( + ) = ( ) + ( ) = ( + ) ( ). (8.4) We have seen that we can construct an XOR gate from combinations of other gates. There is an interesting theorem that states that any ogic function can be constructed from NOR gates aone, or from NND gates aone. For exampe, suppose we want to make an ND gate from NOR gates. Using ooean agebra, we can find the way: = ( + ) = ( + ) + ( + ). (8.5) In the first equaity, we have used the second DeMorgan Theorem and in the second equaity we have used the fact that anything OR'd with remains the same. The point is that the fina expression is a in terms of NOR functions. The resuting circuit is shown in Fig. 8.2.

12 8. 7 Making ogic gates Figure 8.2 Making an ND gate from NO Rs. It may seem that this is a siy thing to do. If you need an ND, why not just buy an ND instead of making it from NO Rs? There are two reasons. The first concerns the way ogic gates are packaged. typica integrated circuit (IC) chip wi have four or six gates on a singe chip, but a the gates are the same type (e.g., a NORs). Now if you are buiding a ogic circuit that needs one NOR gate and one ND gate, you can buy two integrated circuits (one with NOR gates on it and one with ND gates on it) or you can use a singe NOR gate IC containing at east four gates. In the atter case, one of the gates is used for the NOR function and the other three are used, as in Fig. 8.2, to produce the ND function. Thus you have saved money and circuit board space by using the NOR equivaent for the ND. The second reason is, again, a practica one. If one is working on a ogic circuit and runs out of one type of gate, is it usefu to know that you can make do with a combination of NOR or NND gates. ternativey, if you are stocking an eectronic workshop, you coud just buy NOR or NND gates instead of stocking a the different ogic gates; you coud aways construct a needed function from the one type of gate you had on hand Making ogic gates though we have discussed how ogic gates function, we have not yet indicated how to make them. There are, in fact, many ways to make ogic gates. simpe, ow-tech way is to use an eectromagnetic switch or reay, as shown in Fig The reay has a soenoid with a movabe iron core that is mechanicay attached to a switch. When a votage is appied to the contro input, the iron core is pued into the soenoid and coses the switch. Without a contro votage, a spring (not shown) returns the switch to an open position. Figures 8.22 and 8.23 show the use of reays to form an ND gate and an OR gate. The gate inputs and are connected to the reay contros and cose the reevant switch when they are high. For the ND gate, two reays are connected in series, and for the OR gate, two reays are connected in parae. When the switches

13 Digita circuits and devices In--+-'- :.+. contro~-,: ~--~ Figure 8.2 bas ic reay. + 5 v --~ '-- ~~I ~ ---J--i,_ ~ ----o=i Figure 8.22 ND gate made from reays. +5v r--~- =+ Figure 8.23 OR gate made from reays. are open, the output is hed at ground potentia by the resistor R. When the ogic is satisfied, the output is connected to the +5 V suppy votage and is thus high. Semiconductor ogic gates come in various types or famiies. One common type is the transistor-transistor ogic (or TTL) famiy. Here bipoar transistors are used to create the ogic gates. For exampe, the TTL NOR gate is shown in Fig If either nor is high, its transistor is driven into saturation, making the coectoremitter votage sma and the gate output ow. If neither nor is high, both transistors are off, so there is no votage drop across R and the output is high (+5V). nother important ogic famiy is the compementary meta oxide semiconductor (or CMOS) famiy. These circuits empoy fied-effect transistors. For exampe, a CMOS NOT gate is shown in Fig When a high votage is appied to the input, the transistor turns on and the votage across it becomes sma, thus giving a ow output. When a ow votage is appied, the transistor does not conduct, so the output remains at +5 V (i.e., high).

14 8.8 dders Tabe 8.4 Characteristics of some ogic famiies Famiy TTL CMOS ECL Pros Common, fast, cheap Low power consumption, suitabe for arge scae integration Fastest Cons High power consumption Reativey sow High power consumption, ow noise immunity +sv ut = + +sv Figure 8.24 TTL NOR gate made with bipoar transistors. Figure 8.25 CMOS NOT gate made with a fied-effect transistor. There are aso specia purpose ogic famiies, ike the fast-switching ECL (emitter couped ogic) famiy, but we wi eave these for more advanced study. Some of the pros and cons of the famiies we have mentioned are shown in Tabe dders In addition to performing ogic functions, gates can aso be used to add binary numbers. To see this, consider the data in Tabe 8.5. We imagine that and are two binary numbers consisting of one bit, so each can ony have the vaue or.