Interconnect effects on performance of Field Programmable Analog Array

Transcription

1 nterconnect effects on performance of Fied Programmabe Anaog Array D. Anderson,. Bir, O. A. Pausinsi 3, M. Spitz, K. Reiss Motoroa, SPS, Phoenix, Arizona, USA, University of Karsruhe, Karsruhe, Germany, 3 University of Arizona, Tucson, Arizona, USA, Technica University of Poznan, Poand Abstract Fied programmabe anaog array (FPAA) based on switched capacitor circuits operating with operationa ampifiers and numerous switches incorporates many casses (subsystems) of interconnections. mportant components of the array are programmabe capacitor bans, where interconnections and switches are used to mae proper parae connections of unit capacitors to obtain an appication determined capacitance vaue. The interconnections in capacitor bans form a sub-system which pays an important roe in FPAA performance because of its parasitic capacitance. This paper describes a method for design of interconnection ayout in ban of unit capacitors to minimize the infuence of interconnect parasitic capacitances. A measure of errors due to the ayout imperfections is introduced, and a technique for experimenta evauation of the imperfection measure is aso presented. The anaytica deveopment and resuts were positivey verified by aboratory measurements. Representative experimenta data are incuded in the paper. ntroduction n this paper we study an eectrica behavior of a cass of interconnections in fied programmabe anaog array (FPAA), which is a nove mixed-signa integrated circuit technoogy deveoped by Motoroa. Motoroa chip MPA00 is subdivided into 0 anaog ces, 3 anaog input-output buffers (unity gain foowers), and digita section for storing contro programs and performing numerica operations. Each anaog ce consists of 5 programmabe capacitor bans, operationa ampifier, and digitay controed anaog static and dynamic switches. Static switches estabish circuit structure (configuration of capacitors and operationa ampifiers) and are set at the programming phase. Dynamic switches are controed by the switching coc and are used during the chip operation to define capacitor functions. The FPAA chip may be programmed and reprogrammed to perform user defined function using a P or a program stored in a digita chip. The FPAA chip contains many (6,850) anaog switches, which have to be set in programming (function downoading) phase in order to determine a circuit configuration and its function. Setting such a number of switches is a very compex operation and to faciitate this operation there is a speciaized software pacage, Easy Anaog TM suppied by Motoroa. More detaied description of Motoroa s impementation of FPAA is avaiabe in [Anderson et. a. 997, Web 998 ]. The FPAA finds many appications in anaog signa fitering and conditioning, synthesis of feedbac system components [Dorn 998], signa generation and many other engineering appications [Pausinsi et a. 997]. Probem formuation - interconnect anaysis The invoved interconnect system in FPAA can be divided into subsystems performing the foowing functions: distribution of anaog signas, distribution of digita signas, power and ground distribution, and distribution of anaog reference (signa ground). Typicay digita signas exhibit intervas of strong transitions separated by intervas of reative quiescence, whie anaog signas are usuay consideraby smoother. However, the FPAA technoogy considered here utiizes switched capacitor circuits, where anaog signas undergo transitions during the capacitor switching. The perturbations due to such transients can be negected in synchronized switched capacitor circuits providing that there is sufficient time aocated for setting within the switching interva. Perturbations due to transients on digita circuits (so

2 caed switching noise) are successfuy minimized by using separate digita and anaog power and ground rais. There are two probems associated with performance of interconnections that need to be investigated: a) cross-ta between the anaog interconnects and b) effects of interconnects in capacitor bans. The first probem is strongy dependent on configuration of FPAA, which is dictated by an appication and can be mitigated by proper chip programming. Study of this probem is carried on and wi be a subject of future report. n this presentation we sha concentrate on the effects of capacitor interconnects on performance of FPAA. We sha assume that the minimum switching interva was determined considering setting time, such that the transient effects can be negected and thus we wi consider ony static (capacitive) effects of interconnections on FPAA performance. For the MPA00 technoogy the minimum switching interva was determined to be [ µs ]. apacitor bans interconnection parasitics apacitor vaues in FPAA are reaized through parae interconnections of unit capacitors, u, contained in bans arranged into binary sub-arrays as shown in Fig., such that a capacitor vaue is a mutipe of unit capacitors, u, where,, is the number of unit capacitors connected together. n the MPA00 version of FPAA the vaue of can be seected as foows: b,,..., 55g. [] [] [] [8] [6] [3] [8] Discussion of capacitor errors Fig. Schematic arrangement of capacitor ban in FPAA. n the foowing we denote an impemented (rea) capacitor, i, the idea capacitor, i, and write the difference in the form i i i =. () apacitors created by connection of unit capacitors have errors caused by manufacturing imperfections resuting in errors of unit capacitor vaues (ε i ; i =,, 3,..., 55 ), by parasitic capacitances of interna sub-array connections ( ξ,,,,,..., = 8 j ), and by parasitic capacitances, of externa connections ( χ n, n = 3, 5, 6, 7,... n m ) between the sub-arrays needed to form a desired circuit capacitance. t is convenient to introduce a specia notation for the errors in capacitances of sub-arrays (mutipes of unit

3 capacitance, determined by the powers of ) showing expicity the contribution of unit capacitor errors,, being a summation of unit capacitor errors (ε i ; i =,, 3,..., 55 ) and the contribution of capacitance of the sub-array interna interconnections, ξ. To iustrate this notation it is appied to denote the errors in the capacitors of the -nd sub-array: = + ; = + ξ ; = ε q + ε 3 q () q and ε 3q are errors of the second and third unit capacitors (Fig. ), and ξ where ε capacitance of this sub-array s interna interconnections. n genera (=0,,, 3.) the error reations are + + = + ; = + ξ ; = ε + ε ε (3) is the where ε j is an error of j-th unit capacitor, is the capacitance error resuting from errors of a unit capacitors in the -th sub-array, and ξ is the capacitance of the sub-array interconnections. The interconnections between the sub-arrays are made outside of the capacitor ban and the parasitic capacitance of those interconnections is denoted using the symbo χ. These interconnections wi be caed externa to distinguish them from the sub-array interna connections defined above. Usuay the externa interconnections are removed from the ban such that the couping to the bottom pate is wea. onsequenty the contribution, χ, of the interconnections between sub-arrays to the tota capacitance is usuay sma. The notation for the combination (parae connections) of sub-arrays, is iustrated beow. For the summation of and yieding 3 we have: 3 3 = + + χ () Using () to show the contribution of errors of the component sub-arrays we obtain the expression 3 3 = χ (5) which defines the error in the capacitance 3 as foows 3 3 = + + χ. (6) Anaogous procedure yieds the errors for other summations of sub-arrays. For exampe the error of the capacitance 7 which is created by a summation of sub-arrays,, and is given in the form 7 7 = χ. (7) Such error formuas are easiy deveoped for any combination of sub-arrays. nterconnect ayout requirement apacitance of interconnections shoud be considered because the unit capacitors formed by poysiicon pates separated by ayer of oxide and thin ayer of nitride are sma. These additiona capacitances create a probem of circuit parameter accuracy. A soution to this probem is obtained through carefu design of interconnection ayout guided by an observation that parameters of FPAA function are determined by ratio of capacitors [Dabrowsi 997]. An exampe of second order (biquadratic) transfer function V V out in bsg s b g = '' B ' s + s + " " AT A T s + s+ T T A B A B (8) 3

4 impemented in FPAA as shown in Fig. iustrates that the coefficients of the transfer function are indeed dependent on the ratios of circuit capacitors. Φ Φ ' A V in Φ Φ Φ Φ _ + Φ 3 Φ Φ Φ _ + B V out " Fig.. High-Q biquad impementation in FPAA. [ Therefore if the tota capacitive contributions (incuding interna and externa connections), ξ ], of active ban interconnections, are proportiona to the seected number of unit capacitors connected [ ] [ ] together, i.e. ξ = ξ [, where, ξ ], is the eementary (reated to the unit capacitor) interconnection contribution to the capacitance, then the tota resuting capacitor vaue is [ ] [ ] = u + ξ = u + ξ c h. (9) Such idea interconnect capacitances wi be caed proportiona. t is easy to verify that in the case of proportiona interconnect parasitics the coefficients of the transfer function are not infuenced by the interconnects. A ayout of capacitor ban in MPA00 was designed with the goa to obtain proportiona interconnect parasitics of interconnects. Anaysis of interconnect ayout, which aows for verification of parasitic proportionaity is presented in the next section. Anaysis of capacitor ban ayout Methodoogy of ayout anaysis The existing capacitor error mode encompasses the quantization error and errors caused by the manufacturing process of two distinct inds: macroscopic and microscopic errors. Both, macroscopic and microscopic errors due to process imperfections are random, so in the overa error mode they are accounted for using random variabes theory. There are, however, systematic error sources aready buit into the capacitor ayout. Within one capacitor ban, there are additiona interconnection parasitic capacitors affecting the accuracy of the seected capacitor size. Athough the ayout is carefuy designed to compensate this error, it cannot be eiminated competey because of other constraints. Detaied evauation of the actua chip measurements and anaysis of the ayout pot confirm the existence of errors. n the foowing part of this section, we propose a methodoogy for investigation of ban interconnection capacitance caused by overap of the bottom ayer and the meta ayer. Fig. 3 shows a simpified part of the capacitor ban ayout, representing a sub-array consisting of two unit capacitors. We see that the bottom pate of a singe unit capacitor is arger than its top pate. To connect a

5 singe capacitor either with the other capacitors within a sub-array or to connect two sub-arrays, meta connections (hatched area) are needed. These interconnections in the respective top pates. bottom pate top pate meta ayer meta ayer/top pate interconnection Fig.3. Simpified part of the capacitor ban ayout. By inspection of Fig. 3, it can be seen that each sub-array has a specific area of overap of the meta ayer and the bottom pate (gray-hatched area). These regions of overap occur either due to interconnections within the sub-array or due to the connection of different sub-arrays. Therefore, depending on the capacitor size to be reaized in one ban, the additiona interconnection capacitor area wi increase or decrease. At this point it is important to mention again that the performance of a s/c circuit is not dependent on a singe capacitor vaue but on the ratio of two capacitors or product of ratios. Therefore, the main goa is to eep the tracing error (i.e. the error in the ratio) as sma as possibe. f we design the capacitor ban ayout to get an additiona interconnect capacitance exacty proportiona to each possibe capacitor size, the tracing error wi disappear. To obtain an adequate representation, a new approach to describe the impemented capacitor of size is chosen: M M   = 0 = 0 [ ] [ ] [ ] [ ] = a + a D + c, a Œ 0, p (Error! o text of specified stye in document.-) where M equas 7 for a capacitor ban size of 55. a stands for the binary digits in the digita capacitor [ size representation of, ] is the idea capacitance containing [ unit capacitors, and D ] is the error term incuding sub-array interna interconnections. c [ ] finay represents the interconnection capacitance between different sub-arrays. Therefore, the idea capacitor of size u can be expressed as   L 7 = = M 7 = 0 = 0 [ ] [ ] a a u. O QP (Error! o text of specified stye in document.-) The sub-array interna interconnect capacitance x [ ] of a capacitor incorporating unit capacitors can be written in anaogy to (Error! o text of specified stye in document.-) as 5

6 7 Â [ ] [ ] x = a x = a b ( a u). = 0 = 0 7 Â (Error! o text of specified stye in document.-3) The b whose numerica vaues are shown in Tabe Error! o text of specified stye in document.- represent numbers in proportion to the additiona capacitor area obtained by measuring the area size in the capacitor ban ayout. A scaing factor a has to be introduced, so that x [ ] represents a capacitance. ts numerica vaue has to be determined by capacitor error measurements, which has not been done yet. b 7 b 6 b 5 b b 3 b b b Tabe Error! o text of specified stye in document.-. umerica vaues for b obtained by capacitor ban ayout anaysis. For the interconnection capacitances c [ ] between different sub-arrays, we get equation (Error! o text of specified stye in document.-) from anaysis of the ayout. where again the scaing factor a from above is used. c [ ] R S 3 Â a u ; a a > 0 = = 0 T 0 ; otherwise, (Error! o text of specified stye in document.-) Resuts of anaysis of MPA00 ayout Appying the equations (Error! o text of specified stye in document.-3) and (Error! o text of specified stye in document.-) for each possibe capacitor size to be set up with one ban, a graph (Fig. ) can be potted showing the resuts for the different capacitor sizes. t is important to mention that the scaing factor a from above was chosen to be as statistica capacitor error measurements were not yet avaiabe. This has no infuence on the genera curve shape. 6

7 Tite: ic_cap.eps reator: MATLAB, The Mathwors, nc. reationdate: 0//98 :3:36 Fig. : Additiona interconnection capacitance and its inearity error; a) interconnect parasitic capacitance versus the capacitor size, b) reative inearity error versus the capacitor size. The reative inearity error is computed by comparing the measured data in Fig. a to an idea curve, ξ, that is obtained through inear fit to the data shown in Fig. a. This yieds the formua ξ ξ e re. in =. (0) ξ The curve in Fig. a appears to be inear. f there were no error, we woud in fact get an idea curve of inear shape. However, inspecting the pot of the reative inearity error in Fig. b it can be easiy seen that there are discontinuities at certain capacitor sizes in the pot. Especiay at sma capacitor vaues, these discontinuities introduce a strong non-inearity in the graph (it wobbes ). Speaing in terms of the tracing error, it is obvious that use of sma capacitors in the s/c circuit decreases the accuracy of the desired capacitor ratio, because the interconnection parasitics are not proportiona at sma capacitances. Verification of resuts via measurements Measurement technique The anaysis of capacitor ban interconnections was verified by measurements performed using inverting gain stage circuit shown in Fig. 5. The approximate transfer function, obtained under the assumption that stc z = e + stc (where Tc = is the coc period), of the circuit is f c 7

8 b g H s Vout s + 3 stc = = V s + st in b g b g b g g c 3 s + f c = s+ fc. () ote that this is an approximation, which wi ony be usefu for frequencies smaer than fact with a system, which is time discrete and ony continuous in the samped data vaues. f c. We dea in Φ Φ Φ v in Φ Φ _ + v out According to Marus Spitz the TF in the z-domain is z -. Measurements were obtained using the above circuit in connection with a sampe-and-hod stage at the output. Φ 3 Φ Φ Φ Φ Φ (v) - V in + V out Fig. 5 FPAA schematics to measure the interconnection effects on capacitor errors; the phase Φ is the odd phase and Φ is the even phase [Dabrowsi 997]. The magnitude of frequency response is b g = H jω F 3 ω + fc H G F ω + fc H G KJ KJ. () 8

9 The circuit was programmed in such a way that the capacitors and were both fixed and had arge quantities such that /. onsidering that the signa frequency was KHz and that the coc frequency was MHz, (5) simpifies to b g = H jω 6 3 π 0. (3) + F H G K J n addition, assuming that 3 3 >> π 0 (which is easy to accompish by seecting the capacitors and 3 to have approximatey the same vaues) we obtain further simpification of (6) to the form H jω (5) b g = 3 representing a gain which can be easiy measured. Gain measurements and capacitor errors We describe here the appication of error definitions to represent measurements and error of gain stage, impemented on the FPAA. To estimate the capacitor error properties, we change the nomina vaue of = u (and aso the vaue of because of the assumption ()) from u to u where =55, and 3 measure the output votage at constant input. We assume that the capacitor is arge, it is formed from the entire ban capacity, i.e. = = u. Using the introduced capacitor error notation we write the idea gain of the anayzed circuit as 3 a = = and the actua gain in the form u 3 b = = = u The gain error G = a b can be easiy represented as F HG 3 3 G = 3 KJ to the first order of accuracy and substitution of (6) into (8) yieds F G = u 3 K J. (9) HG The differentia non-inearity error [Van Pasche 99] can now be expressed in terms of capacitor errors as foows () (6) (7) (8) 9

10 Difer = G G = 3 3 a a u F HG K J (0) which shows that it is a difference between the errors in consecutive vaues of capacitor 3 ess a constant. These differentia errors are recorded and used to evauate the effects of capacitor ban interconnections on tota capacitance. Methodoogy for data representation t wi be usefu to define the difference of differentia errors DD = Difer Difer yieding the formua DD = + u e j () which is convenient in evauating the contribution of interconnections. These second order differences of the measured gain errors show expicity the contributions of capacitor ban interconnections. To simpify the notation, in the discussion to foow, the subscript at the symbo of capacitance 3 wi be dropped in a the reations beow, i.e. it wi be assumed 3 = such that DD = + u e j. () t can be easiy demonstrated that for the subscripts 3 and those that are powers of, i.e. i for = 3,, 8,..., these differences are unique and thus they wi be caed basic differences. The differences with other subscripts, which are not powers of, are combinations of basic differences and capacitance contributions of externa interconnections between the sub-arrays. A few exampes of basic differences are given beow. For = 3 using the appropriate capacitor error expressions we get the formua showing the contribution χ 3 of interconnection between the sub-arrays ( and ) forming the capacitor 3 as foows 3 DD3 = u e + j = e u 3 + χ j (3) Using the reation for the sub-array capacitor errors (3) we obtain the formua showing expicity the contributions of unit capacitor errors and those of interna interconnections DD 3 = u e + ξ ξ + χ 3 j. () For = we obtain 3 DD = e + j = e u u 3 χ j (5) and again, using (3) to show the contributions of interna interconnections we get DD = u e + j+ ξ eξ 3 + ξ j χ. (6) 0

11 These reations show neaty the potentia for canceation of interna sub-array interconnections. For exampe in the ast case ( = ) the term ξ eξ + ξ j is zero (or very sma) if the contributions of interna sub-array interconnections are proportiona. t is expected that the unit capacitor errors aso cance as indicated by the term e + j and that the externa sub-array interconnection capacitance χ 3 is sma. Therefore, if these canceations indeed tae pace the difference (6) shoud be a sma quantity. Otherwise some terms must be arge indicating a ac of canceation in unit capacitor errors or a ac of proportionaity in contributions of interna interconnections or unusuay arge contribution of externa sub-array interconnections. This brief discussion indicates that the differences introduced here are usefu in detecting abnormaities in the interconnections of capacitor ban. Some exampes of non-basic differences ( DD with indexes which are not powers of ) are for = DD5 = DD + χ + χ u e j (7) for = DD6 = DD3 + χ χ + χ u e j (8) and for = DD7 = DD3 + χ + χ χ + χ u e j. (9) These second order differences are usefu in evauating the effects of interconnections on capacitor vaues. A coser inspection of the basic differences shows that they represent the errors due to a ac of canceations in capacitor errors or a ac of proportionaity in capacitance contribution of interna subarray interconnections. The other differences can be used to detect the errors due to the contributions of externa interconnections between sub-arrays. A sampe of measured data A pot of second order differences in gain errors of the first order circuit (Fig.5) impemented in the MPA00 chip and measured using the above described methodoogy is shown in Fig. 6. This pot has a compressed horizonta axis, the quantities are difficut to read and thus it is usefu ony in portraying quaitative overa picture of errors. To obtain a quantitative information the vertica axis needs to be partitioned into a few intervas and the data dispayed in separate pots.

12 DD/ = Differ/ - Differ/(-) Series Fig. 6. Difference of the differentia error over the whoe range of a capacitor ban. Fig. 7 represents a zoom on the Fig. 6 (the range of subscript is imited and ranges from = to = 9) to aow more detaied anaysis of measurement resuts. This aows for convenient comparison with the behavior predicted by the deveoped anaytica mode of interconnection errors. DD/ = Differ/ - Differ/(-) Series Fig. 7. Difference of the differentia error for the subscript range: = 3 to = 9. n Fig. 7 we can have a coser oo at detais. Athough these measurements incude a error sources present on the chip, the theoretica behavior of the interconnect capacitance contributions can be confirmed. According to theory, DD 7 has, negecting the connections between sub-arrays, the same

13 magnitude as DD 6 but different sign (compare equations (6) and (7)), which is indeed the case portrayed in Fig. 7. t shoud be pointed-out that, DD 7 in the graph has amost the same magnitude as DD 3 (equation (7)). This again shows that the contributions of externa interconnections, c, are of very sma magnitude. Further cacuations (which are not shown in this paper) revea that the vaue for DD 8 is independent of the vaue for DD 7, whereas for DD 9 we expect the negative vaue of DD 8 if the contribution due to the externa interconnections is sma. The pot indeed shows that the magnitudes of DD 9 and DD 8 are amost identica. This indicates that the externa interconnection capacitance, c, contributes very itte, and this is aso confirmed independenty by the anaysis of capacitor ban ayout presented in a previous section. Simiar behavior with an even more impressive match between theory and the measurements is observed in the regions of powers of, which is especiay we visibe around = 6 and = 8. This is shown in Fig. 8 and Fig. 9, which both represent the respective zoomed parts of Fig. 6. DD/ = Differ/ - Differ/(-) Series Fig. 8. Difference of the differentia error for the subscript range: = 50 to = 99. 3

14 DD/ Series Fig. 9. Difference of the differentia error for the subscript range: = 00 to = 9. oncuding remars The anaysis of effects of interconnect parasitics in FPAA capacitor bans and actua measurements show that these undesirabe effects can indeed be successfuy minimized, especiay for arger capacitors, through carefu ayout of interconnect metaization. The resuts are usefu in buiding the FPAA capacitor error mode, which permits evauation of performance imitations of various FPAA functions, such as for exampe anaog fitering [Bir 998] and can be used in deveoping design rues. The methodoogy for representation of measured data can be easiy automated and used for identifying the probem areas in the interconnect ayout. The anaytica deveopments of ayout verification and introduced metric of ayout imperfections in terms of proportionaity and parasitic capacitances are nicey confirmed by the measurements. References. Anderson, D.,. Marcjan, D. Bersch, H. Anderson, P. Hu, O. A. Pausinsi, D. Gettman,. Macbeth, A. Bratt, 997, A Fied Programmabe Anaog Array and its Appication, 997 ustom ntegrated ircuits onference Proceedings, May, 5-8, 997, Santa ara, aifornia, USA.. Bir,., 998, Evauation of Fiters mpemented Using Fied Programmabe Anaog Array, WM 98 - SEE, San Diego, aifornia, Jan. -, Dabrowsi, A., 997, Mutirate and Mutiphase Switched-apacitor ircuits, hapman & Ha, 997.

15 . Dorn, H., 998, Synthesis of ontroers for Feedbac Systems Using an FPAA,, San Diego, aifornia, Jan. -, Pausinsi, O. A., D. Anderson, D. Gettman,. Marcjan, H. Anderson, 997, Motoroa Fied Programmabe Anaog Arrays in Simuation, ontro, and ircuit Design Laboratories, 997 Winter Simuation Muti-onference, Jan. 3-5, 997, Phoenix. 6. Van Pasche, R., 99, ntegrated Anaog-to-digita and digita-to-anaog converters, Kuwer Academic, pp Web pages, 998, 5