CONCERT: A Concurrent Transient Fault Simulator for Nonlinear Analog Circuits *

Transcription

1 CONCERT: A Concurrent Transient Faut Simuator for Noninear Anaog Circuits * Junwei Hou and Abhijit Chatterjee Schoo of Eectrica and Compute Engineering, Georgia Institute of Technoogy, Atanta, GA {jhou, chat}@ee.gatech.edu Abstract This paper presents a nove concurrent faut simuator (caed CONCERT) for noninear anaog circuits. Three primary techniques in CONCERT, incuding faut ordering, state prediction, and reduced-order faut matrix computation, greaty simpify faut simuation by maing use of the residua simiarities between the fauty and faut-free circuits. Between successive time steps, a circuits in the faut ist are simuated concurrenty before the simuator proceeds to the next time step. CONCERT aso generates accurate faut coverage statistics that are tied to the circuit specifications. Up to two orders of magnitudes speedup are obtained for compete faut simuation, without any oss of accuracy. More speedup is achieved by CONCERT for evauating the faut coverage of a test, using faut ordering and faut dropping technique. Introduction The faut simuation probem for noninear anaog circuits is argey unsoved due to the compexity of anaog simuation and the difficuties of simuating many anaog fauts simutaneousy. In the digita word, concurrent faut simuation methods are we entrenched as the effects of mutipe digita singe-stuc-at fauts can be propagated simutaneousy from one gate to the next using ony oca information around the circuit nodes to which the faut effects have propagated. In contrast, anaog fauts typicay affect votage and current vaues across a the circuit nodes and branches, respectivey, thereby maing concurrent anaog faut simuation very difficut. Currenty, seria simuation of anaog fauts is the prevaent anaog faut simuation methodoogy used in industry. As a consequence, comprehensive faut simuation of arge mixed-signa circuits is amost impossibe with today s toos. In the digita domain, faut simuation agorithms are based on parae faut simuation [2] and concurrent faut simuation [4] methods. In the anaog domain, no fast faut simuation techniques have been reported for noninear circuits under genera transient stimuus. Frequency domain (AC sma signa) faut simuation of anaog circuits inearized around the DC bias points for parameter * This wor was sponsored by U.S. Defense Advanced Research Projects Agency (DARPA) under Contract No. F toerances is discussed in [3]. This approach is based on the assumption that the DC bias points of the fauty and faut-free circuits are the same, hence, disaowing arge circuit parameter deviations under faut. Househoder s formua [5] is used to assess the impact of the component toerances on the AC response of the circuit under test (CUT). In [7], the authors have discussed the idea of concurrency which avoids re-evauation of those components that have the same interna node vaues as in the faut-free case. A faut simuator caed DRAFTS [9] has been deveoped for seria faut simuation of inear anaog circuits. FLYER [5] reports significant improvement upon DRAFTS for fast faut simuation of inear anaog circuits. A fast faut simuation method using faut ordering and circuit partitioning is reported in [6]. Househoder s formua has aso been appied to anayze mutiparameter argechange sensitivity in inear networs [7]. In this paper, we present a fast and accurate concurrent faut simuator CONCERT for noninear anaog circuits. The paper is organized as foows. An overview of our faut simuation approach is discussed in Section 2. Section 3 provides the bacground for our faut simuation methodoogy. Section 4 presents the proposed concurrent faut simuation agorithm. Various techniques used for concurrent faut simuation are detaied in Sections 5, 6, and 7. The overa faut processing is discussed in Section 8. Simuation resuts are given in Section 9. This is foowed by concusions in Section 0. 2 Faut Simuation Methodoogy The faut simuation methodoogy on which CONCERT is based on are as foows:. A set of training circuit instances, each instance corresponding to a set of different circuit parameter vaues, is first generated. This is performed using statistica methods so that the instances ie across and near the circuit specification boundaries, i.e. some of the circuit instances correspond to good circuits and some correspond to bad circuits. This set of training circuit instance is inserted into a faut ist. The faut ist is then expanded to incude a faut universe which may incude parametric fauts and catastrophic short and open fauts specified by the user. 2. For the specified transient stimuus, concurrent faut simuation is performed as foows: (a) between successive time steps a the circuits in the faut ist are simuated before proceeding to the next time step; (b) if the circuit time step corresponds to one in which the CUT output(s) is samped (the samping frequency is an input to the simuator), then the measurement threshod for that time step is seected in such a way as to give unity yied coverage (this means that no good circuit instance is cassified as bad by choice of the threshod); and (c) a circuit instances in the faut ist that are detected due to the

2 choice of the measurement threshods are dropped and simuation is continued. 3. Faut coverage statistics that are tied to the circuit specifications are generated. Note that here we differ from digita faut simuation in that: (i) the anaog faut simuator need to seect the measurement threshods based on the specifications which may not given in the time domain; (ii) the faut ist contains some good circuits as we as bad for the purpose of measurement threshod seection. In the above, if desired, faut dropping (2(c)) is not performed if the transient response of the CUT over the entire simuation interva for every faut is of interest, say, for diagnosis purposes. The faut simuation methodoogy is iustrated in Figure. The Generate Faut List Faut Processing Concurrent Faut Simuation Agorithms State Prediction Faut Ordering Faut Dropping Reduce-Order Faut Matrix Computation Coverage Statistics or Faut Dictionary Figure Faut Simuation Methodoogy of CONCERT ey contributions of CONCERT are in step 2 described above. The simuator simuates a the entries in the faut ist at every time step before proceeding to the next. This concurrent process aows CONCERT to maximize the sharing of simuation effort for a circuit instances in the faut ist. The goa is to use as much information as possibe from the simuation of every circuit instance in the faut ist to simpify the simuation of the next. Three primary techniques is used to accompish the concurrent faut simuation:. Faut Ordering: Based on the states of the circuit instances, a the circuit instances in the faut ist are ordered at every time step. The dynamic ordering is done in such a way as to maximize the simiarity between consecutive fauts. 2. State Prediction: Given the order specified in the faut ist, the state of the i-th circuit instance in the faut ist is predicted from the state of the i--th simuated circuit instance in the faut ist at every time step. The predicted state greaty reduces the number of Newton Raphson (NR) iterations for soving the system of noninear equations. 3. Reduced-order Faut Matrix (RFM) Computation: Based on the residua simiarity between the noda admittance matrices of the fauty and faut-free circuits, the system of fauty circuit equations is transformed into a reduced-order system of equations and soved with much ess computationa effort. Househoder s formua [5] and sparse matrix technique [6] are used for the transformations. The concurrent faut simuation techniques in CONCERT appy to DC, AC, and transient faut simuation of genera inear and noninear anaog circuits. For reasons of brevity, this paper wi focus on DC and transient faut simuation agorithms. 3 Anaog Circuit Simuation Basics Our concurrent faut simuation approach is based on conventiona modified noda anaysis (MNA) and numerica integration methods [4]. In the foowing, we first discuss the MNA formuation for circuit simuation. We wi then show that most of the entries in the MNA matrix are invariant under faut and this greaty reduces the computations invoved in soving the inearized system of equations. In this paper, we use the term faut to denote a circuit instance in the faut ist. The subscript f is used to denote a faut, the subscript n denotes the time step t n in transient anaysis, and the superscript denotes the -th iteration in the NR equation soving procedure corresponding to time t n. In genera, the system of circuit equations is written as: YU = I, Y R m m, U, I R m () where Y is the modified noda admittance matrix of the circuit, U is the vector of unnown node votages and branch currents, and I is the RHS contributed by the nown current and votage sources. Consider the exampe noninear circuit in Figure 2, the inearized system of equations for DC anaysis is: g d g d g d g d r v + v 2 + i 3 i d v d i d v 2 i 3 v d r c e(t) Figure 2 An exampe noninear circuit where g d is the dynamic conductance and i d is the current of the diode, both evauated at the diode s termina votage v - v 2. Starting with a DC input e(0) and an initia guess v 0, v 0 2, and i 0 3, the system of equations is soved for v +, v + 2, and i + 3 iterativey for =0,,..., unti the soution converges. Transient anaysis is based on stiffy stabe integration methods with companion modes for memory components [4]. For the circuit in Figure 2, the inearized equations at time t n are: g d g d g d g d y r n v n + v 2n + i 3n where y n is the companion conductance and j n is the companion current source of the capacitor corresponding to time t n. Ony after = i d e i d = i d + j n e (2) (3)

3 the NR iterations converge at time t n, can the simuation be advanced to the next time step in transient simuation. In genera, this can be formay stated as soving a system of noninear circuit equations (at time t n ): f( U n ) = 0 using Newton-Raphson (NR) iteration method: + J( U n ) U n = f( U n ) + J( U n ) U n here J(U n ) is the Jacobian matrix of f(u n ) evauated at U n, and U + n is the -th iterative soution. In each NR iteration, the noninear components need to be re-evauated, i.e. the system of equations is re-inearized. The iterative soution is assumed to converge to the soution point when vectors U n and U + n are significanty cose. The number of NR iterations and its convergence heaviy depend on the initia guess U 0 n. The cost of inearizing and soving the system of circuit equations dominate the computationa cost of circuit simuation. 4 Concurrent Faut Simuation Agorithm For transient faut simuation, a the fauty circuits aong with the faut-free circuit are simuated concurrenty at time t n before simuation proceeds to the next time step. The same time step is used for a faut simuations and is determined by faut-free simuation. Agorithm concurrentfautsimuation(t n ) 0 normacircuitsimuation(t n, faut_free_circuit); 02 orderfauts(t n, {faut_ist}); 03 precomputerfm(t n, faut_free_circuit); 04 for each f {faut_ist} do 05 U 0 f := predictstate(f); 06 := 0; 07 do //Newton-Raphson (NR) iterations 08 U + f := soverfm(t n, f); 09 := + ; 0 unti isconverge(t n, f) end for Figure 3 Concurrent faut simuation agorithm Figure 3 shows the agorithm of concurrent faut simuation at time t n. The faut-free circuit is first simuated in function norma- CircuitSimuation() which uses the conventiona circuit simuation method []. A the fauts is ordered in the faut ist in function orderfauts(), which wi be described in Section 7. Every faut is simuated using NR method as shown in the do-unti oop. Functions precomputerfm() prepares the common data for soverfm(), which impements the RFM procedure for reducing the computationa cost in soving the system of inearized equations. Function predictstate() impement the state prediction method which reduce the number of NR iterations. The RFM procedure is expained in Section 5 and the state prediction method is expained in section 6. Function isconverge() checs if the NR iteration converges. This genera agorithm aso appies to DC faut simuation, which is considered as a specia case with t n being 0. For transient faut (4) (5) simuation, the same procedure wi be caed at every time step for the entire test stimuus interva. 5 Reduced-order Faut Matrix Computation When the circuit is fauty, the circuit equations are changed. But certain simiarity between the fauty and faut-free circuit equations sti exists. The difference in the circuit matrix can be captured by extracting the differences of the component conductances under that faut. Since the state of a noninear circuit is affected under faut, some noninear components in the circuit may aso have different behavior than in the faut-free case. It is important to point out that not a the noninear components dynamic behaviors are affected by the faut at a times, especiay in arge mixed signa circuits. In the noninear circuit in Figure 2, ony during a sma period of time, the diode exhibits significanty different conductances in fauty and faut-free case. During majority part of its rectifier operation, the diode is on or off, as iustrated in Figure 4. During that period of transient simuation, the v on : v d >0.7, off : g d ~ v d <0, g d ~ 0 e(t) faut-free response response with r fauty Figure 4 Simiar responses and states of fauty and faut-free circuits in Figure diode gives the same dynamic conductance as in the faut free case. We define a component to be visibe if the difference between its dynamic conductances in fauty and faut-free circuits is arger than certain numerica threshod. Otherwise, it is invisibe. A fauty component in a circuit is thus aways visibe according to this definition. The tota number of visibe components is equa to the number of fauty components pus the number of visibe noninear components in the circuit. The visibiity of a noninear component may change between NR iterations. 5. RFM Computation Consider a fauty circuit with visibe components at -th iteration, and the conductance differences between the faut-free and fauty case are δ i, i=,..., respectivey. The difference matrix between the fauty and faut-free circuits can be expressed as: Y f T = Y f Y = P f D f Q f t period when fauty and fautfree circuits have significanty different diode conductances r δ 0 where, D f R s q =, P f =, Q f =, r p 0 δ s q p (6)

4 P f, Q f R m, and Y is the noda admittance matrix of the faut-free circuit at its soution point. The i-th visibe component is connected from node r i to s i, and controed by the termina votage between node p i and q i. For the specia case of a resistor, nodes (r i,s i ) are the same as nodes (p i,q i ). The inearized fauty circuit equations can now be written as: T + ( Y + P f D fqf ) U f = I f By appying Househoder s formua, we get: + U f Y T P f [ D f + Q f Y Pf ] T ( Q f )Y = I f Since the LU factors of Y are nown from faut-free simuation, it just taes one forward and bacward substitution (FBS) to get an intermediate resuts of E f Y T = I f. And vector F f Q f E f can be easiy fied up based on the simpe matrix structure of Q f We define the Reduced-order Fauty Matrix (RFM) as T R f [ D f + Q fy Pf ]. If we now that the inverse of Y is Z, we can precompute part of the RFM: Z p r T p s q r + Z q s Z p r p s q r + Z q s Q fy Pf = Z p r p s q r + Z q s Z p r p s q r + Z q s Now, the fauty system of equations in (7) is forward transformed into a system of equations with reduced-order : Once we sove for H f in (0), we need to bacward transform the resut to the origina fauty system of equations (7), for which we need to find the matrix product: (7) (8) (9) R,, (0) fh f = F f R f R H f, Ff R G f Y P f H f () There are two ways to compute this matrix product. One is based on the inverse matrix Z of Y, and the product comes from the matrix mutipication. Another way to find G f is based on the observation that the coumn vector P f H f R m can be easiy obtained from the simpe matrix structure of P f. Therefore, the system of equations in () can be soved using another FBS based on the LU factors of Y. Finay, the soution of the -th NR iteration is = + U f = E f G f. (2) N Soving the system of Equations (8) using Sparse Matrix Sover MNA inearized system < T(m) Soution Figure 5 Procedure soverfm() Precomputed part of RFM Forward transform using Equations (0) Soving the system of Equations (2) (in RFM) Bacward transform using Equations (3) 5.2 RFM Procedure and Its Compexity This RFM computation is impemented in the procedure of soverfm() in Figure 3. The procedure is iustrated in Figure 5. The decision of whether the RFM computation shoud be performed depends on, the number of visibe components. An important issue in circuit simuation is that the circuit matrix be sparse using sparse matrix techniques [0], and the compexity of soving equations (7) is practicay O(m.5 ), where m is the order of the equations [0]. Since the RFM matrix is fied from the inverse of Y, itis not sparse. Hence the compexity of soving (0) is O( 3 ). Hence, we choose the decision function in Figure 5 as T(m)= m. If exceeds m, the RFM approach is bypassed. Simiar decision needs to mae in bacward transformation, since the computationa compexity of FBS is around O(m. ) using sparse matrix techniques. When there is ony one visibe component, which is the singe fauty component, the fauty circuit behaves as a inear circuit during this iteration with respect to the faut-free circuit, since a the noninear components are invisibe. Then, soving (0) needs just one division, and the bacward transformation can aso be simpified to just fiing the vector G f from Z. The RFM procedure thus speeds up faut simuation in the foowing ways:. Ony visibe noninear components are evauated at each iteration based on the differences in their termina votages. 2. Instead of the MNA matrix, a much smaer RFM is fied and factorized. 3. The cost of forward transformation may be shared between consecutive fauts in the faut ist, if they have very cose circuit states, which resut in the same RHS in equations (7). It is important to note that a the entries in part of the RFM matrix in equations (9) are faut-independent and ony depend on the Z matrix and the topoogica structure of the visibe components. We can precompute this matrix from Z according to a the noninear and fauty components in the circuit. So the RFM matrix can be directy fied up based on the visibe components at the -th iteration. This pre-computation is performed in function precomputerfm() in Figure 3. Since the LU factors of Y are readiy avaiabe from the faut-free circuit simuation, inverting Y needs about two times more computations compared to one LU factorization. This computationa overhead is we paid off when faut simuation for hundreds of fauts are performed concurrenty. Experiments show that the RFM procedure is stabe numericay. It can be shown that the RFM is not singuar as ong as the origina MNA matrix is not singuar. Y

5 6 State Prediction Whie the RFM approach reduces the computationa compexity within an NR iteration during faut simuation, state prediction method computes an initia guess cose to the fina state and reduces the number of NR iterations significanty. In this method, the simiarities in response between two consecutive fauts in the faut ist under the same stimuus is expoited to compute the best initia guess for the NR iterations. Since the states of two consecutive fauts are the cosest according to faut ordering criteria, the state of the preceding fauts in the faut ist shoud be a good initia guess for the NR iterations in the simuation of the next faut. Since NR iterations converge quadraticay near its soution point, a good initia guess wi greaty reduce the number of NR iterations. An intuitive method in state prediction for DC faut simuation of the next faut f 2 is to tae the state of the preceding faut f as the initia guess. That is: 0 U f 2 = U f (3) This simpe heuristic method wors extremey we for DC faut simuation and resuts in much ess number of NR iterations than other initia guesses based soey on the circuit structure. Further, since the initia guess is cose to the fina soution, the NR iterations for fauty circuits are now more iey to converge. In the case of transient anaysis, circuit simuators have used the state at the previous time step as an initia guess for NR iteration at the present time t n.ani-th order poynomia using previous i+ time step states is proposed for an initia guess []. In practice, most circuit simuators use a first order poynomia, since highorder poynomia interpoation offers about the same speedup. Our state prediction approach for transient faut simuation is based on the simiarity between the oca response waveforms of two consecutive fauts. To iustrate our approach, consider Figure 6 F (t) u n- u n-2 F 2 0 (t)=αf (t)+β u2 n- u n u2 n (a) Loca waveform of the faut f 0 x u2 n + inear interpoation fauty state prediction fina resut u2 n-2 (b) State prediction for the faut f 2 Figure 6 State prediction with reference to the preceeding faut which shows the state prediction at time t n for a faut f 2 using the simuation data from the preceding faut f. A second order poynomia function F (t) is first buit for the faut f, using the states, u n- 2, u n-, and u n. This poynomia function is then used to buid the prediction function for the next faut f 2 : + x 0 F 2() t = αf () t + β (4) which is aso a 2nd order poynomia. To determine the constant α and β, two previous states and of faut f 2 are used. u 2n u 2n 2 In the case that a fixed time step is used for this exampe, with t n t n = t n t n 2, the vaue of the prediction function at time t n can be derived as: 0 0 u n u n u 2n = f 2 ( tn ) = u 2n ( u u n u 2 n u 2 n 2 ) n 2 (5) which wi be used as the initia guess for soving u 2n in NR iteration for faut simuation. As we can see that the overhead of state prediction in faut simuation is very sma. 7 Faut Ordering Faut ordering is a ey issue in predicting the state of the next faut accuratey. The response of one faut may be more simiar to the response of another faut rather than to that of the faut-free circuit. Therefore, more accurate state prediction can be achieved by using one faut response to predict the state of the next faut. For precise DC faut simuation, a the fauts in the faut ist are ordered in terms of their parameter deviations, which are the ony information accessibe before DC simuation. A precise DC soution is necessary for transient faut simuation. In transient faut simuation, a the fauts in the faut ist are ordered in terms of their previous transient responses as shown in Figure 7. When faut simuation proceeds to a new time step t n+, responses F f (t) F f2 (t) F f3 (t) F f4 (t) F f5 (t) t n- t n t n+ t Faut List (ordered before t n+ ): f5, f3, f, f2, f4. Figure 7 Faut ordering based on fauty responses a the fauts are ordered using the simuation data from the previous time steps. Then, faut simuation are performed at t n+. In particuar, a weighted sum of the previous time output responses are used as a ey λ for faut ordering, that is: λ = a 0 u f n + a u f n + (6) Our experiments indicate that a 0 = 2, a = provides a good choice for this ey function, which gives a faut ordering with better state prediction. Faut ordering is impemented in the procedure orderfauts() in Figure 3. Compared to the compexity of soving a set of inear equations, the computationa overhead of faut ordering and state prediction is negigibe. At every time step, fauts in the faut ist are ordered, but few of the fauts need to change their position with respect to the previous time ordering.

6 8 Faut Processing and Faut Coverage Anaysis In test generation appications, faut simuation is primariy used to estimate the faut or yied coverages of a test. For speeding up faut simuation, our approach empoys eary faut dropping to those fauts that are detected at eary steps of test stimuus appication. Our approach aso estimates threshods to separate good and bad circuits. 8. Test Measurement Threshod Threshods on circuit specifications are often specified by circuit designer. For test other than specification tests (aternate tests), these threshods have to be determined from simuation data. In this paper, we propose concurrent Monte-Caro simuation to compute threshods for transient tests. The simuator first generates a arge number L of training circuits with independent norma distributions of certain toerance for the component parameters. Each training circuit is simuated to obtain its specifications. If the circuit satisfies a the circuit specifications, it is mared as good, otherwise it is mared as bad. After the specification simuation, we have a set of good circuits and a set of bad circuits. A ie across and near the circuit specification boundaries. Therefore, the transient test faut detection threshods can be computed by simuating a the L circuits under the test stimuus, as shown in Figure 8. Assume that the test requires 00% yied coverage. Then, the v THD i T i response of good circuit response of bad circuit T i : samping point THD i : threshod at T i Figure 8 Cacuation of measurement hreshod threshod at a samping point is the difference between the highest and the owest responses of a the good circuits. Figure 9 shows the agorithm of faut processing. The function Agorithm Faut processing and coverage anaysis 00 Input: {netist}, {faut_ist}, {stimuus}, {samping_times}; 0 {training_circuits} := L statistica experiment circuits; 02 specssimuation({training_circuits}); 04 Insert {training_circuits} into {faut_ist}; 03 for each time step t n do 09 concurrentfautsimuation(t n ); 0 if t n {samping_times} do //faut dropping THD := getthreshod(t n,{training_circuits}); 2 for each f e {faut_ist} do 3 if response(t n,f e ) > THD 4 {faut_ist} := {faut_ist} - f e ; 5 end if 6 end for 7 end if 8 end for 9 reture {faut_ist} // the set of fauts undetectabe Figure 9 Faut processing and coverage anaysis specssimuation() performs the specification simuation for a the training circuits and mars the good and bad circuits, as t described before. These training circuits are then inserted in the faut ist. Thereafter, a the circuit instances in the faut ist are simuated in concurrentfautsimuation() described in Figure 3. If the current simuation time t n is a samping time for faut detection, the measurement threshod is computed in getthreshod() shown in Figure 8. A the fauty responses are checed against the threshod and those detected fauts are dropped from the faut ist. The agorithm ends up with a set of undetectabe fauts under this test stimuus. Therefore the faut coverage can be evauated. 8.2 Eary Faut Dropping A typica transient test is iustrated in Figure 0. The response to a transient test for a CUT are samped at certain time points. Once v test stimuus T T 2 T t 3 Figure 0 Transient test measurement threshods CUT response samping point threshod the response of a faut deviates from the expected faut-free response by a certain threshod at a samping time, this faut is mared as detected. Therefore, this faut need not be simuated for the foowing samping time points. In our concurrent faut simuation agorithm, we propose eary faut dropping scheme to speed up the overa faut simuation. As the faut simuation proceeds to a new samping time point, those fauts which are detected are dropped from the faut ist. The faut simuation procedure obtains speedup through eary faut dropping due to two reasons:. Since many fauts are dropped during eary samping points, fewer fauts need to be simuated per time step on an average. 2. Those fauts which give arger response deviations at eary samping point are more expensive to simuate during ater time steps, since arge change in fauty states is harder to predict and taes more number of NR iterations during concurrent faut simuation. By dropping those fauts, the average number of NR iterations for each fauts is greaty reduced. 9 Experimenta Resuts The concurrent faut simuation agorithm has been impemented in a prototype simuation program caed CONCERT. It uses SPICE eve- modes for devices ie BJT, MOSFET, and diode etc. For soving the inearized circuit equations, CONCERT use the sparse matrix pacage deveoped in U.C. Bereey [6]. For accuracy and speedup, we compare the performance of CON- CERT with Spectre, an anaog circuit simuator from Cadence Design Systems. Tabe gives the various characteristics of the experimenta circuits for evauation. Among them, Biquad is a second-order ow pass fiter; Amp2 is a two-stage BJT ampifier; Sew is a sew rate fiter; Front is a circuit constructed by combining Amp2 with Sew. U74 is the 74 opamp form CircuitSim90 benchmars [8]. The opamps in Biquad, Sew, and Front are T i

7 Circuit # of fauty # of # of componests Test stimuus name circuits nodes signa stop time Biquad Puse(T w =5ms) 0ms Amp e-3sin(2e4πt) 0.2ms Sew sin(20πt) 40ms Front Puse(T w =0.ms) 0.2ms U sin(2e4πt) 0.4ms Tabe Exampe circuit characteristic described in macromode which incudes input and output votage imiting diodes inearized at v d >0.7vot. Each fauty circuit in the faut ist is generated by injecting singe catastrophic or parametric faut associated with a inear component in the circuit. Two catastrophic fauts (short and open) and 8 parametric fauts (with 5%, 5%, 50%, 80%, 20%, 50%, 200%, and 000% of the nomina vaue, respectivey) are generated corresponding to each inear component. Circuit name # of fauts DC faut simuation Spectre Concert Speed up TR faut simuation Spectre Concert Speed up Biquad Amp Sew Front U Tabe 2 Speedup of Concert over Spectre in simuation for the faut-free and a the fauty circuits Tabe 2 Compares the DC and transient (TR) faut simuation CPU time for the exampe circuits using Spectre and CONCERT on a Sun Utra. The data for Spectre is the intrinsic simuation time reported by Spectre accumuated for a fauts. The actua CPU time for Spectre is even onger due to the overhead invoved in setting up MNA. In transient faut simuation of the Biquad fiter, two order of magnitudes speedup was obtained using CONCERT. Even for U74 with precise device modeing for its 23 BJTs, we sti get 2.5 times speedup. For a other circuits, CONCERT was 6-2 times faster than Spectre. In DC faut simuation, higher speedups are obtained than in transient faut simuation. This is due to the fact that DC faut effects are much more ocaized, and that the state prediction method are far more better than random initia guess which is the case in DC circuit simuation. We aso coected some statistica data during faut simuation to show how speedup is achieved in CONCERT and why different speed up are obtained for various types of circuits. Tabe 3 gives the average number of NR iterations per time step per faut, with and without using the faut state prediction technique. It can be seen that the number of iterations is reduced by 50-65% in CON- CERT using state prediction for transient faut simuation, and much more for DC case. Further speedup is obtained by using the RFM technique, which gives quite different speedup for different type of circuits. Tabe 4 Circuit name DC faut simuation without state prediction with state prediction TR faut simuation without state prediction with state prediction Biquad 5 2 Amp Sew Front U Tabe 3 Average number of NR iterations Circuit name # of nodes DC RFM TR RFM Biquad 20 Amp Sew Front U Tabe 4 Average order of RFM shows the average order of the RFM for a the fauty circuit simuations performed concurrenty in DC and TR faut simuation. The order of RFM is equa to the number of visibe components at any simuation time, since ony visibe components wi contribute to the RFM. The order of RFM for the Biquad fiter is unity at every time step. This is due to the fact that the circuit is operating in its inear range under the test stimuus and CONCERT is very efficient when it detects that the order of RFM is one. For the other circuits, the order of RFM is higher. Among the noninear circuits, the faut simuation for the sew rate fiter gets the argest speedup because most of its noninear components are votage imiting diodes and the average number of visibe components is very sma. Therefore, the speedup obtained by CONCERT is mainy reated to the average number of visibe components in faut simuation. Circuits described in marcomodes or behaviora modes gets more speedup in faut simuation because of the ess number of visibe components. The output waveforms generated from CONCERT were found to match with that from Spectre simuation, with ess than 5% maximum error which is mainy due to the sight difference in time steps and device modeing. Figure shows the simuation outputs from CONCERT and Spectre for the sew rate fiter, with a test stimuus of 6sin(20πt). About 00 time steps are simuated both in CONCERT and Spectre x: faut-free response Fauty circuits with various faut vaues in C (a) CONCERT outputs (b) Spectre outputs Figure Simuation output of one faut-free and ten fauty circuits due to the capacitor C2 in the sew rate fiter

8 To demonstrate the faut processing capabiities of CONCERT, we use the stimui given in Tabe. We consider five measurements made on the transient response of the circuit excited by these stimui. The samping are distributed eveny on the time axis. The resuts of training set simuation is given in Tabe 5. The training set consists of 00 circuits with mutipe parametric fauts. This shows that CONCERT can perform faut simuation of mutipe fauts efficienty. The supporting simuation statistics are aso shown in the tabe. The simuation time in Tabe 5 are the CPU time for Spectre and Concert, both incude the overhead of setting up the MNA in simuation. The faut coverage of the transient measurements was estimated using the faut ist given in Tabe. The resuts are summarized in Tabe 6. The simuation time for Spectre are copied form Tabe 2. We can see that CONCERT achieves considerabe speedup for the purpose of faut coverage evauation. Circuit name Circuit name Spectre Concert # of training circuit Speed up Spectre ave. # of iteration Concert ave. order of RFM Speed up ave. # of iteration Biquad Amp Sew Front U faut coverage Biquad % Amp % Sew % Front % U % Tabe 6 Speedup of Concert over Spectre in faut simuation for faut coverage evauation of the test Tabe 5 Speedup of Concert over Spectre in faut simuation for training circuits 0 Concusions We present nove concurrent faut simuation agorithms for noninear anaog circuits. We beieve that CONCERT is the first of its ind of concurrent faut simuator for noninear anaog circuits. Significant faut simuation speedup is obtained for highy noninear circuits with pure anaog signas, without any oss of accuracy. Higher reative speedup are obtained for circuits described in macromodes, which are more attractive for deaing with compex mixed-signa circuits. Future investigation incudes how to achieve further speedup at the expense of accuracy. For exampe, how to reduce the number of visibe components by reducing the visibiity threshod. Other techniques for speeding up circuit simuation, such as muti-rate simuation, event driven circuit simuation and use of piecewise inear modes, can be used in conjunction with our concurrent simuation approach to further speedup faut simuation for various types of eectronic circuits. Acnowedgments The author woud ie to than Ramarishna Vooraaranam and Pramodchandran N Variyam for hep and vauabe discussions. 2 References [] R.K. Brayton, F.G. Gustavson, G.D. Hachte, A new efficient agorithm for soving differentia-agebraic systems using impicit bacward-differentiation formuas, Proceedings of the IEEE, Vo. 60, No., pp , Jan. 972 [2] G. Devarayanadurg, P. Goteti and M. Soma, Hierarchy based statistica faut simuation of mixed-signa ICs, Proceedings, Internationa Test Conference, pp , 996. [3] R. J. A. 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