An Approach to Worst-Case Circuit Analysis

Transcription

1 Eena Nicuescu, Dorina-Mioara Purcaru and Mariuscristian Nicuescu An Approach to Worst-Case Circuit Anaysis ELENA NICULESCU*, DORINA-MIOARA PURCARU* and MARIUS- CRISTIAN NICULESCU** Eectronics and Instruentation Departent* and Mechatronics and Robotics Departent** University of Craiova, Craiova, C.P. 585, A. I. Cuza Street, No. 13, ROMANIA Abstract: - In this paper, the authors intend to show how to appy the circuit description in paraeter space for a standard worst-case circuit anaysis (WCCA). DC or AC or transient worst-case circuit anaysis can be perfored ony by testing the circuit for the vertices of a poytope in conjunction with a circuit siuator or coputationa environent. In order to vaidate and show the effectiveness of this approach, DC and AC worst-case circuit anayses of an anaog eectronic circuit perfored in conjunction with a genera-purpose circuit siuator are presented and discussed. Key-Words: - Worst-case circuit anaysis, Anaog eectronic circuit, Poytope. 1 Introduction The behaviour of an eectronic circuit is affected when certain paraeters in specific coponents change. Worst-case circuit anaysis (WCCA) exaines the effects on eectronic circuits caused by potentiay arge agnitudes of variations of eectronic piece-parts beyond their initia toerance. WCCA provides a rigorous atheatica evauation of the perforance specification of a circuit against perforance toerance iits, under siutaneous existence of a the ost unfavorabe conditions being at reaizabe iits. This process is accopished by anayzing the variabiity of a circuit with respect to part paraeter toerance extrees. The variations can be the resut of both interna and externa factors as aging or environenta infuences, which can cause circuit outputs to drift out of specification [1], []. WCCA heps to design reiabiity into hardware for ongter, troube-free fied operation because the overstresses in worst-case conditions and iproper appications are identified and eiinated prior to and during test, production and deivery [3], [4]. WCCA has been accepted by any design copanies as a design verification too. Aso, the ethods described for deveoping a worst-case parts variation database and sensitivity anaysis, as we as extree vaue anaysis (EVA), root-su-square (RSS), and Monte Caro anaysis for soving circuit equations and cobining variabes, have becoe accepted industry standards over the ast two decades [5], [6]. Coparisons of the three WCCA techniques naey EVA, RSS, and Monte Caro anaysis are given in [1]-[4], [7]. The extree vaue anaysis is a nonstatistica ethod for handing the variabes that affect circuit perforance. Its appication in WCCA needs to deterine the atheatica sensitivity of the circuit perforance to the variations in coponent paraeters. Autoated faut detection for anaog circuits is subject to specific probes, such as the unknown deviation in toerances of non-fauty coponent vaues, the ocation of soft fauts and the presence of noise. The techniques for soft faut diagnosis in anaog eectronic circuits are based on the siuation before test, approach where a faut dictionary is a priori generated by coecting signatures of different faut conditions [8]-[1]. Worst-case circuit anaysis can be considered as a step in the soft-faut diagnosis aowing us to find out the bound outputs or perforance attributes of a circuit. A ethod to create a worst-case scenario and to detect the worst case in/ax vaues of the outputs and perforance attributes of the anaog circuits is proposed in this paper. It is based on the fact that if a circuit output and/or perforance specification is onotonic with respect to the changes in a circuit paraeter vaue, then the extree vaues of the response occur at the extree vaues of that paraeter. The onotonicity is identified by the sensitivity band coputation over the paraeter space [8], [9], [1]. Unike EVA, the sensitivity anaysis in our proposed approach is ony used to identify the onotonicity of circuit outputs and perforance attributes with respect to each variabe and not for cobining the variation contributions of the variabes to obtain the extree vaues of the perforance. The paper is organized as foows. The anaog ISSN: Issue 1, Voue 4, October 7

2 Eena Nicuescu, Dorina-Mioara Purcaru and Mariuscristian Nicuescu circuit description in the paraeter space by a poytope is given in Section. In Section 3, the probe foruation of the worst-case circuit anaysis based on aforeentioned circuit description is presented. Then, in Section 4, we show how to ipeent and vaidate the proposed procedure using a standard circuit siuator. Two case studies are presented and discussed using a sa-signa apifier with JFET as exape, in order to iustrate the proposed procedure and to deonstrate its effectiveness. Section 5 concudes the paper. Circuit Description.1 Circuits with syetrica toerances The concept of the circuit design approach and toerance seection, based on the foating and expanding poytope, has been proposed by Bander for an optia design of the noina paraeter vaues of the circuit and toerances [13]. But this concept is appiabe to the circuits with syetrica toerances. Briefy, we resue this theore ooking for the circuit description as foows. Let us consider Φ [Φ 1 Φ... Φ k ] T a vector with k eeents that correspond to the paraeter circuit vaues. This vector has a correspondent point P(Φ 1 Φ... Φ k ) in the k-diensiona space of paraeters. The noina Φ Φ.. Φ corresponds to point P ( 1 k) [ Φ Φ.. Φ ] T Φ 1 k the vector of the paraeter noina vaues) and is associated with a non-negative toerance set ε [ ε ε.. ε ] T 1 k. The toerance region R t, in the paraeter space, is given as R PΦ Φ Φ,i I (1) t { } i i i Φ 1,,...k. where I { } The toerance region i t i Φ R is a k-diensiona convex reguar poytope, centered at P, in the k- diensiona space of paraeters, and εi, i IΦ, is the ength of the i side of this poytope. The poytope has k vertices, which are the extree points of R t. Then, the set of vertices can be defined as R PΦ Φ µ, µ ±,i I. () R { } v i i i i i 1 v The nuber of points contained by i k 1 { P P.. P } i, I { 1, } k Φ R v is k :. These points are indexed by P, I v v,...,. Looking for an optia design of circuit, an accepted region R a is defined and it is deonstrated that if R v R a, then R t R a. According to this theore, ony the poytope vertices ust be tested to be sure that R. t R a. Circuits with asyetrica toerances The operating characteristics of active devices and anaog integrated circuits are often unpredictabe because of their interna geoetric dependence. We can create coponent odes that ore cosey represent actua rea word devices by converting easureent or cataog data into ode paraeters by eans of various toos type paraeter extractor. Usuay, the ode paraeter range of a device ot is not centered at noina vaues of the ode paraeters of a given device sape. The spread of the paraeter vaues due to the anufacturing process as we as the drifts due to aging, and high and ow teperature, are generating sources of asyetrica toerances of the paraeters. Aso, the deviations of the suppy votages can be asyetrica with rapport to their noina vaues. This probe of the anaog circuits with asyetrica toerances becoes easy to sove if the asyetrica toerance case can be reduced to that of the syetrica toerance case. In order to sove this kind probe, a poytope with averagednoina point was defined and its equivaence with the poytope with syetrica toerance was deonstrated. We supposed that the noina point is {Φ i } with i I Φ, the positive toerances ε pi and ε ni are opsided, i.e. there is i IΦ for which ε pi ε pi. Soe toerances can be syetrica. Now, the toerance region is Rt { PΦ i ni Φ i Φ i pi,i IΦ}. (3) The toerance region R t is a k-diensiona poytope with side i of ( ε pi + ε ni ) ength, i IΦ, and with k vertices. We repaced the noina point Φ i of the poytope R t with the averaged-noina point Φ i, where ε pi ni Φ i Φ i +, (4) and we denote the ean vaues of toerances, i.e. the syetrica toerances, ε pi ni ε i for a i IΦ. (5) Then, we deonstrated ISSN: Issue 1, Voue 4, October 7

3 Eena Nicuescu, Dorina-Mioara Purcaru and Mariuscristian Nicuescu PΦ i i Φ i Φ i i, Rt Rt. (6) for a i IΦ Repacing the poytope with asyetrica toerances with its equivaent poytope with syetrica toerances aows us to appy the Bander s theore to an anaog circuit with asyetrica toerances. 3 Worst-Case Circuit Anaysis An anaog circuit can be described in the paraeter space by a poytope, i.e. R t or R t, of which vertices represent the extree vaues of paraeters. A DC or AC or transient anaysis perfored for the vertices of the poytope R t wi produce corresponding vaue bands of the circuit outputs or perforance attributes. The bounds of these vaue bands represent the worst case vaues of the circuit outputs or perforance attributes. Consider a circuit of k paraeters, P [p 1, p,,p k ], where p i ay be the resistance of a resistor, the capacitance of a capacitor, the β transconductance paraeter or W/L ratio of a FET, the V th threshod votage, the λ channe ength oduation coefficient etc. The circuit paraeters have the noina vaues P [p 1, p,,p k ] and the toerances ε [ε p1, ε n1, ε p, ε n, ε pk, ε nk ]. Soe toerances can be syetrica, i.e. ε pj ε nj ε j. Let be the poytope R t with the averaged noina point ε pi ni P i pi + (7) and the toerances ε pi ni ε i, with i 1,, k. (8) The vertices of the set R t { P }, where 1,., k, are denoted as foows: P P 1 3 p p p p p p 1 k 1 k k 1 k, P,.., p p p P k 1 k p p p... 1 k 1 k..., 1 k. (9) We suppose that the behaviour of the circuit is characterized by circuit outputs y [y 1, y,, y ] and n perforance attributes S [s 1, s,, s n ]. The circuit DC outputs Y [Y 1, Y,, Y ] are DC votages of nodes or DC currents through circuit branches that describe the DC operating point of circuit. A transient anaysis yieds the circuit outputs y(t) [y 1 (t), y (t),, y (t)]. A circuit output, for exape the r-th output, or a perforance attribute, for exape the t-th attribute, can be represented as a function of a paraeters, i.e. y r f(p 1, p,,p k ) and s t f(p 1, p,,p k ). (1) Regardess of syetrica or asyetrica toerance case, the circuit outputs and perforance attributes at noina vaues of paraeters wi be: y [y 1 (P ), y (P ),, y (P )], (11) S [s 1 (P ), s (P ),, s n (P )]. (1) Each output and perforance attribute of a circuit is expressed by a vaue or a curve at noina point in paraeter space. Considering the variations in the paraeter space and testing the circuit for the poytope vertices, there wi correspondingy be variation in the circuit outputs and attributes: y( P ) [y 1 ( P ), y ( P ),, y ( P )], (13) S( P ) [s 1 ( P ), s ( P ),, s n ( P )]. (14) The reationships between a circuit output or perforance specification and the paraeters wi becoe a band instead of a singe curve. So, the circuit output y r is bounded by y rin and y rax, the perforance specification s t is bounded by s tin and s tax : y rin y r y rax and s tin s t s tax. (15) If the circuit outputs and/or perforance attributes are onotonic with respect to the changes in vaue of each circuit paraeter, then the extree vaues of the response occur at the extree vaues of that paraeter. The bounds y rin and y rax, s tin and s tax are the worst vaues of circuit outputs and perforance attributes for a worst-case circuit anaysis. For a faut detection probe, the sae bounds deiit the operation of the faut-free circuit. The upper bound of a circuit output can be ooked as stress anaysis resut. The proposed procedure to WCCA can be ipeented in conjunction with a circuit siuator or coputationa environent (MatLab, MathCAD, Matheatica etc.) when an appropriate ode of the device/circuit is avaiabe. First of a, the onotonicity of circuit outputs and/or perforance attributes with respect to circuit paraeters ust be identified by the sensitivity coputation over the paraeter space. As it wi be shown in the foowing, this procedure can be appied to perfor ISSN: Issue 1, Voue 4, October 7

4 Eena Nicuescu, Dorina-Mioara Purcaru and Mariuscristian Nicuescu the worst case anaysis of the anaog circuits with syetrica and/or asyetrica toerances. 4 Case Studies Using a genera-purpose circuit siuator, we wi show how to ipeent and vaidate the proposed procedure. The circuit siuator is used to perfor the DC Operating Point Anaysis and AC Anaysis of the apifier circuit for the poytope vertices. In order to verify the proposed procedure for the worstcase anaysis of an anaog circuit, its resuts wi be copared with those produced by the Worst Case Anaysis aowed by the circuit siuator and an experienta setup. For this purpose, we consider a sa-signa apifier with a NJFET type BFW11. The circuit diagra of the test circuit is shown in Fig. 1. Such a ode has been created for three devices naey: NJFET sape and two NJFETs of which characteristic curves represent the ot dispersion. For the NJFET sape ode, we find out the foowing paraeters: V T (V) - (threshod votage), β (A/V ) (transconductance paraeter) and λ (V 1 ).46 (channe ength oduation coefficient). The rest of ode paraeters hods the vaue set for the NJFET type BFW11 contained by the Master Database of the circuit siuator. The new device with its ode was saved in User Database as a coponent naed BFW11_Mod. The bias circuit was designed to set the DC operating point into the active forward region with the foowing noina coordinates: I DQ 1.5 A, V GSQ -1 V and V DSQ 6 V. Consequenty, we obtain the foowing vaues of resistances: R 1 MΩ, R 6 Ω and R kω. A the passive coponents have an initia toerance of ±5%. We consider a constant teperature (7 o C), for the sake of brevity and a better atch of the easureent and siuation conditions. Fig. 1. Circuit diagra of the sa-signa apifier with JFET type BFW11_Mod Firsty, we consider the circuit with syetrica toerances of two resistors in circuit that eans their initia toerances and perfor the DC and AC worst case anaysis based on the dedicated enu of siuator and our procedure. Secondy, the bounds of the paraeter dispersion of the transistor at constant teperature are taken into account as asyetrica toerances of circuit with rapport to a JFET sape. Our NJFET sape type BFW11 was chosen fro a ot of ten transistors for which the characteristic curves were easured. We extracted the threshod votage, noina saturation current and output conductance of each transistor fro its characteristic curves. Then, converting the easureent data, we created a device ode. 4.1 Worst case anaysis of an anaog circuit with syetrica toerances At this point, the effects of the ode paraeter toerances of the JFET are not considered. Looking for DC and AC worst case anaysis of the given circuit, ony the effects of variations of two resistive paraeters naey R and R 3 on the circuit operating are taken into account. So, the circuit paraeters are as foows: p 1 R, p 1 6 Ω, ε 1 31 Ω; p R 3, p 3.9 kω, ε 195 Ω. Firsty, we exaine the effects of these syetrica toerances on three DC outputs of circuit naey: the votages of drain and source nodes (Y1 V9 and Y V1), and the suppy branch current (Y3 vv1#branch I D ). Then, we verify if the proposed procedure can yied the worst case vaues of the id-band votage gain of the apifier that was chosen herein as perforance attribute. In order to appy and vaidate the proposed procedure, the foowing steps ust be done: 1. The circuit fro the Fig. 1 is siuated for the DC and AC Sensitivity Anaysis in order to verify that the DC outputs and id-band votage gain are onotonic with respect to the changes in paraeter vaues of the two circuit coponents.. The circuit fro the Fig. 1 is siuated for the DC and AC worst case anaysis using the aforeentioned toerances, i.e. ε 1 and ε. The DC worst case anaysis resuts are shown in Tabe 1. The AC worst case anaysis yieds the foowing ISSN: Issue 1, Voue 4, October 7

5 Eena Nicuescu, Dorina-Mioara Purcaru and Mariuscristian Nicuescu resuts: noina vaue of the votage gain of the apifier at f 39.8 khz is equa to 7.5 whie its worst-case vaue is equa to The AC worst case anaysis resut corresponds to R increased to 651 Ω and R kω (unchanged). 3. In order to find out the bounds of the specified circuit outputs, the R and R 3 paraeter vaues are odified according to each vertex of poytope. Then, the new circuit is siuated for perfoing the DC Operating Point Anaysis and AC Anaysis. The poytope with syetrica toerances are four vertices: P ; P ; P ; P. 495 The anaysis resuts concerning the DC circuit outputs are given in Tabe 1 whie those of the perforance attribute as agnitude frequency pots of the votage gain are shown in Fig.. Fig.. Magnitude-frequency pots of votage gain obtained by the proposed procedure. Tabe 1. The resuts of the DC worst case anaysis perfored with the dedicated enu of a circuit siuator, proposed technique and experienta setup. Approach DC WCA enu Poytope vertices Experienta DC circuit outputs Y 1 (V) Y (V) Y 3 (A) (R651Ω; (R651Ω; (R651Ω; R3375Ω) R3375Ω) R3495Ω) P P P P P P P P The three DC outputs of the circuit constructed with the NJFET sape for the four pairs of vaues of resistances R and R 3 are easured. The DC experienta resuts are given in Tabe 1. Aso, the agnitude of votage gain at f 39.8 khz was easured for the noina point and each vertex of the poytope. These AC experienta resuts and their siuated correspondents are shown in Fig. 3 in order to faciitate their coparison. Fig. 3. Magnitudes of votage gain at f 39.8 khz as they are obtained by easureent and proposed procedure. 5. Coparison between the resuts of the worst case anaysis perfored with the dedicated enu of a circuit siuator, proposed technique based on the testing of the poytope vertices, and experienta setup show the foowing: a. The worst case anaysis perfored by eans of the dedicated enu of siuator provides an ony vaue for each DC output of circuit: Y 1w.c.a (V) ISSN: Issue 1, Voue 4, October 7

6 Eena Nicuescu, Dorina-Mioara Purcaru and Mariuscristian Nicuescu , Y w.c.a. (V).9759, Y 3w.c.a. (A) The suppeentary index arks the worst case vaue (w.c.a.) of DC outputs. b. The proposed technique provides a vaue band for each DC output of circuit. The iniu and axiu vaues of each band (boded in Tabe 1) represent the resuts of the worst case anaysis based on testing the circuit for the poytope vertices. The band iits of DC outputs correspond to foowing pairs of vertices of poytope: P and P 3 for outputs Y 1 and Y, and P 1 and P 4 for output Y 3. As it was expected, the band iits of the agnitude of votage gain are obtained for the vertices P and P 3. c. The worst case vaues of the DC circuit outputs suppied by dedicated enu of the siuator (DC WCA) are neary recovered for the P and P 4 vertices of poytope. d. The two vaue bands of the DC outputs and votage gain agnitude, and their bounds fro the experienta resuts are neary the sae as those obtained utiizing the proposed procedure. 4. Worst case anaysis of an anaog circuit with asyetrica toerances In this section, we wi iustrate how to appy the proposed procedure on a circuit with soe asyetrica toerances by eans of a circuit siuator. The asyetrica toerances describe the NJFET ot dispersion with rapport to NJFET sape. In our circuit siuator version, the sensitivity anaysis and consequenty the worst case anaysis with rapport with the ode paraeters of active devices is not possibe. For this purpose, we construct the coponent ode for the two transistors of which characteristic curves represent the ot dispersion. Tabe. Main paraeters of the BFW11_Mod_a and BFW11_Mod_b odes BFW11_Mod_a BFW11_Mod_b V T (V) β (A/V ) λ (V -1 ) Let be BFW11_Mod_a the device for which we extracted fro easured curves the foowing paraeters: V T (V) , I DSS (A) and λ(v -1 ).591. The other transistor naed BFW11_Mod_b is characterized by the paraeter vaues: V T (V) -.385, I DSS (A) and λ(v -1 ).317. The user odes characterizing the ot dispersion are constructed and saved with the sae naes as the devices. The ain paraeters of the two odes are suarized in Tabe. As for previous case, the rest of the ode paraeters have the sae vaues as they of BFW11 ode in Master Database of siuator. Now, we consider the effects of five circuit paraeters on the sae DC outputs and perforance attribute as in previous case. Aong these, we have two coponent paraeters with syetrica toerances, i.e. R and R 3, and three device paraeters with asyetrica toerances, i.e. V T, β and λ. The noina vaue and toerance of these five paraeters are as foows: p 1 R, p 1 (Ω) 6, ε 1 (Ω) 31; p R 3, p (kω) 3.9, ε (Ω) 195; p 3 V T, p 3 (V) -, ε p3 (V).9314, ε n3 (V).385; p 4 β, p 4 (A/V ) , ε p4 (A/V ).48386, ε n4 (A/V ).1564; p 5 λ, p 5 (V -1 ).4645, ε p5 (V -1 ).1311, ε n5 (V -1 ).149. The noina vaues p 3, p 4 and p 5 correspond to the ode paraeter vaues of BFW11_od device. Their asyetrica toerances associated to these noina vaues, i.e. ε p3, ε n3, ε p4, ε n4, ε p5, ε n5, represent the differences between the vaues of the hoony paraeters of BFW11_Mod ode and BFW11_Mod_a ode, respectivey BFW11_Mod_b ode. According to the proposed procedure, the poytope with averaged noina point has 5 vertices corresponding to the five considered paraeters of circuit. The hypothesis of the constant teperature introduces soe constraints concerning the cobination of toerances assigned to the ode paraeters of JFET. This eans that the ean vaues of toerances associated to the two ode paraeters wi be siutaneousy added or subtracted fro the averaged noina vaues for a three paraeters. Consequenty, ony 3 vertices of poytope rest to be tested. Next, we have to cacuate the averaged noina vaues and ean toerances of the paraeters according to (7) and (8). These agebraic cacuations yied the foowing data: p 1 p 1 (Ω) 6, ε 1 ε 1 (Ω) 31; p (kω) 3.9, ε ε (Ω) 195; , ε 3 (V).61995; p p 3 (V) - p 4 (A/V ) , ε 4 (A/V ).313; p 5 (V -1 ).4545, ε 5 (V -1 ).137. Now, appying (9) we can write the vertices of the poytope with averaged noina point as foows: ISSN: Issue 1, Voue 4, October 7

7 Eena Nicuescu, Dorina-Mioara Purcaru and Mariuscristian Nicuescu P ; P ; P ; P. 385 ; P. 385 ; P P 6 P Firsty, using the circuit siuator the onotonicity of DC outputs and votage gain of the apifier with respect to the changes in the three paraeter vaues of the JFET ode was checked. This checking ade separatey for each ode paraeter needs other six user odes of active device derived fro BFW11_Mod ode. For instance, to check up the onotonicity of DC outputs and perforance attribute with respect to threshod votage, one ode has V T (V) , β (A/V ) and λ (V 1 ).46, and other ode has V T (V) -.385, β (A/V ) and λ (V 1 ).46. The rest of paraeters have their noina vaues. Siuating the two new circuits one obtains the necessary data to cacuate the DC outputs and votage gain sensitivities over the paraeter range. The resuts of these anayses and sensitivity cacuations show that the DC outputs and votage gain of the circuit are onotonic with respect to ode paraeters of JFET. Next, to find out the DC worst case outputs of the circuit, we have to run eight ties the DC Operating Point Anaysis and AC Anaysis fro the circuit siuator for the eight specified vertices. Each poytope vertex eans a particuar circuit concerning the active device, i.e. either BFW11_Mod_a or BFW11_Mod_b, and extree vaues of the two resistances. The siuation resuts concerning the DC circuit outputs are shown in Tabe 3 whie those of the votage gain are shown in Fig. 4. The iniu and axiu vaues of each band (boded in Tabe 3) represent the resuts of the worst case anaysis based on the poytope vertex test. The paraeter vaue dispersion of active device highighted by the differences of the band bounds of each DC outputs of the circuits in Tabe 1 and 3 has a critica ipact on eeting the design specifications. Tabe 3. The resuts of the DC worst case anaysis based on the poytope vertex test. Poytope DC circuit outputs vertices Y 1 (V) Y (V) Y 3 (A) P P P P P P P P Fig. 4. Magnitude-frequency pots of votage gain obtained by the proposed procedure. The resuts of the worst case anaysis perfored with the proposed technique and experienta setup concerning the votage gain at f 39.8 khz are aso given in Fig. 5. The resuts obtained by the proposed procedure are neary the sae as the experienta resuts. This eans that the proposed procedure can be an aternative eans to perfor the worst case anaysis of an anaog circuit. ISSN: Issue 1, Voue 4, October 7

8 Eena Nicuescu, Dorina-Mioara Purcaru and Mariuscristian Nicuescu Fig. 5. Magnitudes of votage gain at f 39.8 khz as they are obtained by easureent and proposed procedure. 5 Concusion In this paper, a procedure to perfor the worst case anaysis of an anaog circuit with syetrica and/or asyetrica toerance is presented. The worst case vaues of the circuit outputs or perforance attributes are obtained by perforing DC or AC or transient anaysis for the extree vaues of paraeters given by the vertices of a poytope. The nuber of vertices increases with the nuber of circuit paraeters taken into account. When the worst case anaysis is perfored in conjunction with a circuit siuator for a arge nuber of paraeters such a procedure becoes heavy. Each poytope vertex requires the odification and resiuation of the circuit. This drawback disappears when the procedure is appied in conjunction with a coputationa environent. Likewise EVA, our proposed approach to worstcase circuit anaysis is the easiest technique to use and yieds the ost readiy obtainabe estiates worst-case circuit perforance. The proposed procedure is different to extree vaue anaysis (EVA), because it is not based on the sensitivity anaysis to copute the extree vaues of circuit outputs and/or perforance attributes. Aso, our proposed approach yieds an in-depth understanding of a design due to the forat of the required inputs that consists of the worst-case part variation iits for a coponents. References: [1] W. M. Sith, Worst Case Circuit Anaysis Handbooks (Voues 1 5), Design and Evauation Inc., [] W. M. Sith, Worst-case circuit anaysis - an overview (eectronic parts/circuits toerance anaysis), Proceedings of Internationa Syposiu on Product Quaity and Integrity, pp , [3] B. Vinnakota, Anaog and Mixed-Signa Test, Prentice Ha, [4] R. R. Boyd, Toerance Anaysis of Eectronic Circuit Using Mathcad, CRC Press LLC,. [5] [6] W. K. A-Assadi and P. Chandrasekhar, Issues in Testing Anaog Devices, Proc. of the 1 th NASA Syposiu on VLSI Design, 5. [7] A. Brockschidt, R. Carpenter, and F. Shi, Guideines and exapes for perforing worst case anaysis, Proceedings of the IEEE Appied Power Eectronics Conference and Exposition, APEC 99, Vo., pp , [8] M. W. Tian and C.-J.R. Shi, Worst-case anaysis of inear anaog circuits using sensitivity bands, IEEE Transactions on Circuits and Systes: Fundaenta Theory and Appications, vo. 47, no. 8,, pp [9] M. Worsan and M.W.T. Wong, Non-inear anaog circuit faut diagnosis with arge change sensitivity, Internationa Journa of Circuit Theory and Appications,No. 8,, pp [1] C. Marcantonio and A. Fort,Soft Faut Detection and Isoation in Anaog Circuits: Soe Resuts and a Coparison Between a Fuzzy Approach and Radia Basis Function Networks, IEEE Transactions on Instruentation and Measureent, Vo. 51, No.,, pp [11] S.-J. Chang, C.-L. Lee, and J. E. Chen, Structure-based specification-constrained Test frequency generation for Linear Anaog Circuits, Journa of Inforation Science and Engineering, Vo. 19, 3, pp [1] V. C. Prasad and N. C. S. Babu, Seection of test nodes for anaog faut diagnosis in dictionary approach. IEEE Transactions on Instruentation and Measureent, Vo. 49,, pp [13] J. W. Bander, Worst Case Network Toerance Optiization, IEEE Transactions on Microwave Theory, Vo. MTT-3, Aug. 1975, pp ISSN: Issue 1, Voue 4, October 7