74HC259-Q100; 74HCT259-Q100

Transcription

1 Rev. 30 July 202 Product data sheet. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7. The are high-speed es designed for general-purpose storage applications in digital systems. They are multifunctional devices capable of storing single-line data in eight addressable latches and providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7). They also incorporate an active LOW common reset (MR) for resetting all latches as well as an active LOW enable input (LE). The has four modes of operation: ddressable latch mode, in this mode data on the data line (D) is written into the addressed latch. The addressed latch follows the data input with all non-addressed latches remaining in their previous states. Memory mode, in this mode all latches remain in their previous states and are unaffected by the data or address inputs. Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows the state of the data input (D) with all other outputs in the LOW state. Reset mode, in this mode all outputs are LOW and unaffected by the address inputs (0 to 2) and data input (D). When operating the as an address latch, changing more than one address bit could impose a transient wrong address. Therefore, this should only be done while in the Memory mode. This product has been qualified to the utomotive Electronics Council (EC) standard Q00 (Grade ) and is suitable for use in automotive applications. 2. Features and benefits utomotive product qualification in accordance with EC-Q00 (Grade ) Specified from 40 C to +85 C and from 40 C to +25 C Combined demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input

2 3. Ordering information Useful as a 3-to-8 active HIGH decoder Input levels: For 74HC259-Q00: CMOS level For 74HCT259-Q00: TTL level ESD protection: MIL-STD-883, method 305 exceeds 2000 V HBM JESD22-4F exceeds 2000 V MM JESD22-5- exceeds 200 V (C = 200 pf, R = 0 ) Multiple package options Table. Ordering information Type number Package Temperature Name Description Version range 74HC259D-Q00 40 C to +25 C SO6 plastic small outline package; 6 leads; SOT09-74HCT259D-Q00 74HC259PW-Q00 40 C to +25 C TSSOP6 body width 3.9 mm plastic thin shrink small outline package; 6 leads; SOT403-74HCT259PW-Q00 body width 4.4 mm 74HC259BQ-Q00 40 C to +25 C DHVQFN6 plastic dual in-line compatible thermal enhanced very SOT763-74HCT259BQ-Q00 thin quad flat package; no leads; 6 terminals; body mm 4. Functional diagram Z9 G8 G D LE Q0 Q Q2 Q3 Q4 Q5 Q6 Q7 MR mna DX 0 G ,0D C0 8R mna Fig. Logic symbol Fig 2. IEC logic symbol Product data sheet Rev. 30 July of 20

3 Q0 4 0 Q of-8 DECODER Q2 Q LTCHES Q4 9 4 LE Q MR D Q6 Q7 2 mna57 Fig 3. Functional diagram 5. Pinning information 5. Pinning 74HC259-Q00 74HCT259-Q00 74HC259-Q00 74HCT259-Q00 terminal index area 0 VCC MR LE 2 5 MR Q0 4 3 D 2 Q0 Q Q LE D Q7 Q6 Q Q2 Q () Q7 Q6 Q5 Q Q5 Q4 Q4 aaa aaa Transparent top view () The die substrate is attached to this pad using conductive die attach material. It cannot be used as supply pin or input. Fig 4. Pin configuration (SO6 and TSSOP6) Fig 5. Pin configuration (DHVQFN6) Product data sheet Rev. 30 July of 20

4 5.2 Pin description Table 2. Pin description Symbol Pin Description 0,, 2, 2, 3 address input Q0, Q, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 0,, 2 latch output 8 ground (0 V) D 3 data input LE 4 latch enable input (active LOW) MR 5 conditional reset input (active LOW) 6 supply voltage 6. Functional description Table 3. Function table [] Operating mode Input Output MR LE D 0 2 Q0 Q Q2 Q3 Q4 Q5 Q6 Q7 Reset (clear) L H X X X X L L L L L L L L Demultiplexer L L d L L L Q = d L L L L L L L (active HIGH 8-channel) L L d H L L L Q = d L L L L L L decoder (when D = H) L L d L H L L L Q = d L L L L L L L d H H L L L L Q = d L L L L L L d L L H L L L L Q = d L L L L L d H L H L L L L L Q = d L L L L d L H H L L L L L L Q = d L L L d H H H L L L L L L L Q = d Memory (no action) H H X X X X q 0 q q 2 q 3 q 4 q 5 q 6 q 7 ddressable latch H L d L L L Q = d q q 2 q 3 q 4 q 5 q 6 q 7 H L d H L L q 0 Q=d q 2 q 3 q 4 q 5 q 6 q 7 H L d L H L q 0 q Q=d q 3 q 4 q 5 q 6 q 7 H L d H H L q 0 q q 2 Q=d q 4 q 5 q 6 q 7 H L d L L H q 0 q q 2 q 3 Q=d q 5 q 6 q 7 H L d H L H q 0 q q 2 q 3 q 4 Q=d q 6 q 7 H L d L H H q 0 q q 2 q 3 q 4 q 5 Q=d q 7 H L d H H H q 0 q q 2 q 3 q 4 q 5 q 6 Q=d [] H = HIGH voltage level; L = LOW voltage level; X = don t care; d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. Product data sheet Rev. 30 July of 20

5 Table 4. Operating mode select table [] LE MR Mode L H ddressable latch mode H H Memory mode L L Demultiplexer mode H L Reset mode [] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to (ground = 0 V). Symbol Parameter Conditions Min Max Unit supply voltage V I IK input clamping current V I < 0.5 V or V I > +0.5 V [] - 20 m I OK output clamping current V O < 0.5 V or V O > V [] - 20 m I O output current V O = 0.5 V to +0.5V - 25 m I CC supply current m I ground current 70 - m T stg storage temperature C P tot total power dissipation [2] mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO6 package: P tot derates linearly with 8 mw/k above 70 C. For TSSOP6 package: P tot derates linearly with 5.5 mw/k above 60 C. For DHVQFN6 package: P tot derates linearly with 4.5 mw/k above 60 C. Product data sheet Rev. 30 July of 20

6 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to (ground = 0 V) Symbol Parameter Conditions 74HC259-Q00 74HCT259-Q00 Unit Min Typ Max Min Typ Max supply voltage V V I input voltage V V O output voltage V T amb ambient temperature C t/ V input transition rise and fall rate = 2.0 V ns/v = 4.5 V ns/v = 6.0 V ns/v 9. Static characteristics Table 7. Static characteristics t recommended operating conditions; voltages are referenced to (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ Max Min Max Min Max 74HC259-Q00 V IH HIGH-level = 2.0 V V input voltage = 4.5 V V = 6.0 V V V IL LOW-level = 2.0 V V input voltage = 4.5 V V = 6.0 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 20 ; = 2.0 V V I O = 20 ; = 4.5 V V I O = 20 ; = 6.0 V V I O = 4.0 m; = 4.5 V V I O = 5.2 m; = 6.0 V V V OL LOW-level output voltage V I = V IH or V IL I O = 20 ; = 2.0 V V I O = 20 ; = 4.5 V V I O = 20 ; = 6.0 V V I O = 4.0 m; = 4.5 V V I O = 5.2 m; = 6.0 V V I I input leakage V I = or ; current =6.0V I CC supply current V I = or ; I O =0; =6.0V Product data sheet Rev. 30 July of 20

7 Table 7. Static characteristics continued t recommended operating conditions; voltages are referenced to (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ Max Min Max Min Max C I input capacitance pf 74HCT259-Q00 V IH HIGH-level = 4.5 V to 5.5 V V input voltage V IL LOW-level = 4.5 V to 5.5 V V input voltage V OH HIGH-level output voltage V I = V IH or V IL ; = 4.5 V I O = V I O = 4.0 m V V OL LOW-level output voltage V I = V IH or V IL ; = 4.5 V I O = 20 ; = 4.5 V V I O = 5.2 m; = 6.0 V V I I input leakage V I = or ; current =5.5V I CC supply current V I = or ; I O =0; =5.5V I CC C I additional supply current input capacitance V I = 2. V; I O =0; other inputs at or ; = 4.5 V to 5.5 V pin n, LE pin D pin MR pf Product data sheet Rev. 30 July of 20

8 0. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to (ground = 0 V); for test circuit see Figure 2. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max Min Max 74HC259-Q00 t pd propagation D to Qn; see Figure 6 [2] delay = 2.0 V ns = 4.5 V ns = 5.0 V; C L =5pF ns = 6.0 V ns n to Qn; see Figure 7 [2] = 2.0 V ns = 4.5 V ns = 5.0 V; C L =5pF ns = 6.0 V ns LE to Qn; see Figure 8 [2] = 2.0 V ns = 4.5 V ns = 5.0 V; C L =5pF ns = 6.0 V ns t PHL HIGH to LOW MR to Qn; see Figure 9 propagation = 2.0 V ns delay = 4.5 V ns = 5.0 V; C L =5pF ns = 6.0 V ns t t transition time see Figure 8 [3] = 2.0 V ns = 4.5 V ns = 6.0 V ns t W pulse width LE HIGH or LOW; see Figure 8 = 2.0 V ns = 4.5 V ns = 6.0 V ns MR LOW; see Figure 9 = 2.0 V ns = 4.5 V ns = 6.0 V ns Product data sheet Rev. 30 July of 20

9 Table 8. Dynamic characteristics continued Voltages are referenced to (ground = 0 V); for test circuit see Figure 2. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max Min Max t su set-up time D, n to LE; see Figure 0 and Figure t h hold time D to LE; see Figure 0 and Figure C PD power dissipation capacitance 74HCT259-Q00 t pd propagation delay = 2.0 V ns = 4.5 V ns = 6.0 V ns = 2.0 V ns = 4.5 V ns = 6.0 V ns n to LE; see Figure 0 and Figure = 2.0 V ns = 4.5 V ns = 6.0 V ns f i = MHz; [4] pf V I =to D to Qn; see Figure 6 [2] = 4.5 V ns = 5.0 V; C L =5pF ns n to Qn; see Figure 7 [2] = 4.5 V ns = 5.0 V; C L =5pF ns LE to Qn; see Figure 8 [2] = 4.5 V ns = 5.0 V; C L =5pF ns t PHL HIGH to LOW MR to Qn; see Figure 9 propagation = 4.5 V ns delay = 5.0 V; C L =5pF ns t t transition time see Figure 8 [3] = 4.5 V ns t W pulse width LE HIGH or LOW; see Figure 8 = 4.5 V ns MR LOW; see Figure 9 = 4.5 V ns Product data sheet Rev. 30 July of 20

10 Table 8. Dynamic characteristics continued Voltages are referenced to (ground = 0 V); for test circuit see Figure 2. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max Min Max t su set-up time D, n to LE; see Figure 0 and Figure = 4.5 V ns t h hold time D to LE; see Figure 0 and Figure = 4.5 V ns n to LE; see Figure 0 and Figure = 4.5 V ns C PD power dissipation capacitance [] Typical values are measured at nominal supply voltage ( = 3.3 V and =5.0V). [2] t pd is the same as t PLH and t PHL. [3] t t is the same as t THL and t TLH. [4] C PD is used to determine the dynamic power dissipation (P D in W). P D =C PD 2 f i N+ (C L 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of the outputs.. Waveforms f i = MHz; V I =to.5 V [4] pf D input t PHL t PLH V OH Qn output V OL 00aah23 Fig 6. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. Data input to output propagation delays Product data sheet Rev. 30 July of 20

11 n input t PHL t PLH V OH Qn output V OL 00aah22 Fig 7. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. ddress input to output propagation delays D input LE input Qn output V OH V OL t W t PHL V Y V X t THL t PLH t TLH 00aaj446 Fig 8. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. Enable input to output propagation delays and pulse width MR input V OH t PHL t W Qn output V OL 00aah24 Fig 9. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. Master reset input to output propagation delays Product data sheet Rev. 30 July 202 of 20

12 LE input t su t su t h t h D input V OH Qn output Q = D Q = D V OL 00aah25 Fig 0. Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. V OL and V OH are typical voltage output levels that occur with the output load. Data input to latch enable input set-up and hold times n input DDRESS STBLE t su t h LE input 00aah26 Fig. Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. V OL and V OH are typical voltage output levels that occur with the output load. ddress input to latch enable input set-up and hold times Table 9. Measurement points Type Input Output V X V Y 74HC259-Q HCT259-Q00.3 V.3 V Product data sheet Rev. 30 July of 20

13 V I negative pulse 0 V 90 % 0 % t W t f t r t r t f V I positive pulse 0 V 0 % 90 % t W G VI DUT VO RL S open RT CL 00aad983 Fig 2. Test data is given in Table 0. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S = Test selection switch Load circuit for measuring switching times Table 0. Test data Type Input Load S position V I t r, t f C L R L t PHL, t PLH 74HC259-Q00 6ns 5pF, 50 pf k open 74HCT259-Q00 3 V 6 ns 5 pf, 50 pf k open Product data sheet Rev. 30 July of 20

14 2. Package outline SO6: plastic small outline package; 6 leads; body width 3.9 mm SOT09- D E X c y H E v M Z 6 9 Q 2 ( ) 3 pin index θ L p 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D () E () e H () E L L p Q v w y Z Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT09-076E07 MS Fig 3. Package outline SOT09- (SO6) Product data sheet Rev. 30 July of 20

15 TSSOP6: plastic thin shrink small outline package; 6 leads; body width 4.4 mm SOT403- D E X c y H E v M Z 6 9 pin index 2 Q ( ) 3 θ 8 e b p w M detail X L p L mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT403- MO-53 EUROPEN PROJECTION ISSUE DTE Fig 4. Package outline SOT403- (TSSOP6) Product data sheet Rev. 30 July of 20

16 DHVQFN6: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 6 terminals; body 2.5 x 3.5 x 0.85 mm SOT763- D B E c terminal index area detail X terminal index area e e b 2 7 v M w M C C B y C C y L 8 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () Eh e e L v w y y mm Note. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 5. Package outline SOT763- (DHVQFN6) Product data sheet Rev. 30 July of 20

17 3. bbreviations Table. cronym CDM CMOS DUT ESD HBM LSTTL MM TTL bbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic 4. Revision history Table 2. Revision history Document ID Release date Data sheet status Change notice Supersedes v Product data sheet - - Product data sheet Rev. 30 July of 20

18 5. Legal information 5. Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 5.3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. Product data sheet Rev. 30 July of 20

19 No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Product data sheet Rev. 30 July of 20

20 7. Contents General description Features and benefits Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Date of release: 30 July 202