CHARACTERIZATION OF THERMAL INTERFACE MATERIALS TO SUPPORT THERMAL SIMULATION

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1 Nice, Côte Azur, France, 7-9 September 006 CHARACTERIZATION OF THERMAL INTERFACE MATERIALS TO SUPPORT THERMAL SIMULATION Ralph Schacht 1, Daniel May 1, Bernhar Wunerle 1, Olaf Wittler, Astri Gollhart 1, Bern Michel 1, Herbert Reichl 1 Fraunhofer Institut für Zuverlässigeit un Mirointegration, Technische Universität Berlin, Forschungsschwerpunt Technologien er Miroperipheri, Gustav-Meyer lee 5, Berlin, Germany ralph.schacht@izm.fraunhofer.e ABSTRACT In this paper new characterization equipment for thermal interface materials is presente. Thermal management of electronic proucts relies on the effective issipation of heat. This can be achieve by the optimization of the system esign with the help of simulation methos. The precision of these moels relies also on the use material ata. For the etermination of this ata an experimental set-up for a static measurement is presente, which evaluates thermal conuctivity an interface resistance of thermal interface materials (e.g. ahesive, soler, pas, or pastes). A qualitative structure-property correlation is propose taing into account particle size, filler content an voi formation at the interface base on high resolution FIB imaging. The paper gives an overview over the set-up an the measurement technique an iscusses experimental an simulation results. 1. INTRODUCTION It is common practice for high power applications to assemble power evices as bare ies in chip on boar technique or to use flip chip assemblies with a irectly mounte copper or aluminum heat sin. The thermal resistance ( ) of the thermal interface material () is the bottlenec of the thermal heat flow from the active evice junction to the cooler. l the more important is the fact of strongly localize hot spots, as heat spreaing requires better thermal interface materials as just heattransfer [1, ]. If possible, it is useful an common to reuce the thicness of the thermal interface material. But for thinner thermal interface materials the thermal interface resistance (between the silicon an the thermal interface material (0,Si- ) as well as between the thermal interface material an the cooler material (0,CM- )) is no longer negligible [3, 4]. Therefore it is essential to account for this effect in the measurement set-up. In the system esign process thermal simulation is use among other tools to select the thermal interface material to fin the optimum situation. To buil up the simulation moel an get a suitable solution it is necessary to now the accurate geometry an material parameters. As, the tren is towars thinner thermal interface materials, the thermal interface resistances shoul be consiere in the thermal simulation moel. There are several stanarize test methos (ASTM E 15-99, ASTM E , ASTM E , DIN V 5446) as well as in-house-built an maret going set-ups to etermine the thermal resistance [5]. The most wiely use methos are to place the thermal interface material between two plates, heating the top plate an cooling the bottom plate [6, 7, 8] or to use photo or laser flash set-ups [9]. In the paper ifferent thermal interface materials (ahesives) are characterize varying ifferent measurement an material parameters. Thus the thermal conuctivity of the materials an the interface resistance is characterize. It is shown that the interface material can become a ey issue for the thermal management of ynamically loae evices. On this example a moel with statically etermine material ata is valiate an iscusse in simulation an experiment.. THERMAL INTERFACE MATERIAL Thermal Interface Materials as paste, pas, gels, ahesives or solers are use to fulfill the gap or tilt between to surfaces to optimize the thermal path between them. In microelectronics applications the ajacent materials are usually silicon an the heat sin materials or Cu. Figure 1 shows on the left han sie a typical power assembly application e.g. for a reverse-sie coole power evice in flip-chip technology. Heat Sin Microprocessor/ Power Device Heat Path Fig. 1: Thermal interface material is use to fulfill the gap or tilt between to surfaces. For example, on the left a typical reversesie cooling power assembly application is given.

2 Ralph Schacht, Daniel May, Bernhar Wunerle, Olaf Wittler, Astri Gollhart, Bern Michel,... As mentione above thinner layers are aime to minimize the thermal resistance. It is nown that the thermal resistance cannot be infinitely ecrease by maing it thinner. The observe behavior is nown as a bounary effect in the interface between e.g. substrate an as well as between an heat sin material. This thermal interface resistances 0,i has to be ae to the bul resistance of the R an leas to an effective thermal resistance R eff. R = R + R + R (Eq. 1) eff th0,1 th0, 3. TEST SET-UP 3.1. Structure The iea to evelop a new in of set-up was to realize test conitions as they occur in real assemblies. That means using the same surface materials an assembly technology as in the real evice instea of pellets mae of ahesives (or soler). Figure shows the schematic set-up for the new metho. As in microelectronic assemblies usually silicon surface are assemble on aluminum or copper heat sin material a thermal test ie for heating an temperature measuring is use [10]. Therefore a thermal test ie was chosen an assemble in flip-chip technology. Using flip-chip technology, it has - to be assure that the ie surface is flat, what is especially important for grease characterization. This can be achieve uner certain circumstances, as ue to thermal mismatch a flip-chip is always slightly curve. The is instea of a irect mounting on the col plate, mounte on an test socet ( or Cu). The test socet is at least place on the heat sin. The avantage using a test socet is that the heat flow through the coul be measure. Another avantage is that the socet is not fixe on the heat sin, so specimens can be easily change. An while the socet is mae out of an inexpensive, maret going, low tolerance material which can be use as reference resistor. Due to its being inexpensive, it nee not be reuse an can be use for interface characterization by estructive analysis methos lie cross sections or FIB-milling. Here also the exact thicness can be etermine. It therefore has the versatility to be use for characterization of ahesive or soler s without amaging the test-set-up. As in figure 3 is shown for this application a 3x3 thermal test-ie chip is use to supply the heat an to measure the chip temperature. The thermal test chip is mounte in flip-chip technology on a FR-4 boar. To guarantee a small war-page over the test chip a low temperature process uring curing is use. The chip has an uner-fill to eep thermo-mechanical stress from the soler bumps an to stabilize the assembly uring test. Figure 3 an 4 show a schematic of such a thermal test ie with its implante heat resistance an ioe, the test chip assembly an the electrical interconnection. 5mm F = const. Thermal Test Die (Flip Chip Assembly) Si TDie 0mm Test Socet ( temperature measurement points) T 1 Fig. 3: Thermal test chip assembly an electrical interconnection schematic Implante heat resistance Dioe Heat Sin Water cooler Fig. : Principle schematic for new test set-up T Fig. 4: Thermal test ie structure Determining the chip temperature T J the temperatureepening physical effect of the forwar voltage, uring a constant ioe current, is use (equation ). K T I F, Dioe T ~ U F, Dioe = ln ( I F, Dioe = const (Eq. ) e I S Using a linear fit through the measure voltage/temperature relations a numerical equation can be foun to etermine the junction temperature. For each thermal test chip its own characteristic has to be foun. Fig. 5: New test set-up Force gauge Electrical connection Thermal test chip Thermo-couples Test socet Heat sin A Eitions/THERMINIC 006 -page- ISBN:

3 Ralph Schacht, Daniel May, Bernhar Wunerle, Olaf Wittler, Astri Gollhart, Bern Michel,... The temperatures unerneath the surface in the test socet (T 1 ) an at the bottom of the socet (T ) are measure by Ni-Cr thermo-couples (figure 5). Therefore holes are rille into the socet close uner the surface to the an the bottom of the socet. The thermocouples are assemble with heat conuction paste. The measurement ata generation is fully computercontrolle. Following the right part of equation 5, a escribes the thermal conuctivity normalize to the use area an b the thermal interface resistances (equation 6): a = 10 1, b = ( 0,1 + Rth0, ) (Eq. 6) A 3.. Principle Usually the etermination of the heat flow through a thermal interface material is assume to be equal to the electrical power loss. But there is a parallel heat flow through the electrical connection bloc. Raiation an free convection coul be neglecte as shown in section 3.3. Using the presente new assembly structure the real heat flow through the thermal interface material can be etermine. Figure 6 erives the thermal equivalent circuit for the set-up. Pv [K/W] ,0 0, 0,4 0,6 0,8 1,0 [mm] el. contact & mounting force raiation R 0 (Si) () R 0 () (Si) () T1 () T TDie Fig. 6: Schematic of thermal equivalent circuit for test socet an test chip. Measuring the temperature ifference (T 1 -T ) in a physically nown test socet the heat flow can be calculate (equation 3). T1 T = ; Rth socet = (Eq. 3), R socet A Knowing the heat flow through the test socet an the physical quantities of the thermal test chip, the effective thermal resistance R eff for the thermal interface material incluing the thermal interface resistance R 0 can be obtaine (equation 4). TJ T1 R eff = R (Eq. 4) Chip Having several measurements of the same with ifferent thicness the thermal conuctivity an sum of both thermal interface resistances (0,Si- an 0,- ) can be etermine by numerical linear fit (figure 7). convection ( ) = + ( Rth + Rth ) = a + b eff 0,1 0, A R (Eq. 5) Fig. 7: Numerical linear fit through several measurements points of the same with ifferent thicness leas to the thermal conuctivity of the ( ) an the sum of both thermal interface resistances (0,Si- an 0,- ). Knowing at least the values of the geometrical thicness an area, the thicness epening thermal conuctivity of the thermal interface material can be obtaine (equation 7). ( ) = ( R eff ( ) ( R th0,1 + R th0, )) A (Eq 7) 3.3. Failure estimation an accuracy To give a failure estimation an a accuracy for the setup a thermal simulation was investigate an a evaluation of measuring failure was mae [11]. The analysis has shown that the measurement error lies uner 6%, when the temperature ifference between T Chip an T 1 (ΔT Chip-1 ) is 5 K. For example, a thicness of 50 µm results in a maximum measurable (effective) thermal conuctivity of 10 W/mK. This is sufficient as most maret-going ahesives o have values of eff (=50µm) 0,5-1,5 W/mK Measurements 4. RESULTS Figure 8 shows the characteristics of four -fille ahesives base on epoxy or moifie epoxy bul material. A Eitions/THERMINIC 006 -page- ISBN:

4 Ralph Schacht, Daniel May, Bernhar Wunerle, Olaf Wittler, Astri Gollhart, Bern Michel,... R eff (K/W) 1,6 1,4 1, 1,0 0,8 0,6 A B C D Ahesive C 0,4 0, Si 0, (μm) Fig. 8: Characteristic curves of four - fille ahesives are use to etermine its thermal conuctivities an thermal interface resistances. As erive above, the curves can be use to etermine the thermal conuctivities, the thermal interface resistances an the interface heat transfer coefficient respectively. Therefore three specimens of ifferent thicness for each ahesive were analyze. After testing, cross-sections were mae to measure the exact thicness of each specimen (figure 9). Fig. 10: Cross-section of layer Figure 11 shows a cut-out of figure 10 where in the bounary surface region pore structures woul observe. Ahesive C Si a) b) Fig. 9: Cross section of test chip assemble on test socet to etermine the thicness. After numerical linear fitting, thermal conuctivities an interface heat transfer coefficients coul be etermine (table 1). Tab. 1: Determine parameters for investigate fille Epoxy ahesives (A = 11,8 * 11,8 mm²). eff * 0 * A Investigate ahesive types (W/mK) ( = 100µm) (W/mK) (K cm²/ W) A 1,9 3,8 0,4 B,5 1,9 0,07 C 1,4,7 0,31 D 1,3 1,3 0, Metallurgy To get a better unerstaning of the structure of the an its thermal interface resistance, the crosssections were analyze by SEM (figure 10). Fig. 11: in the bounary surface region between the silicon chip an the -fille copolymer. To have a better view into the epth of the interface, the bounary surface regions were analyse by focus ion beam (FIB) an SEM. Ahesive A Filling Gag Ahesive B Ahesive C Filling Gag Ahesive D Fig. 1: Comparison of cross-sections for -Si bounary section from -fille ahesives. Filling Gag Figure 1 compares cross-sections an FIB millings into the - bounary sections of the four thermal interface materials. A Eitions/THERMINIC 006 -page- ISBN:

5 Ralph Schacht, Daniel May, Bernhar Wunerle, Olaf Wittler, Astri Gollhart, Bern Michel,... It can be seen that there are ifferent filling graes an that the particles of ahesive A an C have a larger size then those of B an D. s in the ahesive B coul be observe mainly in the interface region. The other interfaces show a goo connectivity. There also can be seen filling gaps between the particles in the bul material Simulation To tae into consieration of the influence of thermal interface resistance, a transient thermal simulation was one. Therefore the region between test chip surface an test socet was moele using the effective conuctivity eff an using only the etermine conuctivity (without consiering the thermal interface resistances) as given in table 1. Fig. 13: Moel for transient simulation. Figure 13 shows the moel structure. The chip is assemble on a FR-4 PCB. The ie attach area is fille with thermal via s. Table gives the moel parameters. Tab. : Moel parameters for investigate transient thermal simulation. A Chip [mm²]] Chip PCB CU th. via count ia Via 8 x T ( C) fille epoxy ahesive C eff P V = 80W = 100 µm 0 0,0 0,1 0, 0,3 0,4 0,5 0,6 0,7 t (s) Fig. 14: Transient temperature behaviour in respect with an without consiering the thermal interface resistances. Figure 14 compares the transient behavior. As expecte, the observe temperature rise for the solution of the moel, consiering only the thermal conuctivity, is much less than consiering the effective conuctivity. That means that in real systems the junction temperature will be much higher as through simulation expecte. This cause an over heating of the evice an in the en its amage. 5. DISCUSSION OF RESULTS The metallurgical results have shown that it is necessary to observe the an its bounary regions. The particles of ahesives B an D have for instance a closer contact between each other as the particles of A or C which results in a higher thermal bul conuctivity (c.f. figure 8). The observe filling gaps an pores in the bul material coul be a reason for the ifference of thermal interface resistances for the investigate four ahesives. Especially if pores are close to the interface region, as seen in figure 11, the thermal interface resistance will be influence. This is in corresponence with the measure results. A an C have larger particles as B an D an they show a better thermal conuctivity because of its larger particle surface, which leas to less interfaces between the particles over the thicness thus enhancing heat transfer. On the other han larger particles have an influence on the thermal interface resistance as they seem to promote the evelopment of pores in the interface region an gaps in the bul material. Oppose to that, B has small particles which shows a goo filling grae even in the interface region. In this case the thermal conuctivity ecreases (ue to a higher number of interfaces between the filler particles) but the thermal interface resistance becomes negligible. D have very flat an long particles which show a goo accommoation to the interface an therefore a low thermal interface resistance. Because of the oblong particles the number of interfaces between the particles in the polymer matrix increases an for that the thermal conuctivity ecreases, too. Equations 10 an 11 escribe the behaviour of effective thermal conuctivity eff in respect to thicness. It can be conclue that for thin layers the effective thermal conuctivity is a function of both the thermal interface resistances 0,1 + 0,1 an the bul conuctivity. e ff ( ) = + ( Rth0,1 + Rth0, ) A (Eq 10) A Eitions/THERMINIC 006 -page- ISBN:

6 Ralph Schacht, Daniel May, Bernhar Wunerle, Olaf Wittler, Astri Gollhart, Bern Michel,... For thic layers the effective thermal conuctivity follows from the bul resistance. e ff ( ) = (Eq 11) Figure 15 shows for the investigate s the mentione behaviour. eff (W/mK) 1 0, (μm) Fig. 15: Behavior of effective thermal conuctivity in respect to the thicness for the investigate -fille ahesives. It can be recognize that the ahesive A has for thicer layers a better effective thermal conuctivity as C,B an D. But having a thermal esign using a thin layers e.g. the investigate ahesive B or D shoul be taen. The transient thermal simulation has shown that it is necessary to tae the thermal interface resistance into consieration. Otherwise it causes overheating of the evice. Even after 00ms the temperature for the moel that consiers eff rises up to more than 50% of the temperature of the base moel. 6. CONCLUSION A new test set-up to characterize thermal interface materials was investigate. The novelty is that the set-up allows to measure all classes of s (incl. soler an ahesive) uner real assembly conitions. The avantages are: High versatility (all ). A rapi test metho using a test socet. An inexpensive metho using stanarize reference test socet material with narrow tolerances. Obtaining all relevant of information concerning: thicness, force, eff,, 0,i thicness etermination by crosssectioning. Design allows easy analysis by FIB an/or SEM A C B D Flip-chip assembly for thermal test chip use as to assure flatness of ie (important for greases) Test uses surfaces as in real evices More accuracy is possible to improve temperature measurement while using thermocouples with less measurement errors. The etermination of thermal interface resistance an thermal conuctivity was exemplifie for four ahesives. The Structure of the ahesive was analyze by FIB an SEM. It was foun, that there is a structure-property correlation with respect to thermal properties. Vois, particle size an filler content coul be shown to influence interface resistance an bul conuctivity an was explaine accoringly. so the influence of the thermal interface resistance was shown by thermal simulation. 7. REFERENCES [1] S.V. Garimella, Y.K. Joshi, A. Bar-Cohen, R. Mahajan, K.C. Toh, V.P. Baelmans, J. Lohan, B. Sammaia, an F. Anros. Thermal challenges in next generation electronic systems summary of panel presentations an iscussions IEEE Trans. On Components an Pacaging Technologies, 5(4): , 00. [] R. Viswana V. Waharar, A. Watwe an V. Lebonheur. Thermal Performance Requirements from Silicon to Systems, Intel Technology Journal 3, pp. 1-16, 000. [3] Blazej, D. Thermal Interface materials, Electronics Cooling, Volume 9, Number 3, August 003, S. 14 ff [4] Bruce M. Calculations for thermal interface materials ;, Electronics Cooling, Volume 9, Number 3, August 003, S. 8 ff [5] Lasance, C. J.M. Problems with Thermal Interface Material Measurements: Suggestions for Improvement, [6] Bosch, E., Lasance C. High accuracy thermal interface resistance measurement using a transient metho Electronics Cooling, Vol.6, No.3, September 000 [7] Netzsch TCT416, [8] [9] Wöstmann, F.-J, Hahn, O. Messverfahren zur Ermittlung er Wärmeleitfähigeit ünner Klebschichten, Proution von Leiterplatten un Systemen, Heft 1, S. 139ff, 005 [10] May, D. Entwurf un Aufbau eines Messplatzes zur Charaterisierung von Thermischen Interface Materialien, Diploma Thesis, FHTW, Berlin, Germany, 004 [11] Schacht, R., May, D., Wunerle, B., Gollhart, A., Wittler, O., Michel, B., Reichl, H. Characterization of Thermal Interface Materials for Thermal Simulation, ESTC 06, Dresen, Germany, 006 A Eitions/THERMINIC 006 -page- ISBN: