UST/DME: A Clock Tree Router for General Skew Constraints

Transcription

1 UST/DME: A Clock Tree Rouer for General Skew Consrains C.-W. Alber Tsao Ulima Inerconnec Technology, Inc. Cheng-Kok Koh School of ECE, Purdue Universiy (Suppored in par by NSF) 4// Ouline of Talk Inroducion Problem Formulaion Incremenal Skew Scheduler The UST/DME Algorihm Experimenal Resuls Fuure Works 4// usdme

2 Clock Skew Consrains To avoid zero-clocking (Upper-bound) i + logic, max + seup j + P i j P logic, max seup δ u To avoid double-clocking (Lower-bound) i j logic, min + hold +δ l FFi Combinaional Logic FFj i j 4// Review of Previous Works Clock skew scheduling opimizaion Linear programming [Fishburn 9] Graph-based algorihms [Deokar/Sapanekar 94, Neves/Friedman 96] Clock ree rouing opimizaion Zero-skew ree (ZST) rouing [Jackson/Kuh 9, Tsay 9] ZST rouing by Deferred-Merge Embedding (DME) Paradigm [Chao/Hsu/Ho 9, Boese/Kahng 9, Edahiro 9] Bounded-skew ree (BST) rouing by DME [Cong/Kahng/Koh/Tsao 98] Useful skew scheduling and ree rouing (UST-BP) [Xi /Dai, 96] 4// 4 usdme

3 Problem Formulaion Given Se of n sinks S = {s, s,, s n } Opional clock source s Se of local skew consrains: C = {l ij i j u ij } = { i j [l ij, u ij ] } Find ree T over S Toal wire lengh is minimized Schedule { i } saisfies skew consrains C 4// 5 Ouline of Talk Inroducion Problem Formulaion Incremenal Skew Scheduler The UST/DME Algorihm Experimenal Resuls Fuure Works 4// 6 usdme

4 Graph-based Skew Scheduling Skew Consrains C Graph G c (V,E) [, ] [ 5, ] [, 4 ] Feasible skew schedules exis 4 5 v v No negaive cycles in G c [Cormen/Leiserson/Rives] 4// 7 Feasible Skew Range (FSR) Maximum skew range for commiing skew beween sinks such ha final skew schedule is feasible [, ] Given [ 5, ] [,4] = =? =? v 4 5 v = 4// 8 v usdme 4

5 Feasible Skew Range (FSR) Given [, ] [ 5, ] [,4] FSR [ 9, ] = = 9 = 6 = = 5 = = = 4 = 4 = 4// 9 Compue an FSR [, ] [-5,-] [,4] Given d = 9 d = 4 5 v ij : Shores disance vi v j 4// d FSR = d d = 9, [ ] [ ], v usdme 5

6 Compue all FSR's v v v v All-pair shores disance marix D = v { } d ij 4 5 v FSR d [ ] ij = ij,d ji v G c (V,E) 4// Updae Disance Marix Skew Commimen i j = x New consrain x i j x Edges in G c updaed wih d ij = x, d ji =x Marix D updaed in O(n ) = 9 d = 9 d = 9 d v 4// v d kl = min d d ki kj d + d + d kl = d + d = ij ji + d + d 4 jl il usdme 6

7 Incremenal Skew Scheduler Build G c from skew consrains C : O( E ) Build disance marix D from G c : O(n ) For any non-rivial FSR ij : n seps Commi skew a xfsr ij (bes for rouing) Updae disance marix D : O(n ) ime Complexiy: O(n ) 4// Ouline of Talk Inroducion Problem Formulaion Incremenal Skew Scheduler The UST/DME Algorihm Experimenal Resuls Fuure Works 4// 4 usdme 7

8 The UST/DME Algorihm Incremenal skew scheduler + DME Exension from a global skew bound o general skew consrains Two-phase ree consrucion Boom-up: Consruc a binary ree of merging regions for inernal nodes Top-down: Embed nodes in merging regions 4// 5 UST/DME: Boom-Up Phase Merging regions Loci of min-lengh locaions of inernal nodes Consruced beween child regions wih feasible skew a s b mr(a) s s s s Topology s s s 4// 6 usdme 8

9 UST/DME: Boom-Up Phase Merging regions Loci of min-lengh locaions of inernal nodes Consruced beween child regions wih feasible skew v v v v v mr(a) s s FSR = [-9,-] s s 4// 7 Merge a, s b Choose segmen L a mr(a) closes o s Compue skew = on L a for sinks s, s Updae marix D for commiing skew = v v v v v mr(a) s L a s ( skew = ) s s 4// 8 usdme 9

10 Merge a, s b Choose segmen L a mr(a) closes o s Compue skew = on L a for sinks s, s Updae marix D for commiing skew = v v v v v 4 4 mr(a) s L a s ( skew = ) s s 4// 9 Merge a, s b (con.) Ge FSR from marix D for sinks s and s Build mr(b) beween L a, s where skew FSR v v v v v 4 4 s mr(b) mr(a) FSR L a ( skew = ) [, ] = 4// s s s usdme

11 Top-Down Embedding Embed inernal nodes in merging regions where closes o paren nodes s s s a b b s s Topology s s a s 4// Experimens ISCAS89 circuis #sinks #skew consrains Max. global skew bound (ns) s s s // usdme

12 Experimenal Resuls 5% % 5% % 5% % 5% % Wirelengh reducion over ZST s4 s578 s585 UST-BP (Xi/Dai,96) BST/DME (Cong e al., 98) Greedy- UST/DME UST/DME +Topology 4// Experimenal Resuls (con.) um.45 Wirelengh vs. Safey Margins on s585.5 Greedy-UST/DME UST/DME (BST opology) BST/DME Safey margins δ l = δ u ( ps) hold log ic,min + δ l i j P logic, max seup δ u 4// 4 usdme

13 Conclusions UST/DME: Simulaneous clock skew scheduling and ree rouing Exension of DME paradigm for general skew consrains Fuure Work Reduce O(n ) complexiy of UST/DME Improve opology generaed by Greedy-UST/DME Inegraion wih buffer inserions 4// 5 usdme