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1 õ Î î Ç Phase Detector Â Ì ç í 1, Â Ä 2, Ö ì µ 1 1 ¼ ë Ð ³ ü â Ä» Í ø Ð ú, 2 Ñ ¹ ü Ú ë Å ø í Ó º À T E L : ( O 2 ) , E - m a l : p a¹ tn ihmrmnm sä egm rnm Ynm½u iï cä owm rnmiḑ4 y OÌm rnm1s säò ed ilh a aä c ¹kº A Giga- bps C lock and Data Recoveq System with a New Phase Detector J a e - U k L e e 1, D e s k C h e w - 2, W o o - Y o u n g C h o p ( 1 D e p t o f E l a m c a l a d C o m p u t e r E n g, Y o n s e i U n i v e r s i t y, 2 m e c u m H c s a d T e l a o r n m u r t i c a t i o n s R e s e a r c h I n s t i t u t e, H i g h s p e e d s w i t c h T e m T E L : ( O 2 ) B 7 4, E - m O l : pm am tu ibmrmnm sä egm InmYnm½u iï cä oìm rnm1m 4 y oìm rnm1s sä» ed ilmaaä Ccd»k lkó é - A b s t r a c t Sen d transmission links at Gbps a e bc om r a commercial r eality td ay - T o V ansmit high Sï à d dam, clä k ra overy ch um- s a- cri Ucally imm rtant and must be develon d Gmt W e proä se a Gbps ClÄ k and Data Ra m e y (CD[D Sy stem w ith a new Phase De- cm (fd ) T he PD can sense data transition and sa y deactivated during no- transition m 1d s n e sy stem w ith a new PD has faster lä king dme M d su¼p r esses high fmquem y j itter T his sy ste m is designed w ith 25 V, Oø p m CM 0 S with H SPICE simulation 1 I n t r o d u c t i o n º ü Â Ò ñ Í ú ñ ë Ì ó  å CM0 S ç ë Ñ Ã º Û ë Ñ Â Ð Ô ø à Ç í Ö Ù æå à º Û Ì í Ó, ë ë Ê û ó, à º Û ¹ Ç ý û Ö Ù Ì û ó GbpsÞ Ç ô º Î Î Í clä k Å ß ã Ï Â Ç Ñ ß Ì ç î ö í Ö Ù Fiber - channel» ç ë Ñ data transceiver Ç æì GbpsÞ ü Û ü BER< l o-- Ç º ó ² ä Ï â µ Ñ Ù Gig- it Ethernet ProtÄ ol (% 23 z)ç æ ì 12 5Gbps dataü ¹ ø Ï â Ø Physic Layer Ç Ô Ý ² 8B 10B coding à ç ë Ñ N RZ dataî ï í Ö ç, â ç ë É PM A (Physical M d ium A ttachment) L ayer Ô È T BI (T en Bit Interface) block º 1 M H zç à º Û clä k Î Î Í 12 5GH zç clock» ß ý Ã Ñ data lä k Ã Ñ ß Ñ Ù [ 1]» È È Ã º Û º Ì Ñ â É ² ö à Ò ö Ö µ Ï 1OÐ Ö È Ã º Û cla k ² ø Þ Æ GHzÞ Ç data ¹ ø ç ë É clä k» ß ý à í NRZ dataç transition Ý ë Ï Â õ Î î Ç PDê ç ë Ï Ó È Oú 1Ì ö Å É æ ì µ Ù È û Î d Ä k Ã ß ý à µ Ï ³ è Ç ú Ù 2å  ü ¼ à º Û ç ë È blä k ú È È Î Ç â ó» ³ í Ï í 3 å ³ è È ü ¼ à º Û ë Ñ HSPICE simulation á ú Ì ç á Ð Ã Î Â Ù 9 1

2 g Ö ±m >½ = 2 C D R s t r u c t u r e È È Ã º Û º ² 1 ¼ ö Ö í Ì 1OÐ Ö È Ã º Û clä k V CO (V oltage Controlld oscillator ) ini ti al frq uem y acquisition Ç Â Ï Ý û Î PFD (Phase FIº uency Det- - r ) ç ë Ñ lä p[2], Ì ó  dam ö Å É æ ì dag Ü tr am nion à deä ct Ï UPú DOW N Å ß ý à  lä p[3], í Ì Î lä p Ç Û Ã ± Ã Ò ö Ö µ Ï î Ï Â lä k da m or Ç ¼ Î Ð Î ª ö Ö Ù [4,5] Ddw mud Iø D m e iñ D * c C:WN R d d R o t- - d h C - e- Da, * u l U K í - - ¹ L ku d* d Û» I C P - a la-a X du - -B - - -L du - -c n h U (Í Ch ck Ì D u ð u D h u - r,,,» 7Jm f m J (b) C lock ú D u aâ lock Ç ú» û R ÄWN v v v v v x du a A ,, - d u B Z d u -C + d ¹ f s, n m f ± ± ( c ) C h c k Ì D - u Ê» ð ± 3 Pt- a- e D e te ct o r Ç î Û 9 2

3 é dam- B Í Ì Ù ü Ð data- A Í Ç ex clusive- ORü ë Ø ò î ö ç UP Å Â dau - A Í dau - C Ç exclusive- OR µ ª ß clä k Å Í ã  ΠР² deta t Ï á ¹ data- B Ç d geí clä k Ç negative d geê lä k Ã Ô È Ù ² 4 (a)â Ì ó û Î æ ì Ç PD Û ¾ ª» í Ö Ù [ 1] È È Î Ç Û º ³ 4 (b )ê Ì í Ì delay Ç â (Ë) ö Ï Ì ó û Î æì Ù Ï Ô Ç Â, delay Ç â í Ç î Ö» æ ì À Á ç ë Ç Â clock Ç Ö Ä ö û ó ËÇ â Ù ð ö Ö ½ ² Ü Ì Ñ Ù Ç Ì µ ª º Ö ë î ö å É ö Ö Â dd ay V CO Ö Ä ö û ó ó Ç ª» ú ö Ö î ß Ö û Ç Û» Ò ö Ö È Ã Ç Ì Ñ Ù È È Â 4Ü differential inver ter V CO Ç ³ è Ä 2Ü Ç ¹» ç ë Ï m Ç delay ç ú ö Ö µ Ï Ï ç î ü л Ï V COÇ Ö Ä ö û ó û Î Û Ï Ô È Ù Ö í Ö ç VCO gainº à XPMHz¹ Ì Ù z Y, os--: r m f* ù 6 V Ex- a t :,, o s RH u meyµ - = c mroi Volu - -IVl ² 7 VC0 Hequem y º Ò ± W u (a) Ç Ñ æì Ç m î Û P K - - [ ± t -* ² 4 Ru a D a m Ç Û È È È Ç m î Û VCO ³ 5ú Ì 4Ü Ç differential inve t- ç ç ë Ï º Ï ç lak h ü Â Ç loadê Î Ï í Ó Ö È û Î ß» Ò ö Ö ç ß ø ø ø Ç â õ Ã Ñ PD Ù È û Î ü Û ² Ò ö Öµ Ï Ï Ø Ù [6] v d d ra d[ rd[ ]h ]V è4 M,,, (a) â ì Ä ll ) 4Ü d m - m u Ä ci1l 5 VCOÇ Î ä ² 6 õ É Ö Ä ö Ç VC0 Ø Ù ³ è È VCOÇ Ö Ä ö å º º é

4 2000â 5ù CAD 3 S i m u l a t i o n a n d A n a l y s i s È È Ã º Û º ² 1ú Ì º Ç î ö Å È damü ¹ ø Ï Ô Ç Â ü ¼ à º Û Ç º É º VC0 Ç î Å Î Ë ö Ö Ù ³ 9 ö Å È dah 16Ä bps, 15 Ä bps, 14Ä bpsï Ç VÄ î ü л ª ½ Í Ì Ù Ê â Ö Ä ö ñ Ö Ä ö Ç 10%Ì» ¹ ÖÙ í ß» Ç Ê â ª Î Ã Û Ï Ç lä king time» ¼ ö Ö Â ß É Ö Ä ö ü þ î ö Ï ³ ü ù Ç Ø lä MÄ UmeÌ æî ö Ô Ç ö (b)ç æì O3, sì» lockingì Ê» Ë ö Ö Ù ² 1Oº 15Ä bpsç dab ê ö Å ß» PDÇ delay control voltageü ª» í Ö VCO î Ï Â ü Ð Ì ÆÑ lä p filter Ç cap o mr É ü Ð Î Ù È û Î PDê î Ï í Ö½» Ë ö ÖÙ ± O, 4 4 T i n - { p l» Ú,,, - - I µ, I A Oo o o o o r am - * J ± ± : 3 T im I u l ± - - a rm ing tiff- ng, µ, -,, T lm I l ± Ä o au an 6 n ne [nï ³ 12R e ify- d C lock a d D au I x, 4 n m I u l 9 4

5 4 C o n c h s i o n»  daw Ç Vano tion» deta t Ï Â delay cell² Ì ë Ñ PDê È Ï Mgh frq uem y j itter Ù Ì í ü Ð lä Mng time» µ Ï Ï í, ë Û º damí clä k Ç phase error û simulation² ë Ø Ë õ Ï Ù Ì Ç Ã º Û º NRZ ü Â Ç dau Ó È O, 1² ö Å Ò µ È û Î Û ² Ï Ô Ç ç VCOÇ â» cell» ç ë Ñ PDÇ ³ è Î ³ è à ² Ü à à ð ö Ö ç PD MUX, ü Ï ß Á  í Ó Ç Û ² å Ï â Ø h 1ly diffe ntial logic Î ³ è Ç ú Ù blä kº Gig- it Ethernet R otä ol Â ß î ³ è Ç î high S@d switch data transceiv- Î Ì ë É ö Ö² Í Ì Ù R e f er e n c e s [1] I EEE Sd 23, 1%8 Edition [2] Bet ad Ra n i, MomOra- PAg e-l- A- d Loops and Cfa A Ra m-- Orea s, n eo- ad * sòn, E EE Press, 1%% [3] Bang- sup Song, et al, NRZ Timing Ra overy Tc hu m- for Band- Limitd Channels,± JSSC, vol- 32, no4, m 514- Ä 0, AN il [4] German Guiderrez, et d, 4248 Gb s Silicon BiÄ lar ClÄ k and Data Ra w a y IC for SONER OC- 48),± CICC, m 5755 % M B [5] Moun- Meghelli, et d, SiGe BiCM 0 S 33V ClÄ k and Data R- ov- T Send Transmission PPM -57, 2d P [6] K- m-an In varh, et d, Ra overy for 12Ä b s in O3 5p m CM0 S,± [7] John P W a tt- a, rl9, %Sa pa- - ~ - H a - - Rm - -,

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