CERAMIC THICK-FILM CAPACITOR FOR EMBEDDED PASSIVES IN PRINTED CIRCUIT BOARDS

Transcription

1 CERAMIC THICK-FILM CAPACITOR FOR EMBEDDED PASSIVES IN PRINTED CIRCUIT BOARDS Diptarka Majumdar,* William Borland,* Olga Renovales,* Marc Doyle,* and Gerard Vanrietvelde** DuPont Electronic Technologies *Research Triangle Park, NC 779 **Frenchay, Bristol, U.K. BS16 1QD ABSTRACT The embedding of passive devices within the substrate is critical to achieving the next step change in miniaturization of electronic designs concomitant with increased functionality. Embedded passives have numerous advantages that show up in different segments of the market, but one crucial need is high capacitance density in low-cost organic substrates using simple manufacturing processes. This capability is needed for a variety of cell phone handset components and emerging computing needs. Ceramic thick-film embedded capacitor technology brings the capability to bury high capacitance density components for the first time within an organic substrate, allowing high value decoupling capacitors to be buried for chip packaging or related applications in spaces available within any layer of the substrate. The ability to locate decoupling capacitors within a couple hundred microns of semiconductor I/Os greatly improves response time and signal integrity leading to product performance improvements. This paper discusses the development of ceramic thick-film capacitors embedded in printed circuit boards. The dielectric paste is based on doped barium titanate composition and works together with a cofired copper electrode paste. The capacitor system is designed to be screen printed on copper foil in the locations desired in the circuit and fired in nitrogen at 9 C to form the ceramic components. Following this, the foil is laminated, component face down, to the organic laminate using standard prepreg and the inner layer etched to reveal the components in an organic matrix. The system achieves a very high capacitance density of ~1.5 nf/mm per dielectric layer, exceeding even the capability of on-chip technologies such as thin film on silicon and glass. The dielectric system shares many characteristics with X7R type dielectrics although its TCC behavior is broader than X7R. It can achieve high dielectric constants greater than 4 and low dissipation factors <.5% over a broad frequency range. In the following sections, some process issues are discussed and test data for electrical performance and reliability are presented. INTRODUCTION Current commercially available embedded passive materials include etchable thin film resistor laminates, organic capacitor laminates, and polymer thick-film capacitors and resistors. The capabilities and limitations with existing systems have been discussed in the literature. 1-5 One key limitation of current embedded and integrated passives approaches is limitations in capacitance densities achievable within applications having limited free board area. The ceramic thick-film approach can achieve in excess of ~1.5 nf/mm per layer with multiple layers readily integrated into organic laminates using simple and low-cost process technology. The current work began as part of the Advanced Embedded Passives Technology (AEPT) consortium and was co-funded by the National Institute of Standards and Technology of the U.S. Government and industry participants. 6 The objective was to develop a process and materials that would allow ceramic components with high capacitance density and a broad range of ohmic values to be buried inside PCBs, thereby making embedded passives viable for small size circuitry. The ceramic thick-film process for embedding passive components is based on a combination of two well-understood commercial processes: nitrogen-fired thick-film hybrid production and traditional printed circuit board fabrication. 7 Overall, the process offers a tremendous simplification in the production of finished circuit boards with ceramic components by significantly reducing the number of steps and putting the process of component fabrication and assembly into the hands of the PWB fabricator. The most unique aspect of the ceramic thick film embedded passives technology is the capability to achieve relatively high-value capacitors in small space within an organic based substrate. Due to the high dielectric constant achievable with fired ceramic materials, capacitance densities in excess of 1.5 nf/mm can be achieved which is beyond any other technology known at this time. This enables the costeffective removal of capacitors with values in the range of about 1 pf up to greater than 6 nf which can often represent a high percentage of total capacitors in a system. THICK-FILM FIRING PROCESS

2 The process flow for embedding ceramic passives has been documented quite extensively elsewhere. 7-1 In brief, it combines conventional thick film processing and standard PCB processes. For the development of a robust manufacturing process, key issues pertaining to the thick film and PCB sections of the process flow have to be addressed and are discussed below. When a copper foil with screen-printed paste is sent through a hot wall furnace with a peak temperature of 9 C (Figure 1), the paste experiences three primary reactions viz. burnout of organics, densification of the ceramics and reactive bonding to the copper foil. An important thick-film processing issue pertains to the control of the firing atmosphere. Since the capacitor and resistor pastes are printed on copper foil, the oxygen levels in the feed nitrogen and the furnace should be carefully controlled and monitored. Despite its potentially deleterious effect on the copper, some oxygen is necessary to burn off the organics in the paste completely. While excessive amounts of oxygen oxidize the copper, insufficient amounts may lead to residual carbon from incomplete burnout which hinders the subsequent ceramic densification processes and thus negatively impacts the electrical properties and physicochemical robustness of the final ceramic components. The typical concentration of oxygen in commercially available nitrogen is ~1- ppm. While this should be enough to oxidize Cu at 9 C as copper (I) oxide is the stable phase under these conditions, copper foils fired in nitrogen using the profile in Figure 1 remain practically unaffected. This is because some of the excess oxygen is used to burn off the organics and the rest dissolves in copper which can retain as much as.16% oxygen by weight. Hence, an atmosphere that is slightly oxidizing to copper is used to fire DuPont s embedded passives on copper foil. Temp, Deg. C Ramp Rate (3-6C) 45-5 C/min 9 Degree Furnace Profile 1+/-1 min. Peak (9C) Time, Minutes Descent Rate (8-3C) 6-8 C/min Figure 1 Firing Profile for Ceramic Embedded Passives Pastes Another issue arises from the dimensional changes that a copper foil undergoes upon firing. This can lead to misregistration of circuit patterns that are screen printed on the foil and fired sequentially. Therefore, it becomes necessary to accurately quantify these dimensional changes associated with multiple firings so that they can be accounted for by proper scaling of artwork used to make screens. One system that has the necessary gage capability to measure +/- mil movement over an 18 x4 copper foil is the ACTCO Metrology OGP system. This system was used to examine the dimensional changes that occur during multiple firings of copper foils either with just preprint or covered with dielectric and/or resistive pastes. Figure shows the data taken from three replicate measurements on four identical foils taken through four firing steps for an Oak-Mitsui PLSP grade copper foil covered with preprint and a cross-hatch pattern. These results show that the copper foil shrinks a constant amount with each successive firing if little or no paste is present on the foil surface other than the preprint. This shrinkage continues through at least three firing operations with no significant increase in variability from firing to firing. Y mil o of passes 1 Figure Movement in One Direction (Y is shown here) upon Successive Firings at 9 o C The dimensional changes are substantially lower for designs that have a high coverage of dielectric or resistor paste on the foil. In some cases, the absolute shrinkage of the bare copper foil (as defined by the data in Figure ) can be reduced to nearly zero, making no compensation necessary to match the copper foil with the innerlayer artwork. The most critical issue to control is the handling of the copper foils and any damage that occurs during handling, which can lead to an apparent shrinkage much greater in magnitude and more variable than the true shrinkage due to firing the copper foil. More significant registration challenges are posed by standard PCB processes, which are routinely addressed by board fabricators. 9 CAPACITOR SYSTEM Boxplots of Y mil by No of pa (means are indicated by solid circles) 3 4

3 The capacitor material is based on a doped barium titanate functional phase and a compatible glass which form a thick-film dielectric paste referred to as EP31 capacitor dielectric. It has broad TCC characteristics similar to Z5U (+/- % change over 1 to 85 o C) and a high dielectric constant (K) of ~4 and low dissipation factor of <.% at 1kHz. It is printed to a total thickness of 8-34 µm which fires to ~18-4 µm and can be used in either single or multi-layer capacitor constructions, depending on space availability within the PCB innerlayer. Table 1 gives typical capacitor properties in combination with EP3 copper thick-film paste. Dielectric pastes with different TCC properties have also been formulated and tested, including X7R type dielectrics with lower K values, but the current dielectric is believed to meet a pressing market need for very high capacitance density in the temperature range of 5 to 85 o C which is a common operating temperature range for Rf components. Table 1 - Typical Capacitor Properties for EP31 Dielectric System Property Dielectric Constant Capacitance Density Dissipation Factor Insulation Resistance Breakdown Voltage TCC Characteristics Curie Temperature Value ~15 nf/cm per layer <. > 1 9 Ohms > 3 V/mil +/- 35% change from 55 to +15 o C 5-15 o C Figure 3 illustrates typical TCC properties for the dielectric system. The Curie peak temperature is located at ~15 o C which is ideal for maximizing dielectric constant at ambient temperature while keeping dissipation factor low. TCC data from several different scale-up lots of dielectric paste are shown in Figure 3 to demonstrate the typical lot-to-lot variability. Note that capacitance can vary due to variations in paste properties, screen print variations such as thickness, and inherent measurement capability. We typically see a variability of about 1% (one sigma) on capacitance value on capacitor test vehicles built in-house with a variety of different paste lots. that we have envisioned have been documented within preliminary Design Guidelines available from the author upon request Cap;(pF) TCC: EP31 Scale-up pastes 5 45 Temperature; C Lot 1 Lot Lot 3 Lot 4 Lot 5 Figure 3 TCC Curves for Several Different Lots of EP31 Capacitor Dielectric The fired dielectric thickness has been varied over the range of about 1 to 4 microns for testing purposes. Too thin a dielectric (less than about 16 microns) leads to an increase in shorting rates while too thick (greater than 4 microns) can lead to burn-out problems. Our standard recommended thickness is on the low side of this range in order to maximize capacitance density of the system. Customers have also vigorously pursued multi-layer capacitor structures with various termination designs. For example, a two-layer capacitor structure with recommended dielectric and electrode thicknesses can be accommodated within a prepreg thickness of 6 microns, which is popular in IC packaging applications. Multi-layer capacitor designs can accommodate the need to have throughholes penetrate through the structure and can be interconnected into larger structures that provide higher capacitance making use of any space available within an innerlayer Design Rules for Capacitors Embedded capacitors using the EP31 ceramic dielectric paste system have been embedded into a range of PWB test vehicles and commercial prototype parts. Capacitors can be placed onto any layer within the PWB and can be interconnected using a variety of termination designs and schemes. Many of the designs

4 Figure 4 Cross-section of Fired Capacitor Dielectric Showing a Dense Microstructure under Standard Firing Conditions The active capacitor area as defined by the top electrode size can vary from 1 mils on a side up to several hundred mils. We recommend top electrode size ranges from 1 to 18 mils for purposes of screen printing tolerances and keeping the capacitor size small enough to minimize distortion of the underlying copper foil after firing. When higher capacitance is needed, we recommend a variety of interconnection schemes that limit the maximum dielectric size in any given area to around 18 mils on a side. Figure 4 is a high magnification cross-section of the capacitor microstructure. The barium titanate is the white dispersed phase and the glass is the darker background continuous phase. The microstructure is very dense with some isolated porosity. Typical barium titanate grain size is in the range of -5 microns. Processing Factors Typical firing conditions (1- ppm oxygen) give a barium titanate structure with well-developed grain size in the 3-5 micron range. Higher oxygen concentrations up to 5 ppm give a continual reduction in peak K value and lowering of dissipation factor to less than 1%. The effect of oxygen content on dielectric constant is illustrated in Figure 5. The higher oxygen concentration also reduces barium titanate grain size down to the 1- micron range for >14 ppm oxygen. While we do not recommend higher oxygen contents during firing, it is clearly possible to manipulate dielectric properties using oxygen control during firing. up to six times to assess the impact on dielectric properties and shorting rate. No significant increase in shorting rate is seen with multiple firings. There is clearly an increase in dielectric constant and dissipation factor with multiple firings. Figure 6 shows the average capacitance of a set of samples fired three successive times through the standard nitrogen firing process. This increase in capacitance levels off and remains essentially constant after the third firing. We speculate that this increase over the first three firings is due to continual grain growth in the barium titanate particles. The variability across the samples also increases on the second firing Firings Cap at 1kHz Figure 6 Box Plots of 1kHz Capacitance after Three Successive Firing Processes 15 Boxplots of Cap at 1kHz by Firings 1 Regression Plot Cap = log(frequency) log(frequency)** S =.5388 R-Sq = 98.8 % R-Sq(adj) = 98. % 3 Dielectric Constant 4 3 Boxplots of Dk by O Content Capacitance (nf) Frequency (khz) 5 1 Regression 95% CI 95% PI Figure 5 Box Plots of 1kHz Dielectric Constant as a Function of Furnace Oxygen Content Multiple refirings of the dielectric are possible and even essential in some capacitor constructions. The capacitor system is designed for cofiring together with the copper electrode paste. However, a double-layer capacitor will commonly be formed using two firing processes (although complete cofiring is possible also). For purposes of testing, we have fired capacitors 14. O Content (ppm). 7. Figure 7 Frequency Dependence of EP31 Test Vehicle Capacitance Frequency Dependence We have examined the dielectric properties of the EP31 capacitor dielectric material up to frequencies of 1 MHz. The dissipation factor and capacitance as functions of frequency over the range of 1kHz to 1MHz are shown in Figures 7 and 8. The capacitance shows an approximate reduction of <1% in value over this range, while the dissipation factor generally increases with frequency. Both systems show relatively stable frequency dependence over the whole range measured. Regression analyses were done to

5 quantify the frequency dependence of K and Df and are given in the figures. Note that both regression equations gave very good R squared values indicated a good fit to the data. The red dotted lines in Figures 7 and 8 illustrate the 95% confidence intervals for the frequency dependent K and Df data. Confidence intervals represent the likely range of the mean value of either capacitance or Df at a given frequency. The blue dotted lines in both figures represent the 95% prediction intervals for the two sets of data. Prediction intervals give the predicted range of values expected from individual measurements of capacitance or Df at a given measurement frequency. Df (%) S =.661 R-Sq = 74. % R-Sq(adj) = 56.6 % Regression Plot Df = log(frequency) log(frequency)** Frequency (khz) 5 1 Figure 8 Frequency Dependence of EP31 Test Vehicle Dissipation Factor Dielectric Aging Rate Aging is a characteristic of all ferroelectric materials that involves the reversible decay in dielectric constant and dissipation factor after the system is cooled to below the Curie temperature. The spontaneous domain polarization that occurs below the Curie temperature creates stresses throughout the fired ceramic body that relax over a finite time, causing the characteristic decay in electrical properties. The EP31 capacitor dielectric exhibits aging after each firing step and the aging process has been characterized and quantified Regression Plot Cap@1kHz = log(time(min)) S = R-Sq = 89. % R-Sq(adj) = 88.1 % Regression 95% CI 95% PI Figure 9 Aging Rate of 1kHz Mean Capacitance over Multiple EP31 Dielectric Lots Figure 9 shows a plot of 1kHz capacitance versus time for a particular test vehicle composed of large square single-layer capacitors on copper foil with active electrode area of.81 cm. The regression plot fits the capacitance decay to a logarithmic decay curve. As expected, the quality of the fit is very good with R squared value of 89%. Several different test vehicles involving different lots of dielectric paste were used to measure the aging rate and its variability for this system. Capacitance aging rates averaged.6% per decade-minute over different lots of dielectric paste with a standard deviation of.4% (CV=16%) between the different lots. The aging rate specification for X7R dielectrics is less than.5% per decade-hour decay rate. The EP31 system falls short of X7R requirements but is very close to this value. The aging rate of the 1kHz dissipation factor was 8.5% with CV of 8% using data on three different lots of paste. In practice, the MLCC industry will often over-design capacitors to allow for the known aging behavior of ferroelectric materials. This same practice may become common in the embedded capacitor field. Board-Level Reliability Reliability testing was done on finished printed circuit boards containing ceramic thick-film capacitors on the L/L3 core of the 8-layer board. Four different sized capacitors were tested, having areas as follows: C1: 55x6 mil, C: 188x188 mil, C3: 84x84 mil, and C4: 19x19 mil. We would like to acknowledge the assistance of Compeq in Taiwan for building the boards and creating the test data given in this section. Tests performed included temperature-humidity at 85 o C, 85% RH conditions, thermal cycling testing between 4C and +15 o C for 5 cycles, and HAST testing at 11 o C and 85% RH for 64 hours Cap@1kHz Time(Min) C1 C C3 C4 Drift C1 C C3 C4 Max -4.% -3.59% -.43% 1.49% Min.53% -.3%.5%.95% Ave -1.6%.73% -.6% 1.94%

6 Figure 1. Change in Capacitance Values During HAST Testing for Different-Sized Capacitors <.5% over a broad frequency range when processed under standard conditions. HAST testing was performed at 11 o C and 85% RH for 64 hours without baking after the test prior to measurement of the final capacitance. The capacitance changed less than 4% for all capacitors after the 64 hours. The results are illustrated in Figure 1. Average changes were around 1% for most of the capacitor sizes except the smallest-sized capacitor that averaged a % change. Thermal cycling testing was done between 4 o C and +15 o C for 5 cycles. All four capacitor sizes showed less than 3% drift after 5 cycles as shown in Table. Humidity-temperature (85 o C/85%RH) testing was done for 1 hours and capacitance was measured both with and without a baking step after the 85/85 exposure. The final percent drift after 1 hours was generally less than 5% for all capacitors. However, one outlier showed a 1% drift, for reasons that are still under study. In general, the capacitance drifted upwards between and 5% during 85/85 and was brought down to to 5% after the baking step. Table. Capacitance Values and Percent Drift During Thermal Cycle Testing to 5 Cycles nf initial 1 cycle 3 cycle 5 cycle Drift C % C % C % C % SUMMARY The simplicity of the Interra ceramic embedded passives process is due to its elimination of numerous steps from today's circuit board process flow, including many component fabrication steps and the elimination of inventory, assembly and rework for surface mounted components. Interra ceramic thickfilm embedded capacitor technology brings the capability to bury high capacitance density components for the first time within an organic substrate, allowing high value decoupling capacitors to be buried for chip packaging or related applications in spaces available within any layer of the substrate. Finally, the ability to locate decoupling, bypass, and blocking capacitors within a couple hundred microns of semiconductor I/Os can greatly improve response time and signal integrity leading to tremendous product performance improvements. The dielectric system presented here shares many characteristics with X7R type dielectrics although its TCC behavior is broader than X7R. It can achieve high dielectric constants greater than 4 and low dissipation factors ACKNOWLEDGMENTS The authors gratefully acknowledge the assistance of Rick Traylor, Saul Ferguson, Alton B. Jones, and Lynne Dellis in the sample preparation and electrical testing and the SEM work of Tom Davenport, all of DuPont Electronic Technologies. We would also like to acknowledge Peter Chiang from Compeq for the reliability test results. REFERENCES 1. W. J. Borland and S. Ferguson, Embedded Passive Components in Printed Wiring Boards: A Technology Review, Circuitree, March 1.. D. MacGregor, Standards Development Efforts for Embedded Passive Materials, IPC Annual Meeting, October P. Sandborn, B. Etienne, and D. Becker, Analysis of the Cost of Embedded Passives in Printed Circuit Boards, IPC Annual Meeting, October J. Savic, R. T. Croswell, A. Tungare, G. Dunn, T. Tang, R. Lempkowski, M. Zhang, and T. Lee, Embedded Passives Technology Implementation in RF Applications, IPC Expo, March. 5. J. J. Felten and S. Ferguson Embedded Ceramic Resistors and Capacitors in PWB -- Process and Design, IPC Expo, March. 6. AEPT website: 7. Japanese patent application JP to Ibiden. 8. W. Borland, J. Felten, L. Dellis, S. Ferguson, D. Majumdar, A. Jones, M. Lux, R. Traylor, and M. Doyle, Ceramic Resistors and Capacitors Embedded in Organic Printed Circuit Boards, Proceedings of IPACK3, International Electronics Packaging Technical Conference and Exhibition, July 6-11, 3, Maui, Hawaii, USA. 9. J. Felten, S. Ferguson, L. Dellis, W. Borland, M. Doyle, G. Vanrietvelde, J. Ferguson, J. Cocker, J. Zhou, and J. D. Myers, Reliability Data for an Engine Control Module Emulator Board Containing Ceramic Thick Film Embedded Resistors, 14 th European Microelectronics and Packaging Conference & Exhibition, Friedrichshafen, Germany, 3-5 June R. Snogren, Embedded Passives A Novel Approach Using Ceramic Thick Film Technology, Proceedings of IPACK3, International Electronics

7 Packaging Technical Conference and Exhibition, July 6-11, 3, Maui, Hawaii, USA.