P&H 4.51 Pipelined Control. 3. Control Hazards. Hazards. Stall => 2 Bubbles/Clocks Time (clock cycles) Control Hazard: Branching 4/15/14

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1 P&H.51 Piplind Contol CS 61C: Gat Ida in Comput Achitctu (Machin Stuctu) Lctu 2: Piplin Paalllim Intucto: Dan Gacia int.c.bkly.du/~c61c! Hazad SituaHon that pvnt tahng th nxt logical intuchon in th nxt clock cycl 1. Stuctual hazad Rquid ouc i buy (.g., oommat tudying) 2. Data hazad Nd to wait fo pviou intuchon to complt it data ad/wit (.g., pai of ock in diffnt load). Contol hazad Dciding on contol achon dpnd on pviou intuchon (.g., how much dtgnt bad on how clan pio load tun out). Contol Hazad Banch dtmin flow of contol Ftching nxt intuchon dpnd on banch outcom Piplin can t alway ftch coct intuchon SHll woking on ID tag of banch BEQ, BNE in MIPS piplin Simpl oluhon phon 1: Stall on vy banch unhl hav nw PC valu Would add 2 bubbl/clock cycl fo vy Banch! (~ 20% of intuchon xcutd) I n t. d bq Int 1 Int 2 Int Int Stall => 2 Bubbl/Clock Tim (clock cycl) I$ Wh do w do th compa fo th banch? Rg D$ Rg Contol Hazad: Banching phmizahon #1: Int pcial banch compaato in Stag 2 A oon a intuchon i dcodd (pcod idnhfi it a a banch), immdiatly mak a dciion and t th nw valu of th PC Bnfit: inc banch i complt in Stag 2, only on unncay intuchon i ftchd, o only on no- op i ndd Sid Not: man that banch a idl in Stag, and 5 Qution: What an fficint way to implmnt th quality compaion? 1

2 I n t. d bq Int 1 Int 2 Int Int n Clock Cycl Stall Tim (clock cycl) I$ Banch compaato movd to Dcod tag. Rg D$ Rg Contol Hazad: Banching phon 2: Pdict outcom of a banch, fix up if gu wong Mut cancl all intuchon in piplin that dpndd on gu that wa wong Thi i calld fluhing th piplin Simplt hadwa if w pdict that all banch a NT takn Why? Contol Hazad: Banching phon #: Rdfin banch ld dfinihon: if w tak th banch, non of th intuchon al th banch gt xcutd by accidnt Nw dfinihon: whth o not w tak th banch, th ingl intuchon immdiatly following th banch gt xcutd (th banch- dlay lot) Dlayd Banch man w alway xcut int a8 banch Thi ophmizahon i ud with MIPS Exampl: Nondlayd v. Dlayd Banch Nondlayd Banch Dlayd Banch o $8, $9, $10! add $1, $2,$! add $1, $2, $! ub $, $5, $6! ub $, $5, $6! bq $1, $, Exit! bq $1, $, Exit! o $8, $9, $10! xo $10, $1, $11! xo $10, $1, $11! Exit: Exit: Contol Hazad: Banching Not on Banch- Dlay Slot Wot- Ca Scnaio: put a no- op in th banch- dlay lot Bm Ca: plac om intuchon pcding th banch in th banch- dlay lot a long a th changd don t affct th logic of pogam R- oding intuchon i common way to pd up pogam Compil uually find uch an intuchon 50% of Hm Jump alo hav a dlay lot Gat IntucHon- Lvl Paalllim (ILP) Dp piplin (5 => 10 => 15 tag) L wok p tag hot clock cycl MulHpl iu upcala Rplicat piplin tag mulhpl piplin Stat mulhpl intuchon p clock cycl CPI < 1, o u IntucHon P Cycl (IPC) E.g., GHz - way mulhpl- iu 16 BIPS, pak CPI = 0.25, pak IPC = But dpndnci duc thi in pachc.10 Paalllim and Advancd Intuction Lvl Paalllim 2

3 MulHpl Iu StaHc mulhpl iu Compil goup intuchon to b iud togth Packag thm into iu lot Compil dtct and avoid hazad Dynamic mulhpl iu CPU xamin intuchon tam and choo intuchon to iu ach cycl Compil can hlp by oding intuchon CPU olv hazad uing advancd tchniqu at unhm Supcala Laundy: Paalll p tag T a k 6 PM AM A B C Tim (light clothing) (dak clothing) (vy dity clothing) D (light clothing) d E (dak clothing) Mo F (vy dity clothing) ouc, HW to match mix of paalll tak? Piplin Dpth and Iu Width Intl Poco ov Tim Micopoco Ya Clock Rat Piplin Stag Iu width Co Pow Piplin Dpth and Iu Width Clock 1000 Pow i MHz W Pntium MHz W Pntium Po MHz W P Willamtt MHz W Piplin Stag Iu width Co P Chapt Pcott Th Poco MHz W StaHc MulHpl Iu Compil goup intuchon into iu packt Goup of intuchon that can b iud on a ingl cycl Dtmind by piplin ouc quid Think of an iu packt a a vy long intuchon Spcifi mulhpl concunt opahon Schduling StaHc MulHpl Iu Compil mut mov om/all hazad Rod intuchon into iu packt No dpndnci within a packt Poibly om dpndnci btwn packt Vai btwn ISA; compil mut know! Pad iu packt with nop if ncay

4 MIPS with StaHc Dual Iu Two- iu packt n /banch intuchon n load/to intuchon 6- bit alignd /banch, thn load/to Pad an unud intuchon with nop Add Intuction typ Piplin Stag n /banch IF ID EX MEM WB n + Load/to IF ID EX MEM WB n + 8 /banch IF ID EX MEM WB n + 12 Load/to IF ID EX MEM WB Hazad in th Dual- Iu MIPS Mo intuchon xcuhng in paalll EX data hazad Fowading avoidd tall with ingl- iu Now can t u ult in load/to in am packt add $t0, $0, $1 load $2, 0($t0) Split into two packt, ffchvly a tall Load- u hazad SHll on cycl u latncy, but now two intuchon Mo aggiv chduling quid n + 16 /banch IF ID EX MEM WB Schdul thi fo dual- iu MIPS Loop: lw $t0, 0($1) # $t0=aay lmnt addu $t0, $t0, $2 # add cala in $2 w $t0, 0($1) # to ult addi $1, $1, # dcmnt point bn $1, $zo, Loop # banch $1!=0 /banch Load/to cycl Loop: 1 Schdul thi fo dual- iu MIPS Loop: lw $t0, 0($1) # $t0=aay lmnt addu $t0, $t0, $2 # add cala in $2 w $t0, 0($1) # to ult addi $1, $1, # dcmnt point bn $1, $zo, Loop # banch $1!=0 /banch Load/to cycl Loop: nop lw $t0, 0($1) Schdul thi fo dual- iu MIPS Loop: lw $t0, 0($1) # $t0=aay lmnt addu $t0, $t0, $2 # add cala in $2 w $t0, 0($1) # to ult addi $1, $1, # dcmnt point bn $1, $zo, Loop # banch $1!=0 /banch Load/to cycl Loop: nop lw $t0, 0($1) 1 Schdul thi fo dual- iu MIPS Loop: lw $t0, 0($1) # $t0=aay lmnt addu $t0, $t0, $2 # add cala in $2 w $t0, 0($1) # to ult addi $1, $1, # dcmnt point bn $1, $zo, Loop # banch $1!=0 /banch Load/to cycl Loop: nop lw $t0, 0($1) 1 addi $1, $1, nop 2 addi $1, $1, nop 2 addu $t0, $t0, $2 nop

5 Schdul thi fo dual- iu MIPS Loop: lw $t0, 0($1) # $t0=aay lmnt addu $t0, $t0, $2 # add cala in $2 w $t0, 0($1) # to ult addi $1, $1, # dcmnt point bn $1, $zo, Loop # banch $1!=0 /banch Load/to cycl Loop: nop lw $t0, 0($1) 1 addi $1, $1, nop 2 addu $t0, $t0, $2 nop n IPC = 5/ = 1.25 (c.f. pak IPC = 2) Loop Unolling Rplicat loop body to xpo mo paalllim Rduc loop- contol ovhad U diffnt git p plicahon Calld git naming Avoid loop- caid anh- dpndnci Sto followd by a load of th am git Aka nam dpndnc Ru of a git nam bn $1, $zo, Loop w $t0, ($1) Loop Unolling Exampl /banch Load/to cycl Loop: addi $1, $1, 16 lw $t0, 0($1) 1 nop lw $t1, 12($1) 2 addu $t0, $t0, $2 lw $t2, 8($1) addu $t1, $t1, $2 lw $t, ($1) addu $t2, $t2, $2 w $t0, 16($1) 5 IPC = 1/8 = 1.75 Clo to 2, but at cot of git and cod iz addu $t, $t, $2 w $t1, 12($1) 6 nop w $t2, 8($1) 7 Dynamic MulHpl Iu Supcala poco CPU dcid whth to iu 0, 1, 2, ach cycl Avoiding tuctual and data hazad Avoid th nd fo compil chduling Though it may Hll hlp Cod manhc nud by th CPU bn $1, $zo, Loop w $t, ($1) 8 Dynamic Piplin Schduling Allow th CPU to xcut intuchon out of od to avoid tall But commit ult to git in od Exampl lw $t0, 20($2) addu $t1, $t0, $t2 ubu $, $, $t lti $t5, $, 20 Can tat ubu whil addu i waihng fo lw Why Do Dynamic Schduling? Why not jut lt th compil chdul cod? Not all tall a pdicabl.g., cach mi Can t alway chdul aound banch Banch outcom i dynamically dtmind Diffnt implmntahon of an ISA hav diffnt latnci and hazad 5

6 SpculaHon Gu what to do with an intuchon Stat opahon a oon a poibl Chck whth gu wa ight If o, complt th opahon If not, oll- back and do th ight thing Common to tahc and dynamic mulhpl iu Exampl Spculat on banch outcom (Banch PdicHon) Roll back if path takn i diffnt Spculat on load Roll back if locahon i updatd Piplin Hazad: Matching ock in lat load T a k d 6 PM AM A B C D E F bubbl A dpnd on D; tall inc fold Hd up; Tim ut- of- d Laundy: Don t Wait T a k 6 PM AM A B bubbl Tim C D d E F A dpnd on D; t conhnu; nd mo ouc to allow out- of- od ut f d Intl All u inc 2001 Micopoco Ya Clock Rat Piplin Stag Iu width ut-of-od/ Spculation Co i MHz 5 1 No 1 5W Pow Pntium MHz 5 2 No 1 10W Pntium Po MHz 10 Y 1 29W P Willamtt MHz 22 Y 1 75W P Pcott MHz 1 Y 1 10W Co MHz 1 Y 2 75W Do MulHpl Iu Wok? Th BIG Pictu Y, but not a much a w d lik Pogam hav al dpndnci that limit ILP Som dpndnci a had to liminat.g., point aliaing Som paalllim i had to xpo Limitd window iz duing intuchon iu Mmoy dlay and limitd bandwidth Had to kp piplin full SpculaHon can hlp if don wll And in Concluion.. Piplining i an impotant fom of ILP Challng i (a?) hazad Fowading hlp w/many data hazad Dlayd banch hlp with contol hazad in 5 tag piplin Load dlay lot / intlock ncay Mo aggiv pfomanc: Long piplin Supcala ut- of- od xcuhon SpculaHon 6

CS 61C: Great Ideas in Computer Architecture (Machine Structures) Instruc(on Level Parallelism: Mul(ple Instruc(on Issue

CS 61C: Great Ideas in Computer Architecture (Machine Structures) Instruc(on Level Parallelism: Mul(ple Instruc(on Issue CS 61C: Gat Ida in Comput Achitctu (Machin Stuctu) Intuc(on Lvl Paalllim: Mul(pl Intuc(on Iu Intucto: Randy H. Katz David A. PaGon hgp://int.c.bkly.du/~c61c/fa10 1 Paalll Rqut Aignd to comput.g., Sach