Michela Taufer CS:APP

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1 Michla Taufr CS:APP Powrpoint Lctur Nots for Computr Systms: A Prorammr's Prspctiv,. Bryant and D. O'Hallaron, Prntic Hall, 2003

2 Ovrviw 2 CISC 360 Faʼ08

3 al-world Piplins: Car Washs Squntial Paralll Piplind 3 CISC 360 Faʼ08

4 Computational xampl 300 ps 20 ps Combinational loic Dlay or latncy = 320 ps Throuhput = 3.12 GOPS Clock 4 CISC 360 Faʼ08

5 3-Way Piplind Vrsion 100 ps 20 ps 100 ps 20 ps 100 ps 20 ps loic A loic B loic C Dlay = 360 ps Throuhput = 8.33 GOPS Clock 5 CISC 360 Faʼ08

6 Piplin Diarams OP1 OP2 OP3 Tim OP1 OP2 OP3 A B C A B C A B C Tim 6 CISC 360 Faʼ08

7 Opratin a Piplin Clock OP1 OP2 OP3 A B C A B C A B C Tim 100 ps 20 ps 100 ps 20 ps 100 ps 20 ps loic A loic B loic C Clock 7 CISC 360 Faʼ08

8 Limitations: Nonuniform Dlays 50 ps 20 ps 150 ps 20 ps 100 ps 20 ps loic A loic B loic C Dlay = 510 ps Throuhput = 5.88 GOPS OP1 OP2 OP3 Clock A B C A B C A B C Tim Throuhput limitd by slowst sta Othr stas sit idl for much of th tim Challnin to partition systm into balancd stas 8 CISC 360 Faʼ08

9 Limitations: istr Ovrhad 50 ps 20 ps 50 ps 20 ps 50 ps 20 ps 50 ps 20 ps 50 ps 20 ps 50 ps 20 ps loic loic loic loic loic loic Clock Dlay = 420 ps, Throuhput = GOPS As try to dpn piplin, ovrhad of loadin ristrs bcoms mor sinificant Prcnta of clock cycl spnt loadin ristr: 1-sta piplin: 6.25% 3-sta piplin: 16.67% 6-sta piplin: 28.57% Hih spds of modrn procssor dsins obtaind throuh vry dp piplinin 9 CISC 360 Faʼ08

10 Data Dpndncis Combinational loic Clock OP1 OP2 OP3 Tim 10 CISC 360 Faʼ08

11 Data Hazards loic A loic B loic C OP1 A B C OP2 A B C OP3 A B C OP4 A B C Tim Clock sult dos not fd back around in tim for nxt opration Piplinin has chand bhavior of systm 11 CISC 360 Faʼ08

12 Data Dpndncis in Procssors 1 irmovl $50, %ax 2 addl %ax, %bx 3 mrmovl 100( %bx ), %dx sult from on instruction usd as oprand for anothr ad-aftr-writ (AW) dpndncy Vry common in actual prorams Must mak sur our piplin handls ths proprly Gt corrct rsults Minimiz prformanc impact 12 CISC 360 Faʼ08

13 SQ Hardwar nw Nw Stas occur in squnc On opration in procss at a tim Mmory Mm. control rad writ valm data out Data Addr Data Bch val xcut CC fun. A B vala valb dst dstm srca srcb dst dstm srca srcb Dcod A B M istr fil Writ back icod ifun ra rb valc Ftch Instruction incrmnt 13 CISC 360 Faʼ08

14 SQ+ Hardwar Mmory Mm. control rad writ valm data out Data Addr Data Bch val xcut CC fun. A B vala valb dst dstm srca srcb dst dstm srca srcb Dcod A B M istr fil Writ back icod ifun ra rb valc Ftch Instruction incrmnt picod pbch pvalm pvalc pvalp 14 CISC 360 Faʼ08

15 nw Nw valm Mmory Mm. control rad writ data out Data Addr Data Mmory Mm. control rad writ valm data out Data Addr Data Bch val xcut CC A B fun. xcut Bch CC A val B fun. vala valb dst dstm srca srcb dst dstm srca srcb vala valb dst dstm srca srcb Dcod icod ifun ra rb valc A B M istr fil Writ back Dcod A B M istr fil dst dstm srca srcb Writ back icod ifun ra rb valc Ftch Instruction incrmnt Ftch Instruction incrmnt picod pbch pvalm pvalc pvalp 15 CISC 360 Faʼ08

16 Addin Piplin istrs val, valm W_icod, W_valM Writ back valm valm W valm W_val, W_valM, W_dst, W_dstM Mmory Data Addr, Data Mmory M_icod, M_Bch, M_valA Data Addr, Data val M xcut Bch CC xcut Bch CC val alua, alub alua, alub vala, valb Dcod Ftch icod, valc icod, ifun ra, rb valc Instruction srca, srcb dsta, dstb incrmnt A B M istr fil Dcod Ftch D icod, ifun, ra, rb, valc Instruction d_srca, d_srcb vala, valb incrmnt A B M istr fil Writ back prd pstat f_ 16 CISC 360 Faʼ08 F

17 Piplin Stas W_icod, W_valM W W_val, W_valM, W_dst, W_dstM valm Mmory M_icod, M_Bch, M_valA Data Addr, Data M xcut Bch CC val alua, alub Dcod D d_srca, d_srcb vala, valb A B M istr fil Writ back icod, ifun, ra, rb, valc Ftch Instruction incrmnt prd f_ F 17 CISC 360 Faʼ08

18 Writ back PIP- Hardwar W icod Mmory M_Bch Mm. control val valm dst dstm data out rad Data writ data in Addr M_valA M icod Bch val vala dst dstm CC _Bch fun. xcut A B icod ifun valc vala valb dst dstm srca srcb Slct A d_rvala dst dstm d_srca d_srcb srca srcb Dcod A B M istr fil W_valM W_val D icod ifun ra rb valc Ftch Instruction f_ Slct incrmnt Prdict M_valA W_valM F prd 18 CISC 360 Faʼ08

19 W_icod, W_valM W_val, W_valM, W_dst, W_dstM Writ back Mmory M_icod, M_Bch, M_valA W valm Data Addr, Data W Mmory icod M_Bch Mm. control val valm dst dstm data out rad Data writ data in Addr M_valA M M icod Bch val vala dst dstm xcut Bch CC alua, alub val xcut CC _Bch A B fun. icod ifun valc vala valb dst dstm srca srcb Dcod D d_srca, d_srcb vala, valb A B M istr fil Writ back Dcod Slct A d_rvala A B M istr fil dst dstm d_srca d_srcb srca srcb W_valM W_val Ftch icod, ifun, ra, rb, valc Instruction incrmnt f_ prd D Ftch icod ifun ra rb Instruction f_ Slct valc incrmnt Prdict M_valA W_valM F F prd 19 CISC 360 Faʼ08

Writ back Fdback Paths W icod Mmory M_Bch Mm. control val valm dst dstm data out rad Data writ data in Addr M_valA M icod Bch val vala dst dstm CC _Bch fun.

20 Writ back Fdback Paths W icod Mmory M_Bch Mm. control val valm dst dstm data out rad Data writ data in Addr M_valA M icod Bch val vala dst dstm CC _Bch fun. xcut A B icod ifun valc vala valb dst dstm srca srcb Slct A d_rvala dst dstm d_srca d_srcb srca srcb Dcod A B M istr fil W_valM W_val D icod ifun ra rb valc Ftch Instruction f_ Slct incrmnt Prdict M_valA W_valM F prd 20 CISC 360 Faʼ08

Prdictin th D icod ifun ra rb valc Prdict M_icod M_Bch M_valA W_icod W_valM Instr valid Nd valc Nd rids incrmnt Split Alin Byt 0 Byts 1-5 Instruction Slct F prd Start ftch of nw

21 Prdictin th D icod ifun ra rb valc Prdict M_icod M_Bch M_valA W_icod W_valM Instr valid Nd valc Nd rids incrmnt Split Alin Byt 0 Byts 1-5 Instruction Slct F prd Start ftch of nw instruction aftr currnt on has compltd ftch sta Not nouh tim to rliably dtrmin nxt instruction Guss which instruction will follow covr if prdiction was incorrct 21 CISC 360 Faʼ08

22 Our Prdiction Straty 22 CISC 360 Faʼ08

covrin from Misprdiction D Instr valid icod ifun ra rb valc Nd valc Nd rids incrmnt Prdict M_icod M_Bch M_valA W_icod W_valM Split Alin Byt 0 Byts 1-5 Instruction Slct

23 covrin from Misprdiction D Instr valid icod ifun ra rb valc Nd valc Nd rids incrmnt Prdict M_icod M_Bch M_valA W_icod W_valM Split Alin Byt 0 Byts 1-5 Instruction Slct F prd Misprdictd Jump Will s branch fla onc instruction rachs sta Can t fall-throuh from vala turn Instruction Will t rturn whn rt rachs writ-back sta 23 CISC 360 Faʼ08

24 Piplin Dmonstration irmovl $1,%ax #I F D M irmovl $2,%cx #I2 F D M irmovl $3,%dx #I3 F D M W irmovl $4,%bx #I4 F D M W halt #I5 F D M W F I5 24 CISC 360 Faʼ08 W Cycl 5 W I1 M I2 I3 D I4 W

25 Data Dpndncis: 3 Nopʼs F D M W 0x006: irmovl $3,%ax F D M W 0x00c: nop F D M W 0x00d: nop F D M W 0x00: nop F D M W 0x00f: addl %dx,%ax F D M W 0x011: halt F D M W # dmo-h3.ys 0x000: irmovl $10,%dx Cycl 6 W [%ax] 3 Cycl 7 D vala [%dx] = valb [%ax] CISC 360 = 3 Faʼ08

26 Data Dpndncis: 2 Nopʼs # dmo-h2.ys x000: irmovl $10,%dx F D M W 0x006: irmovl $3,%ax F D M W 0x00c: nop F D M W 0x00d: nop F D M W 0x00: addl %dx,%ax F D M W 0x010: halt F D M W Cycl 6 W [%ax] 3 D vala [%dx] = 10 valb [%ax] = 0 rror 26 CISC 360 Faʼ08

27 Data Dpndncis: 1 Nop # dmo-h1.ys 0x000: irmovl $10,%dx F D M W 0x006: irmovl $3,%ax F D M W 0x00c: nop F D M W 0x00d: addl %dx,%ax F D M W 0x00f: halt F D M W Cycl 5 W [%dx] 10 M M_val= 3 M_dst= %ax rror vala [%dx] = 0 27 valb [%ax] = 0 CISC 360 Faʼ08 D

28 Data Dpndncis: No Nop # dmo-h0.ys 0x000: irmovl $10,%dx F D M W 0x006: irmovl $3,%ax F D M W 0x00c: addl %dx,%ax F D M W F D M W 0x00: halt Cycl 4 M M_val= 10 M_dst= %dx _val = 3 _dst= %ax D vala [%dx] = 0 valb [%ax] = 0 rror 28 CISC 360 Faʼ08

29 Branch Misprdiction xampl dmo-j.ys 0x000: xorl %ax,%ax 0x002: jn t # Not takn 0x007: irmovl $1, %ax # Fall throuh 0x00d: nop 0x00: nop 0x00f: nop 0x010: halt 0x011: t: irmovl $3, %dx # Tart (Should not xcut) 0x017: irmovl $4, %cx # Should not xcut 0x01d: irmovl $5, %dx # Should not xcut Should only xcut first 8 instructions 29 CISC 360 Faʼ08

30 Branch Misprdiction Trac # dmo-j x000: xorl %ax,%ax F D M W 0x002: jn t # Not takn F D M W 0x011: t: irmovl $3, %dx # Tart F D M W 0x017: irmovl $4, %cx # Tart+1 F D M W 0x007: irmovl $1, %ax # Fall Throuh F D M W Incorrctly xcut two instructions at branch tart Cycl 5 M M_Bch = 0 M_valA = 0x007 val 3 dst = %dx D valc = 4 dst = %cx F valc 1 30 rb %ax CISC 360 Faʼ08

31 turn xampl dmo-rt.ys 0x000: irmovl Stack,%sp # Intializ stack pointr 0x006: nop # Avoid hazard on %sp 0x007: nop 0x008: nop 0x009: call p # Procdur call 0x00: irmovl $5,%si # turn point 0x014: halt 0x020:.pos 0x20 0x020: p: nop # procdur 0x021: nop 0x022: nop 0x023: rt 0x024: irmovl $1,%ax # Should not b xcutd 0x02a: irmovl $2,%cx # Should not b xcutd 0x030: irmovl $3,%dx # Should not b xcutd 0x036: irmovl $4,%bx # Should not b xcutd 0x100:.pos 0x100 0x100: Stack: # Stack: Stack pointr quir lots of nops to avoid data hazards 31 CISC 360 Faʼ08

32 Incorrct turn xampl # dmo-rt 0x023: rt F D M W 0x024: irmovl $1,%ax # Oops! F D M W 0x02a: irmovl $2,%cx # Oops! F D M W 0x030: irmovl $3,%dx # Oops! F D M W 0x00: irmovl $5,%si # turn F D M W Incorrctly xcut 3 instructions followin rt W valm = 0x0 M val = 1 dst = %ax val 2 dst = %cx D valc = 3 dst = %dx F 32 valc 5 rb %si CISC 360 Faʼ08

33 Piplin Summary 33 CISC 360 Faʼ08

CS:APP Chapter 4 Computer Architecture Pipelined Implementation

CS:APP Chapter 4 Computer Architecture Pipelined Implementation CS:APP Chaptr 4 Computr Architctur Piplind Implmntation CS:APP2 Ovrviw Gnral Principls of Piplinin n Goal n Difficultis Cratin a Piplind Y86 Procssor n arranin SEQ n Insrtin piplin ristrs n Problms with