Low-Latency SC Decoder Architectures for Polar Codes

Transcription

1 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < ow-atncy SC codr Architcturs for Polar Cods Chuan Zhang, Bo Yuan, and Kshab K. Parhi, Fllow, IEEE Abstract owadays polar cods ar bcoming on of th most favorabl capacity achiving rror corrction cods for thir low ncoding and dcoding complxity. Howvr, du to th larg cod lngth ruird by practical applications, th fw xisting succssiv cancllation (SC dcodr implmntations still suffr from not only th high hardwar cost but also th long dcoding latncy. This papr prsnts novl svral approachs to dsign low-latncy dcodrs for polar cods basd on look-ahad tchnius. ook-ahad tchnius can b mployd to rschdul th dcoding procss of polar dcodr in numrous approachs. Howvr, among thos approachs, only wll-arrangd ons can achiv good prformanc in trms of both latncy and hardwar complxity. By rvaling th rcurrnc proprty of SC dcoding chart, th authors succd in rducing th dcoding latncy by 5% with look-ahad tchnius. With th hlp of VSI-SP dsign tchnius such as piplining, folding, unfolding, and paralll procssing, mthodologis for four diffrnt polar dcodr architcturs hav bn proposd to mt various application dmands. Sub-structur sharing schm has bn adoptd to dsign th mrgd procssing lmnt (PE for furthr hardwar rduction. In addition, systmatic mthods for construction rfind piplining dcodr ( nd dsign and th input gnrating circuits (ICG block hav bn givn. taild gat-lvl analysis has dmonstratd that th proposd dsigns show latncy advantags ovr convntional ons with similar hardwar cost. Indx Trms Polar cods, look-ahad, piplining, folding, unfolding, paralll procssing. I. ITROUCTIO TROUCE by Arıkan rcntly [], polar cods hav Ishown th capabilitis to achiv th symmtric capacity I(W of any givn binary-input discrt mmorylss channl (B-MC W. Considrd as th first low complxity schm which provably achivs th capacity for a fairly wid array of channls, polar cods hav bcom on of th most favorabl rsarch topics. By rcursivly combining and splitting th copis of B-MC, w obtain a scond channl W, which is ( composd of W i with i. Among thos nwly constructd channls, only thos with highst capacity ar usd for data transmission. W rfr outputs of ths channls as information bits, and th st of corrsponding indics as. Also th outputs of th othr channls ar dnotd as frozn bits, and ths channls indics mak up th st c. Manuscript rcivd Sptmbr,. Authors ar with partmnt of Elctrical and Computr Enginring, Univrsity of Minnsota, Twin Citis (U of M, USA. {zhan4, yuan, parhi}@umn.du. Although a grat dal of rsarch ffort has bn xpndd in study of polar cods, most of th rsarch is focusd on cod prformanc rathr than th dsign of high fficincy dcodrs. Shown in [], th straightforward polar dcodr implmntation with succssiv cancllation (SC algorithm rsults in th complxity of O(log. A simpl implmntation approach basd on blif propagation (BP algorithm was proposd by th sam author in []-[]. Howvr, du to its lowr complxity compard with BP algorithm, th SC approach appars mor attractiv for hardwar dsignrs. Thrfor, a rducd SC dcodr with complxity of O( was givn by []. For th dcoding of a polar cod with lngth of, totally (- clock cycls ar ruird by th dcodr. And in ach activ stag, th highst hardwar fficincy can b only 5%, which mans mor than half procssing lmnts (PEs ar idl at th sam tim. This is bcaus th stimation of th currnt bit also dpnds on th prvious codd bit, which forcs all codd bits to b output succssivly. In ordr to achiv fastr dcoding, th loop computation can b rformulatd basd on look-ahad tchnius, which pr-calculat all possibl outputs of th nxt cod bit and thn slct th corrct on with a multiplxr. Howvr, among all possibl candidats, only th on with short latncy and low hardwar complxity can b slctd. This papr addrsss on nic rcursiv tim chart construction mthod which succds in rducing th dcoding latncy with look-ahad tchnius in any cass. By mploying dsign tchnius such as piplining, folding, unfolding, and paralll procssing, svral gnral dsign mthods for polar dcodrs ar prsntd accordingly. Bnfitting from th fficint ral FFT procssor architctur in [4], th input gnrating circuits (ICG block is proposd to can gnrat all slctiv signals on th fly. Along with th rducd-complxity mrgd PE, all gat-lvl dsign dtails for proposd polar dcodrs ar wll illustratd. Comparison rsults hav shown that ach dsign approach givn in this papr is abl to achiv only half dcoding latncy whil consums comparabl hardwar as th convntional ons, which is attractiv for high spd ral-lif applications. Th rmaindr of this papr is organizd as follows. A brif rviw of SC dcoding algorithm and its logarithm domain variants ar providd in Sction II. In Sction III, th convntional dcoding tim chart is rgnratd with rcurrnc rlationship. And th systmatic algorithm to construct th look-ahad schduling schm is givn in a rcursiv mannr. Th corrsponding latncy-rducd polar dcodr architctur

2 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < ( st dcodr and its sub-blocks, such as th mrgd PE and th ICG modul is discussd in block Sction IV. In Sction V, basd on th on givn in Sction IV thr modifid dcodrs ar prsntd, which mploy unfolding ( nd dcodr, folding ( rd dcodr, and paralll procssing tchnius (4 th dcodr, rspctivly. Th nd dcodr architctur is compatibl with M conscutiv inputs procssing. Th rd on tim-multiplxs all dcoding oprations on a singl PE stag. Using th sam numbr of PEs as th rd on, th 4 th dcodr manags to implmnt -paralll procssing at th pric of an additional clock cycl. It is obvious to s that compard with th st dsign, ach variant improvs th hardwar fficincy whil kps th sam low-latncy advantag. Th corrsponding prformanc stimation and comparison with stat-of-th-art dsigns ar prsntd in Sction VI. Sction VII concluds th papr. II. REVIEW OF SC AGORITHM A ITS VARIATS In this sction, w provid th prliminaris of th SC dcoding algorithm. Morovr, som variants and simplifid modifications of th SC algorithm ar xplaind as wll. A. SC coding Algorithm Considr an arbitrary polar cod with paramtr (, K,, u c []. W dnot th input vctor as u, which consists of a random part u and a frozn part u c. Th corrsponding output vctor through channl W is y with conditional probability ( W y u. fin th liklihood ratio (R as, ( i i ( i i W ( y, u ( y, u. ( ( i i W ( y, u Th a postriori dcision schm is givn as follows, A Postriori cision Schm with Frozn Bits c : if i thn u i= ui; : ls ( i i : if ( y, u thn ui=; 4: ls u i=; 5: ndif 6: ndif It is notd that Rs with vn and odd indics can b gnratd by applying th rcursiv formulas givn by E. ( and (, rspctivly: ( i i ( y, u ( i i i ui ( i i ( =[ ( y, u ] ( y, u,, o, +, (i- i (, ( i ( (, i i,, i (, i y u o u y + u, + ( i i i ( i i ( y, u, o u, + ( y +, u, i (, i y u =. Obviously, th calculation of ( y u dpnds on th stimation of th prvious bit, from which th SC dcoding algorithm is namd. For th as of clar xplanation, th dcoding procdur of a polar cod with = is illustratd in Fig., whr Typ I and Typ II PEs ar in charg of computations givn in E. ( and (, rspctivly. And th ( labl attachd to ach PE indicats th indx of clock cycl whn th corrsponding PE is activatd. ( ( y ( y, u ( ( (, y u ( y, u ( 7 6 ( y, u ( ( 6 5 (, y u 7 ( 4 (, y u 4 ( y, u ( 7 4 û û 5 û û 7 stag stag stag û û : Typ I PE : Typ II PE û Figur : SC dcoding procss of polar cods with lngth =. ( ( ( ( 4 ( 5 ( 6 ( 7 ( B. SC coding Algorithm in ogarithm omain For any gnral dcoding algorithm, its variant dfind in logarithm domain always has advantags in trms of hardwar implmntation, computational complxity, and numrical stability ovr th on in ral domain. Thrfor, similar to th approach addrssd in [5], th SC algorithm daling with logarithm-liklihood ratio (R was mntiond by []. E. (4 and (5 can thn b rwrittn as follows: ( i i ( y, u i ( ( =(- u i (, i i y u u i ( y, u i (4 +,, o, +, (i- i ( y, u ( i i i =artanh{tanh[ ( y, u, o u, ] (5 ( i i tanh[ ( y +, u, ]}. Hr th Rs ar dfind as: ( i i ( i i ( y, ln ( y, u. (6 C. Min-Sum SC coding Algorithm In ordr to implmnt th hyprbolic tangnt function and its invrs function in E. (5, larg amount of look-up tabl (UT is ruird. ot that in logarithm domain, for variabl x, th following approximation holds: ln[cosh( x] x ln. (7 Consuntly, E. (5 can b rducd to th min-sum updat rul, which is UT fr: (i- i ( y, u ( i i i ( i i ( y, u, o u, + ( y +, u, ( i i i ( i i ( y, u, o u, ( y +, u, ( ( i i i ( i i = sgn[ ( y, u, o u, ]sgn[ ( y +, u, ] ( i i i ( i i min[ ( y, u, ( y, u ]., o, +, Simulation rsults hav dmonstratd that th min-sum SC dcoding algorithm only suffrs from littl prformanc dgradation than th optimal on whil achivs a good hardwar fficincy []. This proprty maks min-sum SC

3 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < dcoding algorithm vry attractiv for VSI implmntation. Thrfor, in th following sctions w will discuss th polar dcodr dsign basd on this sub-optimal algorithm. Howvr, among all thos dcoding algorithms pr-statd, probabilitis ar updatd according to th sam data flow illustratd in Fig., which is straightforward but not fficint nough. In th nxt sction, w prsnt our high-prformanc schm for polar dcodr dsign. In th proposd schm, compard to th schms prsntd abov, th numbr of clock cycls ruird for obtaining th stimatd information bits has bn rducd by 5%. Morovr, this latncy-rducd schm is suitabl for any cod lngth, and can b gnratd in a nic rcursiv mannr. III. PROPOSE ATECY-REUCE UPATIG SCHEME FOR POAR ECOER ESIG In what follows, w prsnt a latncy-rducd updating schm for polar dcodrs basd on a novl look-ahad schduling mthod. Th proposd tchnius nd fwr numbr of clock cycls to prform th sam opration as th convntional SC dcoding algorithm, lading to lowr dcoding latncy. For th straightforward SC dcoding implmntation of -bit polar cods, totally (- clock cycls ar ruird. Carful invstigation has shown that th corrsponding tim chart can b constructd in rcursiv way, which is dscribd by th following psudo-cods. In an ffort for concisnss, in th rst of this papr, th notation TC = {[,TC], s} is usd for th lft insrtion of an array into th prviously arrangd tim chart TC at Stag s. Similarly, TC = [TC,TC] simply mans duplication of prvious tim chart. Rcursiv Construction of Convntional Tim Chart : initializtion TC= ; : for i= log i,,do : j = log i+ ; 4: TC = {[ jof Typ I,TC], i} ; 5: TC = [TC,TC]; 6: chang th lftmost jof Typ I with jof Typ II; 7: ndfor : output TC. Hr, i and j ar indics of itrativ xcution. j of Typ I is th short for j copy (or copis of Typ I PE(s. Basically, Stag i will b activatd i tims during th whol dcoding procss. Thrfor, th total numbr of clock cycls ruird can b calculatd as follows: log log i ( = = (, (9 i= which matchs th gnral conclusion givn bfor. According to Fig., it can b obsrvd that ach PE is activatd only onc during th ntir dcoding procss. In on spcific clock cycl only singl typ of PE is activ. Th output Rs will b gnratd th sam clock cycl in which th log -th stag is activ. For as of clar xplanation, th polar dcoding procss shown in Fig. is mployd for dtaild illustration. Sinc block lngth =, according to E. (9 totally 4 clock cycls ar ruird to finish th whol dcoding procss. Th corrsponding dcoding tim chart is givn in Fig. (a. Howvr, this convntional dcoding approach is not suitabl for practical applications for th following two rasons. First, in ordr to achiv ruird dcoding prformanc, th cod lngth is usually st to b as larg as -. An immdiat consunc is th latncy of (- clock cycls is too larg. Scond, according to Fig. (a, it is apparnt that during th whol dcoding procss th highst hardwar utilization in a spcific clock cycl is only 5% (Clock cycl. As th stag indx incrass, th hardwar fficincy will go down as low as.5%. For gnral cas with cod lngth of, th minimum hardwar fficincy for activ stag is / (Clock cycl log. Sinc only polar cods with cod lngth gratr or ual than can achiv a good prformanc that approaching th channl capacity, th straightforward implmntation in Fig. bcoms impractical for ral-lif applications bcaus th lowst hardwar usag can b around -. Evn for th piplind tr architctur proposd by [] in Fig., th highst utilization is only 5% as wll, which mans half PEs ar in idl stat during ach clock cycl. ( y, u i ( i ( y, u ( i i Stag Stag Stag : Typ I PE : Typ II PE : Piplin ( ( ( ( 4 ( 5 ( 6 ( 7 ( Figur : Piplind dcodr architcturs of polar cods with lngth =. This dilmma is introducd by th bottlnck of suntial dcoding proprty of SC algorithm. In ordr to addrss this issu proprly, th computation loop can b r-schduld with look-ahad tchnius. Howvr, in ordr to achiv th goal of low latncy and high prformanc, th nw dcoding schdul nds to b carfully chosn. It is notd that if both th two R inputs for E. (5 ar availabl, thr ar only two possibl outputs. Thrfor, for any Typ I PE, givn two dtrministic R inputs, th look-ahad schm only nds to pr-comput two output candidats. Th corrct output can b slctd by a multiplxr thraftr. For th instanc shown in Fig., all possibl outputs of Typ I PEs labld by in Stag can b pr-calculatd in Clock cycl. In othr words, for Stag th ruird computation in Clock cycl can b incorporatd into

4 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < 4 Clock Stag 4 of Typ II 4 of Typ I Stag of Typ I of Typ of Typ I of Typ I Stag of Typ II of Typ I of Typ II of Typ I of Typ II of Typ I of Typ II of Typ I Output ( ( y ( y, u ( ( y, u ( ( y, u ( 4 (a ( y, u ( 5 4 ( y, u ( 6 5 ( y, u ( 7 6 ( y, u ( 7 Clock Stag Stag Stag Output of Typ I & II of Typ I & I of Typ I & II of Typ I & II of Typ I & II of Typ I & II of Typ I & II & & 4 5 & 6 7 & ( y, ( y, u ( ( ( y, u, ( y, u ( ( 4 ( y, u, ( y, u ( 5 4 ( 6 5 ( y, u, ( y, u ( 7 6 ( 7 (b Figur : Convntional and look-ahad dcoding tim charts for polar cods with =. Clock cycl. In th similar way, for Stag computation in Clock cycl 5 and can b takn car of in Clock cycl and 9, rspctivly. Calculation in Clock cycl 4, 7,, and 4 can b r-schduld into Clock cycl, 6,, and for Stag. As a rsult, only half clock cycls ar ruird to implmnt th sam dcoding task with th hlp of th proposd look-ahad schdul. In gnral cas, only th PE s with two dtrministic R inputs can b activatd in a crtain clock cycl. If th corrsponding PE is catgorizd into Typ I, both two possibl rsults ar pr-calculatd. Othrwis, if th corrsponding PE falls into th catgory of Typ II, th uniu output is drivd dirctly and thn propagatd to th nxt stag. For th -bit polar dcodr xampl, all PEs at Stag ar activatd during Clock cycl bcaus both dtrministic R inputs for ach PE ar guarantd by channl outputs. Howvr, in Clock cycl, only PEs labld with and 5 can b activatd, bcaus thy ar th only ons with dtrministic R inputs. For PEs with labls of 9 and, thir R inputs ar gnratd by Typ I PEs in Stag, which hav two possibl valus at this momnt. In ordr to avoid rror propagation causd by pr-computing to th nxt stag, thos PEs stay idl during Clock cycl. Similar schms apply to furthr dcoding procsss. Thrfor, th wll schduld look-ahad dcoding procdur is obtaind by folding th straightforward tim chart into half, which is illustratd by Fig. (b. It is clar that in ordr to dcod polar cods with lngth, th ruird numbr of clock cycls can b halvd to -. Th tim chart construction of th proposd nw schm is givn by th following psudo cods. As indicatd in Stp 4 of th givn construction mthod, bnfit from th look-ahad tchnius both typs of PEs can work simultanously in th sam clock cycl, which not only shortns th dcoding latncy by 5% but also improvs th hardwar fficincy twic. Morovr, th proposd approach succd in giving th construction mthod in a rcursiv way. For clar undrstanding of th Russian oll-lik rlationship btwn stags, both convntional and look-ahad construction procsss hav bn pointd out with arrows. Rcursiv Construction of ook-ahad Tim Chart : initializtion TC= ; : for i= log i,,do : j = log i+ ; 4: TC = {[ jof Typ I & II,TC], i} ; 5: if i = thn 6: brak; 7: ndif : TC = [TC,TC]; 9: ndfor : output TC. IV. ARCHITECTURES FOR PROPOSE OOK-AHEA ECOER In this sction, w prsnt th dtaild hardwar architcturs of th proposd latncy-rducd SC polar dcodr using look-ahad tchnius. It is known that th oprations in SC dcoding blong to two catgoris, which ar xcutd by Typ I and Typ II PEs, rspctivly. In othr words, implmnting th dcodr in hardwar coms down to th dsign of two lmntary lmnts. According to th Min-Sum SC dcoding algorithm, both lmntary lmnts ar associatd with addition and comparison oprations, which provids us with facilitis to carry out furthr optimization using sub-structur sharing tchnius. ow-complxity structurs for both two typs of PEs ar proposd in th rst of this sction. Morovr, an optimizd architctur for th input gnrating circuit (IGC is drivd as wll. A. sign of Typ I PE According to th look-ahad schm, Typ I PE is in charg of pr-computing two possibl outputs. In ordr to incorporat both capabilitis of adding or subtracting oprands togthr, an addr-subtractor architctur is mployd by Typ I PE. For th sak of clarity, it is supposd that -bit uantization is adoptd hr.

5 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < 5 C X- Y- B -bit full B- B -bit full -bit addr full -bit addr full addr addr S- - C- C X S Y C B X Y -bit full -bit addr full addr Figur 4: -bit addr-subtractor architctur. S C X Y -bit full -bit half addr addr B As shown in Fig.4, in ordr to avoid larg procssing latncy, paralll implmntation is mployd hr. Howvr, simpl duplication rsults in pnalty of doubling both ara and powr. For a -bit addr-subtractor, totally - -bit full addr and on -bit half addr ar ruird. In ordr to implmnt Typ-I PE mor ffctivly, th novl architctur of addr-subtractor is proposd in this sction. Rathr than implmnting Typ-I PE with two s complmnt approach, th original carry-borrow ida is mployd hr. Suppos X and Y ar th two oprands, and Z in is th carrid-in or borrowd-from bit. For th full addr th two outputs of summation and carry-out ar rprsntd by S and C out, rspctivly. In similar way, th diffrnc and borrow-out producd by th full subtructor ar dnotd with and B out. Thrfor, th truth tabl for th full addr and subtractor is givn blow. S hardwar complxitis ar convrtd in th form of uivalnt XOR gat numbr. According to Fig. 5, th complxitis of -bit full and half addr-subtractor ual to 4 XOR gats and XOR gat, rspctivly. Compard with th straightforward ons, th total savings of th proposd approachs ar 4% and 5%, rspctivly. Composd of - -bit full addr-subtractor and a -bit half addr-subtractor, th gnral -bit addr-subtractor architctur with th givn dsign mthod ruirs only lss than 57% hardwar compard with th convntional on whil achivs xactly th sam prformancs. B out S C out (a -bit full addr-subtractor. B out S X Y B in X Y C in TABE I TRUTH TABE OF BOTH FU AER A SUBTRACTOR Inputs Outputs Addr Subtructor X Y Zin S Cout B From Tabl I on can draw th Karnaugh map for all outputs basd on which th logic uations ar drivd as follows: S = X Y Z ; ( in C = X Y + ( X Y Z ; ( out = X Y Z ; ( in B = X Y + X Y Z. ( out in It is obvious that outputs S and ar actually th sam. And asy to notic that X Y is an intrmdiat trm of X Y. Similarly, ( X Y Zin can b tratd as a byproduct of trm X Y Z in as wll. Sinc both outputs C out and B out can b calculatd by rcursivly mploying th A or A-OT opration twic, thy can b obtaind simultanously with othr two outputs. Th rsultd gat-sharing tchnius can not only implmnt paralll procssing but also rduc th hardwar consumption. Th proposd gat-lvl structurs of -bit full and half addr-subtractor ar dpictd in Fig. 5 (a and (b rspctivly, whr th carry-in bit C in and borrow-out bit B in ar supposd to b diffrnt rathr than in th uniu form of Z in. For th sak of asy stimation and comparison, all th in out C out (b -bit half addr-subtractor. Figur 5: Proposd -bit addr-subtractor architcturs. Without bing misundrstood, it is agrd that hrinaftr th nwly proposd Typ I PE illustratd in Fig. 6 is still rfrrd to as Typ I PE. Th Typ I PE with th convntional architcturs will not b mployd or discussd any mor. B C X- S- Y- -bit full addrsubtractor - B- C- B C B. sign of Typ II PE X S Y -bit full addrsubtractor B C X S Y -bit half addrsubtractor Figur 6: Proposd Typ I PE architcturs. X Y Typ I PE sgn output input sgn TtoS mag StoT input CMP mag TtoS Typ II PE ( i i input (, +, ; : y u ( i i i input (, : y u, o u, ; output: ( i- i (, y u. Figur 7: Proposd architcturs of Typ II PE. Instad of implmnting tanh and artanh functions, Typ II PE which mploys th min-sum algorithm is shown in Fig.7. TtoS block will prform th convrsion from two s complmnt S

6 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < 6 rprsntation to sign-magnitud rprsntation. StoT block will prform th rvrs convrsion. Th TtoS block is illustratd in Fig.. In ordr to avoid th ovrflow situation, a sign xtnsion opration is ruird as wll. I- -bit half addr C- C I -bit half addr C I -bit half addr C I -bit half addr C Typ I PE to procss th computation. Morovr, for fficint xcution of ach Typ I PE, th valu of u i nds to b providd on th fly. Howvr, vn for th -bit dcodr illustratd in Fig., th complicatd intrlaving of odd and vn indics maks th straightforward calculation of u i inconvnint. In ordr to solv this inhrnt problm, th input gnrating circuit (IGC for Typ I PEs is proposd in this sction. Carful invstigation has shown that it is possibl to gnrat th ruird u i using th ral FFT-lik signal flow. For an instanc, all th xtra input valus u i for -bit polar cod dcodr can b asily gnratd according to th following in-plac procdur. O O- O Figur : Proposd structur of TtoS block. Th StoT block is similar to th TtoS block. Th only diffrnc is that a sign comprssion opration is ndd to mak th output data in th form of th -bit uantization. C. Sub-structur Sharing of Typ I and Typ II PEs Sinc th comparator in Typ II PE is actually a -bit subtractor, which is also mployd by Typ I PE, it is possibl to incorporat both Typ I and Typ II PEs togthr using th sub-structur sharing schm. Th dtaild structur is illustratd as follows: O O u u u u4 u5 u6 u7 u Stag u 4 u4 5 6 u6 7 u Stag u u output output output Mrgd PE StoT StoT StoT S Bn sgn sgn Typ I PE mag mag TtoS TtoS input input : XOR opration : PASS opration Figur : Flow graph of IGC for -point polar dcodr. Hr, th pass opration procss lmnt only lts th lowr input gt through. According to Fig., th flow graph can b furthr simplifid with th proprtis xplaind as follows: input : ( y, u ; output : ( y,, u = ; input : (, ; output : (, =. output : ( i i ( i- i +, i ( i i i ( i- i y u, o u, y u, ui ( i- i (, y u ; Figur 9: Proposd structur of th Mrgd PE. In th Mrgd PE, th comparison opration is carrid out by th Typ I PE illustratd Fig. 6. Two mor StoT blocks as wll as additional control logic ar ruird hr. According to Fig. 9, for -bit uantization schm totally - XOR gats can b savd by th proposd sub-structur sharing approach. As mntiond prviously, usually cod lngth ovr is a must for polar cods to achiv ruird dcoding prformancs in practical applications. For convntional piplind tr polar dcodr architcturs, - Mrgd PEs can b mployd instad of - Typ I PEs and Typ II PEs, rspctivly. As a consunc, th rsultd hardwar saving could b around (- XOR gats.. Input Gnrating Circuit for Typ I PEs As indicatd in E. (5, xcpt for ( i (, i, i y u o u, ( i i and ( y +, u,, anothr input u i is also ruird by. Th first simplification is to considr that all outputs which ar associatd with inputs u ar not ncssary. Consuntly, th shadd rgion can b rmovd. Similar concpt can b applid to th gnral cas of inputs. For any Stag i, its lowr rgion which contains i procss lmnts (PEs, can b rmovd. For xampl, th lowr PEs of Stag and th lowr 4 PEs of Stag ar rmovd from th flow graph in Fig.. Thrfor, only (/(log - outputs nd to b computd.. Th scond simplification rfrs to th fact that th PASS opration lmnt can b rplacd by th wir connction whil th flow graph stays functionally th sam. According to Fig., lmnt only allow th lowr input through to th nxt stag. Thus, if th uppr tokn is not tratd as an input to lmnt any mor, on simpl wir which conncts th lowr tokn and th output can b mployd instad. Manwhil, complxity of th flow graph can b halvd with rspct to th formr on. Th rsultd simplifid data flow graph is givn in Fig.. Both proprtis hav bn fully utilizd. It is asy to s that totally log - stags ar ruird and th numbr of XOR

7 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < 7 oprations is calculatd blow: [ (log ( ( ] u u u u4 u5 u6 = (log +. Stag u 4 u4 5 6 u6 Stag Figur : Simplifid flow graph of th proposd IGC. u4 (4 In addition, it is worthwhil to not that with th hlp of gnrator matrix G [], th sam simplifid flow graph can b obtaind as wll. W dfin to b th matrix Kronckr product and n uals log. Thn th gnrator matrix G is givn by th following uation: n n G = B F = F B, (5 whr B is th bit-rvrsal prmutation matrix and F matrix is dfind as: F. (6 Th piplind architctur of th simplifid flow graph illustratd in Fig. can b implmntd with th following fd-forward architctur, whr totally two XOR-pass lmnts ar ruird. u i u i Stag Stag Figur : Piplind fd-forward architctur for -bit IGC. Easily to obsrv that th proposd piplind architctur is only suitabl for srial inputs. Howvr, as indicatd by th tim chart illustratd in Fig. (b, vry two dcodd bits ar output in th sam clock cycl. In ordr to work compatibly with this schdul, th architctur nds to b modifid to mak itslf a -lvl paralll procssing structur, which is shown in Fig. 4. Th control bit c is changd with th clock flipping mannr and its initial valu is st to b. By unfolding th i-th stag with th unfolding factor of i-, th updatd input gnrating circuit is abl to crat i outputs at th sam tim, which th original circuit dos in i- conscutiv clock cycls. For xampl, th unfoldd vrsion of th circuit shown in Fig. is givn as follows, whr U i dnots th unfoldd piplind architctur which is consists of i stag(s: outputs u i u i Stag c Stag U U Figur 4: Unfoldd vrsion of piplind architctur in Fig.. In gnral, for -bit lngth dcodr, sinc th data structurs of IGC ar dfind rcursivly for powrs of, th unfoldd piplind architctur can b constructd with th rcurrnc rlationship. Th rcursion for th gnral cas is shown in Fig. 5, whr modul U n can b constructd basd on modul U n- and /4 xtra XOR-pass lmnts. Hr, w hav n = log -. And th control bit c n can b obtaind by down sampling c by a factor of n. u i u i U n- c n U n Stag n n- - n- - n- - Figur 5: Rcursiv construction of U n basd on U n-. Thrfor, th total numbr of XOR-pass lmnts can b calculatd as: u i u i U n- n i= c n 4 outputs / outputs i =. (7 U n Stag n RAM n addr. Figur 6: Rcursiv construction of U n basd on U n- using RAMs. / outputs Also it is asy to s that th sam amount of dmultiplxrs is ruird. Finally, as what w xpct, th obtaind piplind

8 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < structur works bst with th proposd tim chart, which nabls all intrmdiat rsults to b gnratd in plac without any xtra clock cycls. Howvr, it can b noticd that for Stag i, th numbr of corrsponding rgistrs incrass with th complxity of i, which is obviously impractical for polar cods of lngth ovr. On possibl approach is to mploy mmory banks instad of flip-flops, which is shown in Fig. 6. For RAM i, totally i- mmory lmnts ar ruird. And th data liftim is i- - clock cycls, according to which th mmory nabl signals can b thrfor dtrmind. E. Piplind Architctur of th ook-ahad codr Taking th advantag of th pr-statd moduls, th ovrall piplind architctur of th proposd look-ahad dcodr can b dsignd accordingly. Without of loss of gnrality, hr w mploy an -bit polar dcodr as an xampl. Fig.7 shows th proposd piplind architctur for a -bit look-ahad polar dcodr, which is composd of th main computation structur and th IGC part. It is a fd-forward piplind structur that tris to maximiz th us of th hardwar and minimiz th latncy of dcoding. dcodr architcturs, th hardwar utilization of ach activ stag is %, othr stags still rmain idl at th sam tim. Morovr, for th proposd -bit polar dcodr, totally 7 clock cycls ar ruird bfor th nxt codword can b procssd. Gnrally, for an -bit polar dcodr ach codword nds - clock cycls to b proprly dcodd with th givn approach, during which no nw codword could b input to th dcodr. Thrfor, vn only half latncy is ndd by th proposd schm, th hardwar fficincy rmains low for dcodrs with larg. Manwhil, in synthsizing SP architcturs it is also important to maximiz th silicon fficincy of th intgratd circuits. On possibl approach is to furthr rfin th piplind architctur which nabls nw input vry clock cycl [6]. According to th dcoding tim chart dpictd in Fig. (b, th nw dcoding schdul which tripls th dcoding throughput is givn in Tabl II. In ordr to procss thr codwords simultanously, Stag has bn duplicatd (Stag to avoid data contradiction. It is obvious to s that th hardwar fficincy for stag i (i > is 5.7%. And that of Stag is 4.9%. Compard with similar approach in [], th proposd on achivs th sam utilization rat at ach stag but is bttr arrangd, which can b obsrvd from Tabl II of [] asily. ( y, u i ( i ( i i ( y, u signs Stag Stag Stag : Piplin O I c O O I + u or 5 6 I u or u 6 RAM ( O I ( ( y 4 O I ( ( y 4 outputs ( 4 ( 5 ( 6 ( 7 ( U U Figur 7: Piplind dcodr of look-ahad polar cods with =. û 4 O O O I 4 I 4 In gnral, for th -bit polar dcodr, totally - incorporatd PEs, - -to- multiplxrs, /- XOR-PASS lmnts, /- -to- dmultiplxrs, (- dlay lmnts, and /- bits of RAM ar ruird. V. MOIFIE ARCHITECTURES FOR PROPOSE ECOER In this sction, w propos th systmatic dsign mthods for thr diffrnt modifid look-ahad polar dcodrs basd on th on illustratd in Fig. 7. SP-VSI dsign tchnius ar wll mployd to improv th hardwar fficincy whil kp th rducd dcoding latncy unchangd. Rfind Piplind Architctur of th ook-ahad codr It is asy to notic that although for th proposd piplind I TABE II REFIE ECOIG SCHEUES OF -POAR ECOER Stag Clock cycl ook-ahad dcoding schdul C C C C C C C C ook-ahad dcoding schdul with rfind piplining C C C C 4 C C C C C C C C C C C C C C ( y, u i ( i ( y, u i ( i ( y, u i ( i ( y, u i ( i signs Stag and ' 6l+, 6 {4, } {5, } {, 6} {4, } {5, } {, 6} : Piplin O O I I U + u or 5 6 or u {, 4} {, 6} {, 5} c c c U U 6 RAM RAM RAM U U U C C C Stag Stag O O I I O I O O I O 4 O I O I u u u {5} {4} {6} 4 û 4 Figur : Rfind piplind dcodr of polar cods with =. O I ( ( ( ( 4 ( 5 ( 6 ( 7 (

9 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < 9 Without loss of gnrality, hr th authors us th rfind architctur of -bit polar dcodr as an xampl, which is illustratd in Fig.. Othr dcodrs with diffrnt cod lngth can b drivd accordingly. It is worth noting that Stag and, which ar activatd in srial, ar gnratd by unfolding transformation with factor of. Kping in mind that th concurrnt inputs ar indpndnt, totally copis of IGC ar ruird as a rsult. According to th rcursiv construction algorithm of look-ahad tim chart givn in Sction III, it is obvious that for -bit polar dcodr th maximum valu of concurrnt inputs is -. Howvr, in ordr to guarant th non-blocking dcoding procss, mor duplicatd stags ar ruird by highr concurrnt numbr M. Th dtaild rlationship btwn concurrnt numbr and hardwar consumption can b statd in th following proprtis. Proprty For -bit look-ahad polar dcodr, th highst concurrnt numbr M is -. Proof According to rcursiv algorithm, th dcoding tim chart will tak totally log log i = = ( i= clock cycls. uring th dcoding procss for a singl codword, Stag is only activatd in on clock cycl. Thrfor, in th rst - clock cycls, Stag is availabl for othr possibl input codwords. Proprty For a givn -bit polar dcodr architctur, th i - concurrnt vrsion can b drivd by duplicating i- - stags, which hav th most significant indics, of th i- - concurrnt vrsion. Proof It can b noticd that i i = ( +, (9 which is in th sam mannr that th look-ahad dcoding chart is constructd. In ordr to mak % hardwar utilization of th whol dcodr (or crtain spcific stags, for ach dcoding stag th numbr of PEs should stay th sam. Sinc th dcoding chart is constructd in th tim domain, w only nd to apply th sam approach in th stag domain, which rsults in th mthod givn in Proprty. For xampl, th -concurrnt vrsion of -bit look-ahad polar dcodr in Tabl II is implmntd by adding a duplicatd Stag to th -concurrnt vrsion. Morovr, its 7-concurrnt vrsion, which can achiv % fficincy, can b constructd basd on th -concurrnt vrsion accordingly as follows in Tabl III. Sinc 7= -, ( - = - th 7-concurrnt vrsion can b drivd basd on th -concurrnt on by duplicat Stag,, and, which hav th most significant indics. It can b sn that th proposd 7-concurrnt dcodr can handl inputs prfctly and achiv % utilization rat during coding itration i (i >. Proprty For any M which satisfis i- - < M i -, th M-concurrnt polar dcodr ruirs th sam hardwar consumption. And % hardwar fficincy can b achivd if and only if whn M = i -. Proof According to th proof of Proprty, th proof is immdiat and its dtails ar omittd hr. Proprty 4 For any M which satisfis i- - < M i -, th totally numbr of PEs mployd by th M-concurrnt polar dcodr is + i- (i-. Proof According to Proprty, th numbr of PEs can b calculatd as follows: log i i + ( i j= i i i = ( + ( i i = + ( i. ( For xampl, th -, -, and 7-concurrnt vrsions of -bit look-ahad polar dcodr ar calculatd to hav 7,, and PEs rspctivly, which can b asily vrifid according to Tabl II and III. TABE III - A 7-COCURRET ECOIG SCHEUES OF -BIT POAR ECOER Stag Clock cycl concurrnt look-ahad dcoding schdul C C C C4 C5 C6 C C C C C C C4 C5 C6 C4 C5 C6 C C C C C C C4 C5 C6 C4 C5 C C C C C C C4 C5 C6 C4 7-concurrnt look-ahad dcoding schdul C C C C4 C5 C6 C7 C C C C4 C5 C6 C7 C C C C4 C5 C6 C7 C C C C4 C5 C6 C7 C C C C4 C5 C6 C7 C C C C4 C5 C6 C7 C C C C4 C5 C6 C7

10 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < Foldd Architcturs of th ook-ahad codr Folding is a tchniu to rduc th silicon ara by tim-multiplxing many algorithm oprations into singl functional unit. Howvr, in most cass th mans of folding will rsult in trading ara for tim in SP architcturs. Thrfor, in ordr not to affct th pr-statd dcoding schdul with mor dcoding clock cycls, th folding approach mployd hr is not trivial. For th -bit polar dcodr, Stag is usd as a functional unit and all functions of othr stags ar proprly mappd to this stag. Fig. 9 shows th folding transformation rsult of th circuits illustratd in Fig. 7. Th tim instancs at which th switch xcuts ar also givn to bttr illustrat th opration schduling of th foldd architcturs. Apart from 9 switchs, which ar ngligibl, th proposd foldd architctur only ruirs th first stag of dcodr givn in Fig. 7 whil kps th latncy-rducd dcoding schdul intact. Easy to obsrv that, for practical applications, 5% of th incorporatd PEs can b liminatd as a rsult. For larg, th corrsponding hardwar fficincy can b as high as twic of that of th non-foldd on. Thrfor, th folding tchniu can hlp to achiv a good tradoff btwn th dcoding latncy and hardwar consumption. Admittdly, highr utilization rat can b achivd if th functional unit mploys fwr Mrgd PEs, for which th most xtrm consists of only on Mrgd PE. Though furthr folding can rsult in lss hardwar consumption, th dcoding latncy will incras drastically du to th ruird tim-multiplxd schm. Usually, it is rcommndd to fold th dcodr on th bas of Stag along with /+ switchs. outputs : Piplin ( y, u i ( i ( i i y u (, signs {, 4, 6, 7} {, 5} {, 4, 6, 7} {, 5} c ( 5 ( 6 ( 7 ( U U Figur 9: Foldd -bit polar dcodr architcturs. {, 6} {4} RAM {, 4, 6, 7} O O O O I I I I 7l+,, 7 {} {,, 7} {} {} {, 5} {} {, 5} ( ( ( ( 4 Paralll Architcturs of th ook-ahad codr It is obvious to notic that only during Clock cycl can th foldd architctur achivs % hardwar fficincy, which indicats that furthr improvmnt is possibl. Sinc paralll procssing and piplining tchnius ar duls of ach othr, and if on dsign can b piplind, it can also b rarrangd in paralll. Sinc in all clock cycls xcpt for th first on, lss or ual than half of th Mrgd PEs ar activ, a -paralll architctur is dsignd hr. Tak th -bit polar dcodr as an xampl, in ordr to proprly procss two indpndnt inputs in an intrlavd mannr, an additional clock cycl is ruird as follows in Tabl IV. Howvr, for larg th additional clock cycl introducd by th proposd -paralll architctur is ngligibl compard with th long dcoding latncy. Also, this paralll architctur can achiv as twic throughput as that of th foldd on. ot that a duplicatd IGC is ncssary to satisfy th ruirmnt of two indpndnt inputs. TABE IV UMBER OF ACTIVE MERGE PES I EACH COCK CYCE Clock cycl Input C 4 C 4 outputs outputs signs signs U U {4, 5, 7, } {4, 5, 7, } {4, 5, 7, } c RAM {4, 7} {5} c RAM {} O {,, 6} {} {,, 6} {} {,, 6} {} O {,, 6} {} {,, 6} {} {,, 6} {} O {,, 6} {} {,, 6} {} {,, 6} {4, 5, 7, } {4, 5, 7, } {4, 5, 7, } {} O {,, 6} {} {,, 6} {} {,, 6} {4, 7} {5} U U Figur : Paralll architcturs for -bit polar dcodr. I I I I : Piplin l+,, ( ( {, } y y9 {,, } ( ( y y {, } {, } ( ( y y {, 6} {, } ( ( y4 y {, 6} {, 6} {, } ( ( y5 y {, 6} {, } ( ( y6 y4 {4,, } {, } ( ( y7 y5 {} {4,, } {, } ( ( y y6 {} On th othr hand, for cass in which low hardwar consumption is th priority rathr than short dcoding latncy, -paralll procssing with < < / can b mor apprciatd. In gnral, -paralll procssing will introduc totally

11 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < iffrnt dsigns st dsign TABE V COMPARISO FOR IFFERET POAR ECOER ARCHITECTURES nd dsign rd dsign 4 th dsign Tr dsign Ovrlappd dsign in dsign Hardwar consumption # of Mrgd PEs - + i- (i- / / - ~+M(log M// / XOR 9 - PE REG MUX 6 5 # of IGCs - M XOR /- IGC RAM /- MUX /- # of othr REGs (-4 (M+[+ i- (i--i]+i (/+ (9/+4 (- ~M[+M(log M//] (- # of othr MUXs (- 6[+ i- (i-] (- (+ ~[+M(log M/] (/- XOR ~7 ~[+ i- (i-] ~7/ ~7/ ~(6- ~(-[+M(log M//] ~(9-/ Total REG ~ ~(M+[+ i- ~(M+[+M(log (i-] ~/ ~9/ ~(+ M// ] ~(+/ coding schdul atncy (- (- (- Throughput M M All dsigns ar proposd by []. Comparison dos not includ IGC block. ormalizd rsults ar compard. i= ( ( i= clock cycls and - copis of IGC. In this papr, for considration of good balanc btwn latncy and hardwar consumption, only dtails of th -bit -paralll dcodr ar providd in Fig.. VI. COMPARISO OF ATECY A HARWARE COSUMPTIO In this sction, w compar th dcoding latncy and th hardwar fficincy for th proposd look-ahad polar dcodr and its thr variants along with stat-of-th-art rfrncs. Tabl V lists th comparison rsults of thos dsigns in trms of both latncy, hardwar, and som othr ky mtrics such as throughput, fficincy, and so on. Th st dsign is th straightforward implmntation of th proposd look-ahad dcoding schdul, whos countrpart is th tr dsign. Th nd on is dvlopd basd on th first on with rfind piplining and unfolding schm with countrpart markd as ovrlappd dsign. Th rd on is drivd by folding th whol architcturs of th st dsign to Stag, whos countrpart is namd as lin dsign. Th 4 th dsign incorporats -paralll procssing with th rd dsign to achiv vn highr fficincy at th xpns of an additional dcoding clock cycl. Sinc it is th first approach which succds in incorporating both folding and paralll procssing togthr, no countrpart is listd hr. For as of xplanation, it is assumd that th (, f uantization schm is mployd by all dsign, whr is th fixd lngth of Rs and f is th lngth of th fraction part. According to Tabl V, th most significant point is that bnfitting from th proposd look-ahad dcoding schm all th givn dsigns ruir only half th latncy as othrs do. This advantag maks th proposd dcodrs mor applicabl for fastr implmntations, which always dmand cod lngth highr than. A good xampl maks th advantag apparnt: no mattr what valu th concurrnt numbr M is, th nd dsign is abl to finish dcoding all codwords bfor its countrpart (ovrlappd dsign outputs its first dcodd word. Anothr point is th IGC, which is inspird by th ral FFT procssor proposd in [4] and can b gnratd with a nic and asy rcurrnc rlationship, is abl to output all control bits ruird by th multiplxrs on th fly. Thrfor, no additional clock cycls ar ndd for computation of u i, which prsrvs th advantag of short latncy. To th bst knowldg of th authors, this is th first dtaild dsign of similar modul with such faturs. ot from Tabl V, th authors succd in giving th dtaild architctur for ach sub-block. Manwhil, sinc rfrnc [] faild to provid dtails of th u s computation block, which is th countrpart of th proposd IGC, only th comparison of hardwar consumption for th rst blocks is conductd. And th assumption that ach -bit -to- multiplxr ruirs th sam silicon ara as an XOR gat is usd hr for stimation [7]. spit of largr numbr of rgistrs, which ar inhrntly rsultd from th look-ahad schm, th proposd dsigns nd similar hardwar ara (in th form of XOR gats numbr compard with thir countrparts. Th st and nd dsigns nd 6.5% and 4.7% mor hardwar than thir countrparts, rspctivly. On th othr hand, th rd and 4 th dsigns only ruir 9.47% hardwar than th lin dsign. And th 4 th on managd to achiv half dcoding latncy and twic data throughput compard with th lin dsign. Among th four dsigns proposd in th manuscript, th nd on can achiv th highst throughput and hardwar fficincy (%. Th rd and 4 th dcodrs ruir th last numbr of Mrgd PEs. And th 4 th on can rach th optimal compromis btwn dcoding throughput and ara, whos throughput-to-ara ratio is twic that of th rd on. Thos proposd dsigns mak it availabl to

12 > REPACE THIS IE WITH YOUR PAPER IETIFICATIO UMBER (OUBE-CICK HERE TO EIT < mt dmands of diffrnt application situations. VII. COCUSIO Basd on th rcursiv construction mthod of dcoding tim chart, a novl look-ahad SC dcoding schdul for polar cods is proposd in this papr, which can halv th dcoding latncy ruird by convntional approachs. For fficint hardwar implmntation issu, a Mrgd PE is prsntd by using sub structur sharing tchniu. Its control signal u i can b gnratd with a ral FFT-lik diagram. This uniu fatur is dirctly applid to dvlop an fficint input gnrating circuit (IGC, which works bst with th latncy-rducd polar dcodr architctur. Th mthodology for dsigning four diffrnt look-ahad polar dcodr architcturs is prsntd along with gat-lvl dtails. Comparison rsults hav shown that asid from th IGC modul, th proposd dsigns show comparabl hardwar fficincy whil hav much shortr dcoding latncy than thir convntional countrparts. REFERECES [] E. Arikan, Channl polarization: a mthod for constructing capacity-achiving cods for symmtric binary-input mmorylss channls, IEEE Transactions on Information Thory, vol. 55, no. 7, pp. 5-7, July 9. [] E. Arkan, A prformanc comparison of polar cods and Rd-Mullr cods, IEEE Communications ttrs, vol., no. 6, pp , Jun. [] C. roux, I. Tal, A. Vardy, and W. J. Gross, Hardwar architcturs for succssiv cancllation dcoding of polar cods, IEEE Intrnational Confrnc on Acoustics, Spch and Signal Procssing (ICASSP, pp , May. [4] M. Garrido, K. K. Parhi, and J. Grajal, A piplind FFT architctur for ral-valud signals, IEEE Transactions on Circuits and Systms I: Rgular Paprs, vol. 56, no., pp , c. 9. [5] F. R. Kschischang, B. J. Fry, H.-A. oligr, Factor graphs and th sum-product algorithm, IEEE Transactions on Information Thory, vol. 47, no., pp , Fb. [6] K. K. Parhi, VSI igital Signal Procssing Systms: sign and Implmntation, w York, Y: John Wily & Sons Inc., 999. [7] Xinmiao Zhang and Fang Cai, Efficint Partial-Paralll codr Architctur for Quasi-Cyclic onbinary PC Cods, IEEE Transactions on Circuits and Systms I: Rgular Paprs, vol. 5, no., pp. 4-44, Fb..