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1 Fanout Optimization under a Submicron TranitorLevel Delay Model P. Cocchini y, M. Pedram z,g.piccinini y and M. Zamboni y y Politecnico di Torino, Torino, Italy y cocchini@polito.it, piccinini@polito.it, zamboni@polito.it z Univ. of Southern California, Lo Anele, CA z maoud@zuro.uc.edu Abtract In thi paper we preent a new fanout optimization alorithm which i particularly uitable for diital circuit deined with ubmicron CMOS technoloie. Retrictin the cla of fanout tree to the ocalled bipolar LTtree, the topoloy of the optimal fanout tree i found by mean of a dynamic prorammin alorithm. The buer election i in turn performed by uin a continuou buer izin technique baed on a very accurate delay model epecially developed for ubmicron CMOS procee. The fanout tree can ditribute a inal with arbitrary polarity from the root of the tree to a et of ink with arbitrary required time, required minimum inal lope, polarity and capacitive load. Thee tree can be contructed to maximize the required time at the root or to minimize the total buer area under a required time contraint at the root. The performance of the alorithm how everal improvement with repect to conventional fanout optimization method. More preciely, the area and delay improvement are 28% and 7%, repectively, when the alorithm i applied to entire circuit. Introduction Durin loic ynthei, everal dein tep are performed to tranlate the initial loic decription into a phyical netlit uitable for the nal manufacturin. One of thee tep, fanout optimization, i uually required after the technoloy mappin tep where typically, for a lare number of node in the circuit, the output inal mut be propaated to everal detination (or ink). Theoretically, a fanout alorithm hould be able to take advantae of the lack available at ome output to increae the lack at the initially more critical output to achieve an equilibrium point where all output are equally critical. Conventional technique commonly ued for CMOS tandard cell do not uually achieve thi oal becaue of the dicrete nature of the delay optimization they are baed on. For example, the work reported in [, 2, 4, 7, 8, 9] rely on a cell library with a nite number of Thi reearch wa funded in part by NSF PECASE award number MIP and SRC under contract number 98DJ606. available buer. Furthermore they all ue very imple delay model that everely limit their applicability epecially when ubmicron procee are involved. On the other hand, the approachwe preent coniderably improve thee two apect. Indeed, it i baed on a continuou delay optimization technique whoe main feature are hih accuracy and independence from the technoloy in ue. The delay model i rt applied to the creation of two numerical routine for the dein of delay and area optimized CMOS tapered buer. Then, a buerin alorithm ue them to create a fanout tree where the available lack at the detination are fully exploited to enerate driver whoe delay are tailored to t perfectly between the ink required time. In Section 2 we ive an overview of the delay model adopted in our work and introduce the routine ued for the eneration of the optimized buer. In Section 3 we ive ome baic denition and explain the buerin alorithm propoed for the olution of the fanout problem. Section 4 report the reult obtained tetin the alorithm on dierent benchmark circuit. Concludin remark are preented in Section 5. 2 Delay Optimization 2. Inverter Delay Model Since the buerin proce which we perform for the eneration of a fanout tree only involve CMOS tapered buer, we are intereted in modelin the behavior of their baic component, that i a tatic CMOS inverter whoe chematic i reported in Fiure. The delay model that we ue throuhout the paper i the one preented in [3]. It i compoed of a et of analytical equation which model the output repone of a CMOS inverter takin into account the main econdorder eect preent in ubmicron procee. The input voltae and output voltae are modeled a inal with trapezoidal hape a hown in Fiure. The feedthrouh eect between input and output i conidered by mean of a capacitance C FF. We will not ive here a detailed explanation of the delay equation a thi i outide the cope of the preent paper. For a more complete treatment, the reader i referred to [3]. In Fiure we alo introduce ome denition ued here and in the ret of the paper. With k r and k f we denote the lope in [V/n] of the riin and fallin ede of a ramp hape voltae inal, repectively. Followin thi notation, k ri and k fi are the lope of the input voltae V I of the inverter, while k ro and k fo are the lope of the output voltae V O. Moreover, t pr and t pf are the propaation time of the riin and fallin ede of V O, repectively. They are

2 V DD I I 2 I N k k fi k fo k ro r I V I t pf C FF T w 2 2,l min T w,l min C L Fiure : CMOS Inverter. meaured a the dierence between the time where V O and V I are at 50% of their total win. An inverter I i identi ed by the tuple I = fm; u, where m i the ratio between the width w of the pulldown tranitor T and the minimum width w min allowed by the uer, and u i the ratio between the width of the pullup and pulldown tranitor of the inverter. With P we denote a et of proce and layout parameter of the technoloy in ue on which the delay model depend. In thi context, the equation for the delay model can be repreented a: t pr = f (P; k ri ;k fi ;C L;m;u), t pf = f 2(P; k ri ;k fi ;C L;m), k ro = f 3(P; k ri ;k fi ;C L;m;u), k fo = f 4(P; k ri ;k fi ;C L;m), where f, f 2, f 3, f 4 are nonlinear function of their arument. To automatically perform the dein of an inverter and therefore of a tapered buer, thee function have been arraned in the routine delay INV, written in C lanuae, which can perform two dierent tak: Tak Given P, k ri, k fi, C L, m, u, calculate k ro, k fo, t pr, t pf. Tak 2 Given P, k ri, k fi, C L, m, calculate u, k ro, k fo, t pr, t pf uch that t pr = t pf = t p. In Tak, delay INV imply compute function f, f 2, f 3, f 4 for the iven arument. On the other hand, in Tak 2, delay INV rt olve the non linear equation V O f (P; k ri ;k fi ;C L;m;u x)=f 2(P; k ri ;k fi ;C L;m) () for the width ratio u x and then compute the remainin function f 3 and f uer Dein Acheme of the buer ued for drivin a lare capacitive load i reported in Fiure 2. A can be een, the circuit i compoed of a cacade of N inverter each one caled up by a factor of M with repect to the previou one (the rt inverter ha alway minimum ize). A buer i then dened a a et of N inverter = fi ;I 2;:::;I N. We extend here the denition of delay and inal lope for the voltae V I and V O iven in the previou ection. A methodoloy for the determination of the optimal parameter N and M of a buer with minimum and ymmetrical propaation delay (t pr = t pf = t p) i iven in [3]. Here, after an initial tep that characterize a cacade of inverter with dierent ize for each proce in ue, peed optimized tapered buer are deined which uniformly ditribute the overall propaation delay t p alon the chain for any iven capacitive load t pr V I u u 2 u N m= m2=m m N =M Fiure 2: CMOS Tapered uer. C L. A limitation of thi buer optimization technique i that it conider only typical value for the input lope k ri and k fi. Thu, to overcome thi problem and conider arbitrary input lope value, the dein of a minimum delay buer i performed in thi work by mean of a new routine min delay UF which i capable of performin the followin tak: Tak 3 Given P, k ri, k fi and C L, nd a buer with minimum and ymmetrical propaation delay t pr = t pf = t p. Similarly, the dein of a buer with minimum area, ubject to a time contraint in term of maximum propaation delay, i accomplihed by mean of routine min area UF that perform the followin tak: Tak 4 Given P, k ri, k fi, C L, t p max, k r req, k f req, nd a buer with minimum area uch that t pr = t pf = t p t p max, k ro k r req and k fo k f req. Additional contraint on the minimum lope of the riin and fallin ede of the output inal are alo iven in order not to woren the delay of ucceive tae. oth routine min delay UF and min area UF are baed on iterative call to routine delay INV which i ued to compute the exact delay ofeach tae. Thu, the propaation delay t pr and t pf and the lope k ro and k fo at the output of a buer can be put in the form: t pr = f 5(P, k ri, k fi, C L, N, M, u N ), t pf = f 6(P, k ri, k fi, C L, N, M), k ro = f 7(P, k ri, k fi, C L, N, M, u N ), k fo = f 8(P, k ri, k fi, C L, N, M), where f 5, f 6, f 7, f 8 are non linear function, N i the the number of tae, M i the taperin factor, and u N i the width ratio of the lat inverter of buer. The value for the width ratio u of all the other tae are not pecied a they remain xed to default value. In the cae of tak 3, routine min delay UF imply calculate the parameter N and M of the minimum delay buer accordin to the technique reported in [3], and then rehape it lat tae olvin the equation f 5(P; k ri ;k fi ;C L;N;M;u N)=f 6(P; k ri ;k fi ;C L;N;M) for the variable u N, in order to have a ymmetrical output repone. On the other hand, routine min delay UF determine the minimum number of tae N min and the correpondin parameter M of a tapered buer whoe propaation delay t pr and t pf are le then a iven maximum value t p max. In particular, to nd a buer with minimum area and delay t pf t p max, min delay UF rt olve the non linear equation N t p max = f 6(P; k ri ;k fi ;C L;N min; M min) for M min uch that M min, and then calculate the variable u Nmin, olvin t pf = f 5(P; k ri ;k fi ;C L;N min; M min; u Nmin ) V O C L

3 where t pf = f 6(P; k ri ;k fi ;C L;N min; M min), to have a ymmetrical buer output repone. Finally, if the limit k r req and k f req on the output lope are pecied, function f 7 and f 8 are computed to verify that the requirement of tak 4 are met. Therefore if k ro k r req or k fo k f req, the buer with minimum area i deined olvin the equation: k r req = f 7(P; k ri ;k fi ;C L;N min;m a;u Nmin ), k f req = f 8(P; k ri ;k fi ;C L;N min;m b ) and takin M min = max (M a;m b ). 3 Fanout Optimization Like other propoed fanout optimization [2] [7] [8], our methodoloy relie on orderin ink by nondecreain required time. While retrictin the et of all the poible fanout tree, thi aumption allowed u to develop an ef cient alorithm of polynomial complexity uin dynamic prorammin. Apart from the far more accurate delay model, our optimization technique ha other important advantae. Firt of all, there i not a buer election proce where tree with ame topoloy lead to dierent olution becaue of the everal combination of ditinct buer available in a library. A a matter of fact, iven a tree topoloy, the extent of the lack between ditinct leave uniquely identie the hape and ize of the needed buer. Secondly, the treatment of ink with dierent polaritie i intrinically implemented in the fanout alorithm and doe not increae it complexity. Finally, the adoption of a preprocein tep, which i preented in Section 3.7, can inicantly reduce the number of ditinct ink to be driven o that the execution time of the alorithm i dratically hortened. 3. Denition We dene S a the et of n detination or ink where a inal v, correpondin to the root of a tree, mut be propaated. Each ink i 2 S ha arbitrary polarity pi 2f;,, capacitive load l i and required time r i. Furthermore, ink f ; 2; :::; n of S are ordered by increain required time, that i, 8i 2 [2;n,], r i, r i r i. A roup G p i;j S i then dened a the et of ink of polarity p amon the adjacent ink f i;:::; js,l i;j bein p the um of the load of it element. Each roup G p i;j can be driven by a correpondin buer p i, whoe input bp i ha required time r b p and load l i b p equal to the input capacitance of i a minimum inverter, that i the one of it rt tae. Finally, a fanout tree i dened a the et T = [ i p i of buer p i that form a tree where the leave are roup and the union of all leave equal S. Under thee denition, the fanout problem can be pecied in two dierent way dependin on the cot function to be minimized. Problem (Max required time with Min area) uild a tree T of buer that ditribute the inal v to the ink S and ) maximize the required time r v at it root, 2) minimize the area of it implementation. Problem 2 (Min area under required time contraint) uild a fanout tree T that minimize the area of it implementation uch that the required time r v at the root i r v rvmin where r vmin i a iven minimum value. Additional contraint to thee problem are the peci cation of a minimum inal voltae lope at the ink a well a the minimum lope k r v and k f v of the inal to be propaated. y 4 y 3 y 2 y level 3 level 2 level y 2 2 y y2 y3 2 y 3 Fiure 3: Example of tree topoloy with three ditinct level. 3.2 Tree Search Space In order to reduce the complexity of the alorithm only a ubet of all the poible tree mut be conidered. A cheme repreentin the topoloy of a fanout tree belonin to uch a ubet i reported in Fiure 3. In thi repreentation, ink S = f ; 2; :::; n are reported in order of increain required time alon the vertical axi, with the indication of their polarity, while buer are drawn a mall circle annotated with the number of tae they are compoed of. A tree i divided into a et of z dierent level identied by a (z)tuple of inteer (y ;:::;y z) uch that: y = < y 2 < ::: < y z < y z = n, with z n. Each level i 2 f;:::;z contain y i, y i ink, from yi to yi,. Sink with poitive polarity form the roup G y i ;y i, and are driven by a buer y i wherea thoe with neative polarity form the roup G, y i ;y i, and are driven by a buer y, i. In the cae of Fiure 3, z =3 with a (z)tuple (, 3, 9, 7). Each buer can accept a connection from one or two buer belonin to the upper level i. Dependin on the polaritie of it ink and the buer of the upper level i, it follow that a level i can alway have exactly one or two buer drivin it ink. The cla of tree that we have jut dened i very imilar to that of LTTree of type introduced in [8]. While the tree belonin to uch cla have at mot one buer in the fanout of any buer, in our cae each buer can drive or 2 buer alon with any number of leave. For thi reaon, we call our tree bipolar LTTree, or for hort ilttree. ecaue of thi property, it i apparent that each (z)tuple identie 2 z poible fanout tree. The number of poible (z)tuple of inteer correpond to the number of ditinct way of chooin z, element amon n,. Therefore, the total number of poible fanout tree i n, X z= n, z, 2 z =2 n,2 X z=0 n, z 2 z =23 n,,2 n (2) Such earch pace i reater than both that of LTTree of type (2 n,2 ), and LTTree of type 2 (2 n, )[8]. In (2) we alo aume that the rt level can have two buer which are drivin ink of dierent polaritie. It i apparent that thi ituation i in contrat with the requirement of a onerooted fanout tree like the one of Fiure 3. Neverthele, every occurrence of thi kind can be uniquely reolved introducin one or two additional inverter in cae p b or p b hold. p b, p b, = =,, repectively, o that the equation till n

4 3.3 The Alorithm for Tree Selection The election of the bet tree for the olution of Problem and 2 i performed with the alorithm tree election, detailed in Fiure 4. At the beinnin, the proce databae P i loaded and ink are ordered by nondecreain required time. Then, the load l p i;j of each poible roup Gp i;j S i precomputed. The problem i now plit in n ubproblem, identied by an index z, of ink ( z; ; n). A ubproblem z, then, i olved in n, z dierent way, indicated by an index h, of which only the bet one T z i kept in a table, hence thi i a dynamic prorammin approach. Each olution h correpond to the inertion of one or two buer and/or,, which repectively drive roup G z;h and G, z;h, and the upper level ubtree T h. Since the alorithm proceed with z from n to, T h ha already been computed and i available. For each polarity p 2 f;,, alorithm tree election load P, S, k rreq, k freq, r vmin ; Sort S by increain required time, S = =P f ; 2;:::; n; 8i2[;n], 8j 2 [i; n], 8p 2f;,, l p j i;j k=i l k pp k, where ppk i the Kronecker delta function; for z = n to f area(t z)=;r Tz =,; for h = z to n f foreach polarity p 2f;, f load = l p z;h lp T ; h if (load > 0) f r load = load required time; if (z >) then r prev = r z, ; ele f if (P roblem =)then r prev = r load ; ele if (P roblem =2)then r prev = r vmin ; p = min area UF (P, k r, k f, load, r load, r prev, k rreq, k freq ); if ( p = ;) then z p = min delay UF (P, kr, k f, load); ele p = ;; T = T h [ [, ; r T = min(r b ;r b,); if (r T >r prev) f if (area(t ) < area(t z)) then T z = T ; ele f if (r T >r Tz )then T z = T ; end tree election Fiure 4: The alorithm for the fanout tree election. the load of a buer p i calculated a the um of the precomputed quantity l p z;h and the load of ame polarity lp T h, oered by the ubtree T h. If uch load i null, the correpondin buer p i not inerted. Each buer i deined callin the routine min area UF whoe arument are ordered, and have the ame meanin, a in the denition of tak 4. Particularly, the lope k r and k f of the input inal are choen a typical value for a correct execution of the alorithm. A can be een, the maximum allowed delay time t max = r load, r prev i equal to the dierence of two term: the required time r load of the load driven by the buer, and r prev which i equal to the required time r z, of the cloet not yet buered ink z,. In thi way, buer p will have a required time equal or hiher than r z,,thu not aectin the required time of ubequent ubtree, and minimum area for it implementation. If t max i too low and no buer with uch delay i poible, then p i deined by mean of routine min delay UF, which, iven it arument dened a for tak 3, return a minimum delay buer. At thi point, the h olution T of ubproblem z i formed by the union of buer,, and ubtree T h. If the required time r T of T, dened a the minimum of the required time of and, (or the required time of one of them if the other i empty), i hiher than r prev, and it area i lower than the one of the bet current olution T z, then ubtree T take it place. On the other hand, if r T i lower than r prev, T i tored only if it required time i the hihet. The ame procedure applie to both Problem and 2 until the lat ubproblem z =, which correpond to the overall fanout problem, ha to be olved. A can be een, in uch a ituation the required time t prev take dierent value. When Problem i bein olved, then r prev = r load and buer p are deined for minimum delay. On the other hand, for Problem 2, r prev take the value r vmin, the iven minimum required time of the root that can be exploited by the routine min area UF to obtain a buer with lower area. In thi way, at the end of the proce, tree T tore the bet olution for a iven fanout problem. 3.4 Optimality for the Min Delay Problem The optimality of the alorithm for the olution of Problem i proved by the followin theorem: Theorem (Optimality for Minimum Delay) The tree election alorithm produce an optimal fanout tree for Problem over the cla of all ilttree, aumin that routine min delay UF produce optimal olution to Tak 3. Proof From the property of dynamic prorammin alorithm, the olution to Problem i optimal exactly if uch i true for the olution T z of each ubproblem z. Therefore, for what pertain to the proof of the theorem, it i ucient toprove the optimality ofa inle ubtree T z. The ret of the proof follow by induction on z. The olution of a ubproblem z, take the eneration of n,z dierent ubtree by mean of routine min delay UF and min area UF. In each cae, min area UF introduce a buer whoe required time i alway reater than the required time r prev of the hihet ink in the lower level. On the other hand, min delay UF enerate a peed optimized buer whoe delay i the mallet poible. The olution T z i then choen a the one with the hihet required time r T if every ubolution ha required time r T <r prev; otherwie the ubtree with minimum area i taken. A a reult, the olution T z i optimal becaue it will oer to the next ubproblem z,, the mallet load to drive (the input capacitance of a buer i alway that of a minimum ize inverter), with a required time uch that the required time r Tz, of the root of the ubequent ubtree T z, can be the maximum poible. 3.5 An Example of Generated Tree An example of a fanout tree enerated by the alorithm tree election i reported in Fiure 5 for a typical problem with 8 ink and a 0.5m CMOS proce. Here, the required time of ink and buer i proportional to their poition alon the yaxi. A can be een, there are three level. Level i compoed of ink ; 2; 3 and the inverter, wherea level 2 i compoed of ink 4, 5 and the inverter, 4, and level 3 i compoed of ink 6 throuh 8 and the twotae buer 6 and, 6. It i interetin to note that the required time of both buer and 6, 6 i reater

5 G,3 G6,7 4,5 G y 0 8 G 2,3 G 9, 2 y 3 G 4,5 y 2 G6,7 Fiure 5: Fanout tree for a typical problem: n = 8, z =3, y =,y 2=4,y 3=6,y 4= 8. Sink can be mered into roup durin the mere ink preprocein tep. than that of any of the ink belonin to the lower level 2. A thorouh examination of the tree eneration proce indicate that both buer have been deined to have minimum area throuh the routine min area UF, and that the minimization proce topped becaue of the contraint on the minimum lope k r req, k f req of the output inal. 3.6 Complexity The number of time we o throuh the mot neted inner loop of the tree election alorithm i equal to n(n ). Therefore the complexity of the alorithm i O(n 2 ), a we aume that both routine min delay UF and min area UF have complexity O() and perform their repective tak in contant time. When treatin ink of dierent polaritie imultaneouly, the alorithm propoed in [8] ha complexity O(d 2 max (n; p) max (np, max (n; p) :5 )), while the one propoed in [7] ha complexity O(d 3 n 2 p 2 ). Here, d i the number of dierent buer in the cell library, and n and p are the number of ink of neative and poitive polarity, repectively. A can be een, our alorithm ha maller complexity due to the direct election of buer in the choen tree. 3.7 PreProcein and PotProcein With our methodoloy ink are treated independently of their load and there are no limit impoed on their ize. Thi property uet that ink with equal or very cloe required time can be mered toether to reduce the ize of the problem with no advere impact on the nal reult. An example of application of thi technique, performed by the routine mere ink, i hown in Fiure 5. Here, the number of ditinct ink n i now reduced to only 0, 7 of them correpondin to roup G i;j of ink of the ame polarity. Since thi technique make a reat improvement in the 2 y 3 8 computation time of the alorithm at no performance cot, it i alway ued durin a preprocein tep to reduce the number of ditinct ink of a fanout problem. It ha already been pointed out that durin the execution of the alorithm tree election, the lope k r and k f of the buer input inal are choen a typical value. Thi introduce ome error, althouh mall. After the alorithm ha completed it execution and the topoloy of the bet tree i available, the delay and lope of all the buer of the tree can be recomputed, yieldin exact value, traverin the tree from root up. 4 Reult and Verication To provide experimental evidence of the eciency of the propoed methodoloy, we have applied our alorithm to the fanout optimization of a et of benchmark circuit and compared it performance with thoe of the correpondin optimization alorithm available in SIS [6]. In the SIS environment, loic ynthei and minimum delay technoloy mappin tep have been performed for each circuit, uin a cutom 0.5m CMOS proce cell library calibrated in DSMlib (Deep SubMicron library) format. In thi format, the delay of each pin of each cell i characterized by four ubet of 4 parameter each, modelin the propaation time t pr and t pf, and the tranition time t tr and t tf. The tranition time t tr and t tf are here dened a the dierence between the time where the riin and fallin ede of a inal are at 0% and 90% of their total win, repectively. The pindependent delay model i a follow: delay =(K K 2load) tranition time K 3 load K 4 where delay repreent any of the term t pr, t pf, t tr and t tf for the output pin, load denote the capacitive load of the cell, and tranition time refer to t tr or t tf for the input pin a appropriate. The choice of uch format ha been dictated by the need for an accurate delay model which include the eect of the lope of the voltae inal in the calculation of the tandard cell timin. Notice that thi delay model ha only been ued for the computation of the propaation and tranition time durin the timin analyi executed in the SIS environment. The procedure ued for the lobal optimization of a circuit i that preented in [5]. With thi methodoloy every node i viited in topoloical order and when a fanout problem i encountered a fanout tree i introduced. In [8], thi procedure i hown to be optimal with repect to delay minimization. The reult of the lobal fanout optimization performed for minimum delay on the benchmark circuit are reported in Table. The mappin eld report the delay and area of the circuit after the execution of the technoloy mappin tep for minimum delay. The econd eld report the reult of the bet fanout optimization obtained from the pectrum of alorithm available in SIS (balanced tree, LTtree, combinational merin, twolevel tree, topdown traveral). The third eld report the reult obtained by optimizin the circuit with the propoed continuou methodoloy. Finally, the lat two column report the performance comparion between the two approache. Here, it mut be pointed out that while the rt approach elect, for each node, the bet olution amon thoe produced by each of the conidered alorithm preent in SIS, the continuou approach, in all cae, perform the optimization in the ame way by mean of the tree election at all. In fact, here the concept of tranition time i not contemplated

6 mappin i continuou % reduction circuit delay area delay area cpu delay area cpu delay area 9ymml C C C C C C alu alu apex apex comp dalu k miex rot x x averae Table : Reult for maximum peed fanout optimization applied to entire circuit. Delay i the dierence in nanoecond between the required time at the rt ink and the required time at the root, and cpu i the runtime in econd on a SUNUltra 2. The tree area i iven in 0 3 m 2. alorithm. It mut be pointed out that every buer enerated by the tree election alorithm wa rounded up to the cloet element in a et of 20 predeined buer of dierent trenth which were available in the cell library. Here, intead of eneratin a new cell for each buer, we have opted for a xed number of buer, available to the ame extent to all fanout optimization alorithm, in order to make a more realitic and fair comparion. A can be een, with the continuou approach every circuit i optimized in horter time and the reultin implementation ha lower delay and lower area. Particularly, the typical reduction i 7.% in delay and 28% in area, while the computation time i typically one order of manitude lower. 5 Concluion and Future Work In thi paper we have preented a new methodoloy for the olution of the fanout problem baed on a continuou delay optimization technique. An accurate tranitorlevel delay model i ued to dein delay and area optimized buer that perfectly t the lack between the leave of the fanout tree they et up, reultin in conitent area avin. Our approach i particularly eective for circuit developed with ubmicron CMOS procee where pecial care mut be taken in the evaluation of delay time and inal lope eect. A polynomial time alorithm which ue dynamic prorammin for the election of the bet poible fanout tree ha alo been preented. The hih accuracy of it delay model, the independence from the technoloy in ue, the wide tree earch pace, and the fat runtime make the alorithm very convenient to be ued in CAD tool for the automatic ynthei of diital circuit. When deep ubmicron technoloie are ued, in everal cae the reitance of the interconnection cannot be nelected and the performance of a fanout optimization technique can be further improved only with a potplacement approach where performancedriven fanout and routin optimization problem are olved imultaneouly. We are currently invetiatin uch an approach. Reference [] T. Aoki, M. Murakata, T. Mituhahi, and N. Goto. Fanouttree retructurin alorithm for potplacement timin optimization. In ASPDAC, pae 47{422, Auut 995. [2] C. L. erman, J. L. Carter, and K. F. Day. The fanout problem: From theory to practice. In C. L. Seitz, editor, Proc. of the 989 Decennial Caltech Conference, pae 69{99. MIT pre, March 989. [3] P. Cocchini, G. Piccinini, and M. Zamboni. A comprehenive ubmicrometer MOST delay model and it application to CMOS buer. IEEE J. SolidState Circuit, 32(8):254{262, Auut 997. [4] M. C. Golumbic. Combinatorial merin. IEEE Tranaction on Computer, 25:64{67, November 976. [5] H. J. Hoover, M. M. Klawe, and N. J. Pippiner. oudin fanout in loical network. Journal of the Aociation for Computin Machinery, 3():3{8, January 984. [6] E. M. Sentovich, K. J. Sinh, C. Moon, H. Savoj, R. K. rayton, and A. SaniovanniVincentelli. Sequential circuit dein uin ynthei and optimization. In Proc. of ICCD, pae 328{333, October 992. [7] K. J. Sinh and A. SaniovanniVincentelli. A heuritic alorithm for the fanout problem. In Proceedin of the 27th DAC, pae 357{360, June 990. [8] H. Touati. Performanceoriented technoloy mappin. PhD thei, Univerity of California, erkeley, November 990. Technical Report UC/ERL M90/09. [9] H. Vaihnav and M. Pedram. Routabilitydriven fanout optimization. In Proceedin of the 30th DAC, pae 230{235, June 993.