Synthesis of Reversible Synchronous Counters

Transcription

1 Porland Sae Universiy PDXScholar Elecrical and ompuer Engineering Faculy Publicaions and Presenaions Elecrical and ompuer Engineering 5-2 Synhesis of Reversible Synchronous ouners Marek Perkowski Porland Sae Universiy, Mozammel H.A. Khan Eas Wes Universiy, Bangladesh Le us know how access o his documen benefis you. Follow his and addiional works a: hps://pdxscholar.library.pdx.edu/ece_fac Par of he Elecrical and ompuer Engineering ommons iaion Deails Perkowski, Marek and Khan, Mozammel H.A., "Synhesis of Reversible Synchronous ouners" (2). Elecrical and ompuer Engineering Faculy Publicaions and Presenaions. 23. hps://pdxscholar.library.pdx.edu/ece_fac/23 This onference Proceeding is brough o you for free and open access. I has been acceped for inclusion in Elecrical and ompuer Engineering Faculy Publicaions and Presenaions by an auhorized adminisraor of PDXScholar. For more informaion, please conac pdxscholar@pdx.edu.

2 Synhesis of Reversible Synchronous ouners Mozammel H. A. Khan Eas Wes Universiy, Bangladesh Marek Perkowski Porland Sae Universiy, USA ISMVL 2, May 2, Tuusula, Finland

3 Agenda Moivaion Background Previous Works on Reversible Sequenial Logic Reversible Logic Synhesis using PPRM Expressions Synhesis of Synchronous ouners onclusion ISMVL 2, May 2, Tuusula, Finland

4 Moivaion Reversible circuis dissipae less power han irreversible circuis Reversible circuis can be used as a par of irreversible compuing devices o allow lowpower design using curren echnologies like MOS Reversible circuis can be realized using quanum echnologies ISMVL 2, May 2, Tuusula, Finland

5 Moivaion (cond.) Reversible circuis have been implemened in ulra-low-power MOS echnology, opical echnology, quanum echnology, nanoechnology, quanum do, and DNA echnology Mos of he reversible logic synhesis aemps are concenraed on reversible combinaional logic synhesis ISMVL 2, May 2, Tuusula, Finland

6 Moivaion (cond.) Only limied aemps have been made in he field of reversible sequenial circuis Mos papers presen reversible design of laches and flip-flops and sugges ha sequenial circuis be consruced by replacing he laches and flip-flops of radiional designs by he reversible laches and flip-flops ISMVL 2, May 2, Tuusula, Finland

7 Moivaion (cond.) In his paper, we concenrae on design of synchronous couners direcly from reversible gaes ISMVL 2, May 2, Tuusula, Finland

8 Background A gae (or a circui) is reversible if he mapping from he inpu se o he oupu se is bijecive The bijecive mapping from he inpu se o he oupu se implies ha a reversible circui has he same number of inpus and oupus ISMVL 2, May 2, Tuusula, Finland

9 Background (cond.) A A A P A A A B A B AB AP (a) NOT gae (b) Feynman gae A P A B B R AB AB ABP (c) Toffoli gae A A B P AB AP (d) Fredkin gae AB A AB A Figure. ommonly used reversible gaes symbols and ruh ables ISMVL 2, May 2, Tuusula, Finland

10 Background (cond.) Toffoli gae may have more han hree inpus/oupus. In an n n Toffoli gae, he firs (n ) inpus (say A, A2,, An) are conrol inpus and he las inpu (say An) is he arge inpu. The value of he arge oupu is P = AA2An An ISMVL 2, May 2, Tuusula, Finland

11 Background (cond.) The and 2 2 gaes are echnology realizable primiive gaes and heir realizaion coss (quanum coss) are assumed o be one The 3 3 Toffoli gae can be realized using five 2 2 primiive gaes The 3 3 Fredkin gae can be realized using five 2 2 primiive gaes ISMVL 2, May 2, Tuusula, Finland

12 Background (cond.) A B D (a) A B AB P AB D A A B B AB AB D D E P ABD (b) E Figure 2. Realizaions of (a) 4 4 (cos =, garbage = ) and (b) 5 5 Toffoli gaes (cos = 5, garbage = 2) ISMVL 2, May 2, Tuusula, Finland

13 Previous Works on Reversible Sequenial Logic 24) J.E. Rice, Technical Repor: The Sae of Reversible Sequenial Logic Synhesis, Technical Repor TR-SJR2-25, Universiy of Lehbridge, anada, ) S.K.S. Hari, S. Shroff, S.N. Mohammad, and V. Kamakoi, Efficien building blocks for reversible sequenial circui design, IEEE Inernaional Midwes Symposium on ircuis and Sysems (MWSAS), ) H. Thapliyal and A.P. Vinod, Design of reversible sequenial elemens wih feasibiliy of ransisor implemenaion, Inernaional Symposium on ircuis and Sysems (ISAS 27), 27, pp ) M.-L. huang and.-y. Wang, Synhesis of reversible sequenial elemens, AM journal of Engineering Technologies in ompuing Sysems (JET), vol. 3, no. 4, ) A. Banerjee and A. Pahak, New designs of Reversible sequenial devices, arxiv:98.62v [quan-ph] 2 Aug 29. ISMVL 2, May 2, Tusula, Finland

14 Previous Works on Reversible Sequenial Logic (cond.) All he above works presen reversible design of laches and flip-flops They sugges ha reversible sequenial circui can be consruced by replacing flip-flops and gaes of radiional design by heir reversible counerpars The (non-clocked) laches have limied usefulness in pracical sequenial logic design ISMVL 2, May 2, Tuusula, Finland

15 Previous Works on Reversible Sequenial Logic (cond.) Level-riggered flip-flops and edgeriggered/maser-slave flip-flops have usefulness in sequenial logic design ISMVL 2, May 2, Tuusula, Finland

16 Previous Works on Reversible Sequenial Logic (cond.) TABLE I. omparison of realizaion coss and number of garbage oupus (separaed by comma) of level-riggered flip-flop and edge-riggered/maser-slave flip-flop designs Ref Level-riggered flip-flop Edge-riggered/maser-slave flip-flop RS JK D T RS JK D T [24] 5,6 62,8 5,6 63,8 [25] 2,4,2 7,2 22,6 2,3 3,3 [26] 6,2 6,2 3,4 7,4 [27] 26,5 6,2 6,2 43,4 3,3 3,3 [28] 8,3 2,3 7,2 6,2 24,3 8,3 3,2 2,2 ISMVL 2, May 2, Tuusula, Finland

17 Rversible Logic Synhesis using PPRM Expression Posiive Davio expansion on all variables resuls ino PPRM expression ISMVL 2, May 2, Tuusula, Finland 2 2 ),,, ( f x f x x x f i n ),,,,,, ( n i i x x x x f f ),,,,,, ( n i i x x x x f f 2 f f f

18 Rversible Logic Synhesis using PPRM Expression (cond.) An n-variable PPRM expression can be represened as f f ( x, x2,, xn) x n x n n ( i {,} ) f {,} i f f x x 2 f x x n n x n f x n ISMVL 2, May 2, Tuusula, Finland

19 Rversible Logic Synhesis using PPRM Expression (cond.) AB F f f f 2 A Expansion on B f f f f f f 2 f 2 Figure 3. ompuaion of PPRM coefficiens from oupu vecor f f f f f f f f 2 f 2 f 2 f 2 ISMVL 2, May 2, Tuusula, Finland

20 AB F f f f 2 A Expansion on B f f f f f f 2 f 2 f f f f f f f f 2 f 2 f 2 f 2 B B A A AB AB F( A, B, ) B A A Figure 3. ompuaion of PPRM coefficiens from oupu vecor ISMVL 2, May 2, Tuusula, Finland

21 Rversible Logic Synhesis using PPRM Expression (cond.) The PPRM expression is wrien from he T final coefficien vecor [] The resuling PPRM expression for he given funcion in Figure 3 is F( A, B, ) B A A ISMVL 2, May 2, Tuusula, Finland

22 Rversible Logic Synhesis using PPRM Expression (cond.) The PPRM expression can be realized as a cascade of Feynman and Toffoli gaes A B B B Figure 4. Realizaion of PPRM expression as cascade of Feynman and Toffoli gaes A A B F B A A ISMVL 2, May 2, Tuusula, Finland

23 Synhesis of Synchronous ouner We consruc ruh able considering he clock inpu and he presen saes as he inpus and considering he nex saes as he oupus Then we calculae PPRM expression of all he oupus and realize hem as cascade of Feynman and Toffoli gaes The feedback from he nex sae oupu o he presen sae inpu is done by making a copy of he nex sae oupu using Feynman gae ISMVL 2, May 2, Tuusula, Finland

24 Synhesis of Synchronous ouner (cond.) The synhesized couner is a level-riggered sequenial circui and clock pulse widh has o deermined based on he oal delay of he circui SHOULD WE DO THIS FOR REVERSIBLE SIMULATE? uanum? uanum is differen ISMVL 2, May 2, Tuusula, Finland

25 Synhesis of Synchronous ouner (cond.) Inpu Oupu PPRM oefficiens TABLE II. Truh able and PPRM coefficiens of he nex sae oupus for mod 8 up couner ISMVL 2, May 2, Tuusula, Finland

26 Synhesis of Synchronous ouner (cond.) The PPRM expressions for he nex sae oupus are 2 2 ISMVL 2, May 2, Tuusula, Finland

27 Synhesis of Synchronous ouner by direc mehod os = 9 Garbage = 2 Figure 5. Reversible circui for mod 8 up couner ISMVL 2, May 2, Tuusula, Finland

28 2 T2 2 T 2 2 T iniializaion 2 2 Modulo 8 couner 2 + = 2 + = + = 2 Exernal feedback wires Figure 5. Reversible circui for mod 8 up couner.

29 Synhesis of Synchronous ouner (cond.) 2 T2 2 T 2 T Figure 6. Tradiional circui for mod 8 up couner ISMVL 2, May 2, Tuusula, Finland

30 mod 8 up couner by replacemen mehod: T T T Figure 7. Reversible circui for mod 8 up couner afer replacemen of he T flip-flops and AND gaes of Figure 6 by heir reversible couner pars. os = 24 Garbage = 4

31 Direc Synhesis of Mod 6 Synchronous ouner We can deermine he PPRM expressions for he nex sae oupus of mod 6 up couner as follows ISMVL 2, May 2, Tuusula, Finland

32 Direc Synhesis of Mod 6 Synchronous ouner os = 35 Garbage = 4 Figure 8. Reversible circui for mod 6 up couner ISMVL 2, May 2, Tuusula, Finland

33 Synhesis of classical Mod 6 Synchronous ouner 3 2 T 3 3 T2 2 T 2 T Figure 9. Tradiional circui for mod 6 up couner ISMVL 2, May 2, Tuusula, Finland

34 Direc Synhesis of Reversible circui for mod 6 up couner. combinaional Exernal quanum memory

35 Flip-flop replacemen mehod for Reversible circui for mod 6 up couner. T T T2 2 T3 2 3 Figure. Reversible circui for mod 6 up couner afer replacemen of he T flip-flops and AND gaes of Figure 9 by heir reversible couner pars.

36 Synhesis of Synchronous ouner (cond.) TABLE III. omparison of our direc design and replacemen echnique for mod 8 and mod 6 up couners Our direc echnique Replacemen echnique ouner os Garbage os Garbage mod mod ONLUSION: Our mehod creaes couners of smaller quanum cos and number of garbages han he previous mehods ISMVL 2, May 2, Tuusula, Finland

37 Synhesis of Synchronous ouner (cond.) PPRM expressions of he nex sae oupus can be wrien in general erms as follows i i ( i ) ( i 2) for i = for i > These generalized PPRM expressions allow us o implemen any up couner direcly from reversible gaes very efficienly ISMVL 2, May 2, Tuusula, Finland

38 onclusions. Reversible logic is very imporan for low power and quanum circui design. 2. Mos of he aemps on reversible logic design concenrae on reversible combinaional logic design [9-22]. 3. Only a few aemps were made on reversible sequenial circui design [23-28, 32-35]. 4. The major works on reversible sequenial circui design [23-27] propose implemenaions of flip-flops and sugges ha sequenial circui be consruced by replacing he flip-flops and gaes of he radiional designs by heir reversible couner pars.

39 onclusions 2 These mehods produce circuis wih high realizaion coss and many garbages We presen a mehod of synchronous couner design direcly from reversible gaes This mehod produces circui wih lesser realizaion cos and lesser garbage oupus The proposed mehod generaes expressions for he nex sae oupus, which can be expressed in general erms for all up couners ISMVL 2, May 2, Tuusula, Finland

40 onclusions 3 This generalizaion of he expressions for he nex sae oupus makes synchronous up couner design very easy and efficien. Tradiionally, sae minimizaion and sae assignmen are pars of he enire synhesis procedure of finie sae machines. The role of hese wo processes in he realizaion of reversible sequenial circuis [32,34] has been invesigaed by us I should be furher invesigaed. ISMVL 2, May 2, Tuusula, Finland

41 onclusions 4 We showed a mehod ha is specialized o cerain ype of couners. We creaed a similar mehod for quanum circuis which is specialized o oher ypes of couners T flip-flops are good for couners T flip-flops are good for arbirary sae machines realized in reversible circuis. Exciaion funcions of T ffs are realized as producs of EXORs of lierals and Inclusive Sums of lierals Don cares should be used o realize funcions of he form: i i abc d e Linear variable decomposiion Kernopf Habiliaion

42

43 H. Thapliyal and A.P. Vinod, Design of reversible sequenial elemens wih feasibiliy of ransisor implemenaion, Inernaional Symposium on ircuis and Sysems (ISAS 27), 27, pp S. Bandyopadhyay, Nanoelecric implemenaion of reversible and quanum logic, Supperlaices and Microsrucures, vol. 23, 998, pp H. Wood and D.J. hen, Fredkin gae circuis via recombinaion enzymes, Proceedings of ongress on Evoluionary ompuaion (E), vol. 2, 24, pp S.K.S. Hari, S. Shroff, S.N. Mohammad, and V. Kamakoi, Efficien building blocks for reversible sequenial circui design, IEEE Inernaional Midwes Symposium on ircuis and Sysems (MWSAS), 26.

44 M.-L. huang and.-y. Wang, Synhesis of reversible sequenial elemens, AM journal of Engineering Technologies in ompuing Sysems (JET), vol. 3, no. 4, 28. A. Banerjee and A. Pahak, New designs of Reversible sequenial devices, arxiv:98.62v [quan-ph] 2 Aug 29. M. Kumar, S. Boshra-riad, Y. Nachimuhu and M. Perkowski, omparison of Sae Assignmen mehods for "uanum ircui" Model of permuaive uanum Sae Machines, Proc. E 2. M. Lukac and M. Perkowski, Evolving uanum Finie Sae Machines for Sequence Deecion, Book chaper, New Achievemens in Evoluionary ompuaion, Peer Korosec (Eds.), URL: hp://sciyo.com/books/show/ile/new-achievemens-in-evoluionarycompuaion, ISBN: , 2 M. Kumar, S. Boshra-riad, Y. Nachimuhu, and M. Perkowski, Engineering Models and ircui Realizaion of uanum Sae Machines, Proc. 8 h Inernaional Workshop on Pos- Binary ULSI Sysems, May 2, 29, Okinawa. M. Lukac, M. Kameyama, and M. Perkowski, uanum Finie Sae Machines - a ircui Based Approach, uanum Informaion Processing, acceped wih revisions