Timed Automata lllllllllll Decidability Results

Size: px
Start display at page:

Download "Timed Automata lllllllllll Decidability Results"

Transcription

1 Timed Automata lllllllllll Decidability Results

2 Decidability? a c b OBSTACLE: Uncountably infinite state space Reachable?

3

4

5

6 Stable Quotient Partitioning a c b y y x Reachable? x

7 Stable Quotient Partitioning a c b y y x Reachable? x

8 Stable Quotient Partitioning a c b y y x Reachable? x

9 Stable Quotient Partitioning a c b y y x Reachable? x

10 Stable Quotient Partitioning a c b y y x Reachable? x

11 Stable Quotient Partitioning a c b y y x Reachable? 0 ε 1 a 2 ε 3 a 4 ε 5 c 6 x

12

13 Regions Finite Partitioning of State Space y x An equivalence class (i.e. a region) in fact there is only a finite number of regions!!

14

15

16 Regions Successor Operation (wrt delay) y 2 1 r x Successor regions, Succ(r) An equivalence class (i.e. a region)

17 Regions Reset Operation y {x}r 2 1 Reset regions r {y}r x An equivalence class (i.e. a region) r

18 An Example Region Graph

19 Modified light switch AG( x y) AG( on AG( on AFoff ) AF 9 off )

20 Reachable part of region graph Properties AG( x y) AG( on AFoff ) AG( on AF 9 off )

21

22

23

24 Fundamental Results PSPACE-c Reachability Alur, Dill Trace-inclusion Alur, Dill Timed ; Untimed Bisimulation Timed Cerans ; Untimed Model-checking TCTL, T mu, L nu,... PSPACE-c / EXPTIME-c

25 Updatable Timed Automata W Diagonals Patricia Bouyer, Catherine Dufourd, Emmanuel Fleury, Antoine Petit W Diagonals

26 TCTL: Timed Computational Tree Logic

27 TCTL = CTL + Time p z α z inφ AP, D, automic formula propositio ns, clocks, constraints over formula clocks and automata clocks freeze operator introduces new formula clock z E[ φ U φ ], A[ φ U φ ] - like in CTL No EX φ

28 Derived Operators = Along any path φ holds continuously until within 7 time units ψ becomes valid. = The property φ becomes valid within 5 time units.

29 Paths Example: push push click y 9 9)... 0,, ( 9) 3), ( 9, ( 3) 3,, ( ) 0,, ( ), ( 0), ( 3.5), ( 0), ( 3) ( = = = + = + = = = = = = = = = = = = + y x off y x on y x on y x on y x on y x on y x off y x off click push push π π π π π π

30 Elapsed time in path 9)... 0,, ( 9) 3), ( 9, ( 3) 3,, ( ) 0,, ( ), ( 0), ( 3.5), ( 0), ( 3) ( = = = + = + = = = = = = = = = = = = + y x off y x on y x on y x on y x on y x on y x off y x off click push push π π π π π π Example: Δ(σ,1)=3.5, Δ(σ,6)=3.5+9=12.5 σ=

31 TCTL Semantics s - location w - formula clock valuation PM(s) - set of paths from s Pos(σ) - positions in σ Δ(σ,i) - elapsed time (i,d) <<(i,d ) iff (i<j) or ((i=j) and (d<d ))

32 Timeliness Properties receive(m) occurs within 5 time units after send(m) receive(m) occurs exactly 11 time units after send(m) putbox occurs periodically (exactly) every 25 time units (note: other putbox s may occur in between)

33 The UPPAAL Verification Engine

34 Overview Zones and DBMs Minimal Constraint Form Clock Difference Diagrams Distributed UPPAAL [CAV2000, STTT2004] Unification & Sharing [FTRTFT2002, SPIN2003] Acceleration [FORMATS2002] Static Guard Analysis [TACAS2003,TACAS2004] Storage-Strategies [CAV2003]

35 Zones From infinite to finite y State (n, x=3.2, y=2.5 ) x y Symbolic state (set) (n, 1 x 4, 1 y 3) x Zone: conjunction of x-y<=n, x<=>n

36 Symbolic Transitions x>3 a y:=0 n m y y x x 1<=x<=4 1<=y<=3 delays to conjuncts to projects to y y x x 1<=x, 1<=y -2<=x-y<=3 3<x, 1<=y -2<=x-y<=3 3<x, y=0 Thus Thus (n,1<=x<=4,1<=y<=3) =a =a => => (m,3<x, y=0) y=0)

37 Zones = Conjuctive Constraints A zone Z is a conjunctive formula: g 1 & g 2 &... & g n where g i is a clock constraint x i ~ b i or x i -x j ~b ij Use a zero-clock x 0 (constant 0) A zone can be re-written as a set: {x i -x j ~b ij ~ is < or, i,j n} This can be represented as a matrix, DBM (Difference Bound Matrices)

38 Operations on Zones Future delay Z : Past delay Z : [Z ] = {u+d d R, u [Z]} [Z ] = {u u+d [Z] for some d R} Reset: {x}z or Z(x:=0) Conjunction [{x}z] = {u[0/x] u [Z]} [Z&g]= [Z] [g]

39 THEOREM The set of zones is closed under all constraint operations. That is, the result of the operations on a zone is a zone. That is, there will be a zone (a finite object i.e a zone/constraints) to represent the sets: [Z ], [Z ], [{x}z], [Z&g].

40 Symbolic Exploration y Reachable? x

41 Symbolic Exploration y Reachable? Delay x

42 Symbolic Exploration y Reachable? Left x

43 Symbolic Exploration y Reachable? Left x

44 Symbolic Exploration y Reachable? Delay x

45 Symbolic Exploration y Reachable? Left x

46 Symbolic Exploration y Reachable? Left x

47 Symbolic Exploration y Reachable? Delay x

48 Symbolic Exploration y Reachable? Down x

49 Fischer s Protocol analysis using zones Init V=1 2 V X<10 X:=0 X>10 V:=1 V=1 A1 B1 CS1 Y<10 Y:=0 Y>10 V:=2 V=2 A2 B2 CS2 Criticial Section

50 Fischers cont. X<10 A1 X:=0 V:=1 V=1 B1 X>10 CS1 Untimed case Y<10 Y:=0 Y>10 A2 V:=2 V=2 B2 CS2 A1,A2,v=1 A1,B2,v=2 A1,CS2,v=2 B1,CS2,v=1 CS1,CS2,v=1

51 Fischers cont. X<10 A1 X:=0 V:=1 V=1 B1 X>10 CS1 Untimed case Y<10 Y:=0 Y>10 A2 V:=2 V=2 B2 CS2 A1,A2,v=1 A1,B2,v=2 A1,CS2,v=2 B1,CS2,v=1 CS1,CS2,v=1 Taking time into account Y X

52 Fischers cont. X<10 A1 X:=0 V:=1 V=1 B1 X>10 CS1 Untimed case Y<10 Y:=0 Y>10 A2 V:=2 V=2 B2 CS2 A1,A2,v=1 A1,B2,v=2 A1,CS2,v=2 B1,CS2,v=1 CS1,CS2,v=1 Taking time into account Y 10 X Y X

53 Fischers cont. X<10 A1 X:=0 V:=1 V=1 B1 X>10 CS1 Untimed case Y<10 Y:=0 Y>10 A2 V:=2 V=2 B2 CS2 A1,A2,v=1 A1,B2,v=2 A1,CS2,v=2 B1,CS2,v=1 CS1,CS2,v=1 Taking time into account Y 10 X Y X

54 Fischers cont. X<10 A1 X:=0 V:=1 V=1 B1 X>10 CS1 Untimed case Y<10 Y:=0 Y>10 A2 V:=2 V=2 B2 CS2 A1,A2,v=1 A1,B2,v=2 A1,CS2,v=2 B1,CS2,v=1 CS1,CS2,v=1 Taking time into account Y 10 X Y X Y X

55 Fischers cont. X<10 A1 X:=0 V:=1 V=1 B1 X>10 CS1 Untimed case Y<10 Y:=0 Y>10 A2 V:=2 V=2 B2 CS2 A1,A2,v=1 A1,B2,v=2 A1,CS2,v=2 B1,CS2,v=1 CS1,CS2,v=1 Taking time into account Y 10 X Y X Y X

56 Forward Rechability Init -> Final? Init Waiting Passed Final INITIAL Passed := Ø; Waiting := {(n0,z0)} REPEAT - pick (n,z) in Waiting - if for some Z Z (n,z ) in Passed then STOP -else (explore) add { (m,u) : (n,z) => (m,u) } to Waiting; Add (n,z) to Passed UNTIL Waiting = Ø or Final is in Waiting

57 Forward Rechability Init -> Final? Waiting n,z Init n,z Passed Final INITIAL Passed := Ø; Waiting := {(n0,z0)} REPEAT - pick (n,z) in Waiting - if for some Z Z (n,z ) in Passed then STOP -else(explore) add { (m,u) : (n,z) => (m,u) } to Waiting; Add (n,z) to Passed UNTIL Waiting = Ø or Final is in Waiting

58 Forward Rechability Init -> Final? Waiting n,z Init n,z m,u Passed Final INITIAL Passed := Ø; Waiting := {(n0,z0)} REPEAT - pick (n,z) in Waiting - if for some Z Z (n,z ) in Passed then STOP -else/explore/ add { (m,u) : (n,z) => (m,u) } to Waiting; Add (n,z) to Passed UNTIL Waiting = Ø or Final is in Waiting

59 Forward Rechability Init -> Final? Waiting n,z Init n,z m,u Passed Final INITIAL Passed := Ø; Waiting := {(n0,z0)} REPEAT - pick (n,z) in Waiting - if for some Z Z (n,z ) in Passed then STOP -else/explore/ add { (m,u) : (n,z) => (m,u) } to Waiting; Add (n,z) to Passed UNTIL Waiting = Ø or Final is in Waiting

60 Canonical Datastructures for Zones Difference Bounded Matrices Bellman 1958, Dill 1989 Inclusion D1 D2 x<=1 x<=1 y-x<=2 z-y<=2 z-y<=2 z<=9 z<=9 x<=2 x<=2 y-x<=3 y<=3 y<=3 z-y<=3 z-y<=3 z<=7 z<=7 Graph Graph x 2 9 z 2?? 2 x z 3 y y

61 Canonical Datastructures for Zones Difference Bounded Matrices Inclusion D1 D2 x<=1 x<=1 y-x<=2 z-y<=2 z-y<=2 z<=9 z<=9 x<=2 x<=2 y-x<=3 y<=3 y<=3 z-y<=3 z-y<=3 z<=7 z<=7 Graph Graph 0 0 x z 2 2 x 3 3 7?? z 3 y y Shortest Path Closure Shortest Path Closure 0 0 x z x y 2 z 3 y

62 Canonical Datastructures for Zones Difference Bounded Matrices Emptiness Compact D x<=1 x<=1 y>=5 y>=5 y-x<=3 Graph x y 3 Negative Cycle iff empty solution set

63 Canonical Datastructures for Zones Difference Bounded Matrices Future D y 1<= 1<= x <=4 <=4 1<= 1<= y <=3 <= x y x Shortest Path Closure x 3 2 y y Remove upper bounds on clocks x Future D 1<=x, 1<=x, 1<=y 1<=y -2<=x-y<=3 x y

64 Canonical Datastructures for Zones Difference Bounded Matrices Reset D y 0-1 x 1<=x, 1<=x, 1<=y 1<=y -2<=x-y<=3 x y {y}d y Remove all bounds involving y and set y to x y=0, y=0, 1<=x 1<=x -1 0 x y

65 Canonical Datastructures for Zones Difference Bounded Matrices x1-x2<=4 x1-x2<=4 x2-x1<=10 x2-x1<=10 x3-x1<=2 x3-x1<=2 x2-x3<=2 x2-x3<=2 x0-x1<=3 x0-x1<=3 x3-x0<=5 x3-x0<=5 3 x1 x x2 x3 2 Shortest Path Closure O(n^3) x1 x2 x x3 2

66 Canonical Datastructures for Zones Minimal Constraint Form RTSS 1997 x1-x2<=4 x1-x2<=4 x2-x1<=10 x2-x1<=10 x3-x1<=2 x3-x1<=2 x2-x3<=2 x2-x3<=2 x0-x1<=3 x0-x1<=3 x3-x0<=5 x3-x0<=5 3 x1 x x2 x3 Shortest Path Reduction O(n^3) x1 2 Shortest Path Closure O(n^3) -4 x2 2 3 x1-4 4 x x0 1 x3 5 2 Space worst O(n^2) practice O(n) x0 x3

67 1 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 Percent SPACE PERFORMANCE Minimal Constraint Global Reduction Combination M. Plant Fischer 2 Fischer 3 Fischer 4 Fischer 5 Train Crossing Box Sorter B&O Audio Audio w Col

68 2,5 2 1,5 1 0,5 0 Percent TIME PERFORMANCE Minimal Constraint Global Reduction Combination M. Plant Fischer 2 Fischer 3 Fischer 4 Fischer 5 Train Crossing B&O Box Sorter Audio Audio w Col

69 Shortest Path Reduction 1st attempt Idea Problem w w v <=w An An edge is is REDUNDANT if if there exists an an alternative path path of of no no greater weight THUS Remove all all redundant edges! v and and w are are both both redundant Removal of of one one depends on on presence of of other. Observation: If If no no zero- or or negative cycles then then SAFE to to remove all all redundancies.

70 Shortest Path Reduction Solution G: weighted graph

71 Shortest Path Reduction Solution G: weighted graph 1. Equivalence classes based on 0-cycles.

72 Shortest Path Reduction Solution G: weighted graph 1. Equivalence classes based on 0-cycles. 2. Graph based on representatives. Safe to remove redundant edges

73 Shortest Path Reduction Solution G: weighted graph Canonical given order of clocks 1. Equivalence classes based on 0-cycles. 2. Graph based on representatives. Safe to remove redundant edges 3. Shortest Path Reduction = One cycle pr. class + Removal of redundant edges between classes

74 Earlier Termination Init -> Final? Waiting n,z Init n,z m,u Passed Final INITIAL Passed := Ø; Waiting := {(n0,z0)} REPEAT - pick (n,z) in Waiting - if for some Z Z (n,z ) in Passed then STOP -else/explore/ add { (m,u) : (n,z) => (m,u) } to Waiting; Add (n,z) to Passed UNTIL Waiting = Ø or Final is in Waiting

75 Earlier Termination Init -> Final? Waiting n,z Init n,z m,u Passed Final INITIAL Passed := Ø; Waiting := {(n0,z0)} REPEAT - pick (n,z) in Waiting - if for some Z' Z Z Z (n,z ) in Passed then STOP -else/explore/ add { (m,u) : (n,z) => (m,u) } to Waiting; Add (n,z) to Passed UNTIL Waiting = Ø or Final is in Waiting

76 Earlier Termination Init -> Final? Waiting n,z 1 n,z 2 n,z k Init n,z m,u Final U i Z Passed i INITIAL Passed := Ø; Waiting := {(n0,z0)} REPEAT - pick (n,z) in Waiting - if for some Z' Z (n,z ) in Passed then STOP -else/explore/ add { (m,u) : (n,z) => (m,u) } to Waiting; Add (n,z) to Passed Z UNTIL Waiting = Ø or Final is in Waiting

77 Clock Difference Diagrams = Binary Decision Diagrams + Difference Bounded Matrices CAV99 CDD-representations Nodes labeled with differences Maximal sharing of substructures (also across different CDDs) Maximal intervals Linear-time algorithms for set-theoretic operations. NDD s Maler et. al DDD s Møller, Lichtenberg

78 4,5 4 3,5 3 2,5 2 1,5 1 0,5 0 SPACE PERFORMANCE CDD Reduced CDD CDD+BDD Fischer5 PowerDown1 PowerDown2 Dacapo GearBox Fischer4 BRP B&O Percent Philips Philps col

79 TIME PERFORMANCE CDD Reduced CDD CDD+BDD BRP PowerDown1 PowerDown2 Dacapo GearBox Fischer4 Fischer5 B&O Percent Philips Philps col

80 UPPAAL Dec 96 Sep 98 Every 9 month 10 times better performance! 3.x

81 Liveness Checking

82 in UPPAAL Liveness Properties F ::= E P A P P Q Bouajjani, Tripakis, Yovine 97 On-the-fly symbolic model checking of TCTL Possibly always P Eventually P is equivalent to ( E P) P leads to Q is equivalent to A ( P A Q)

83 in UPPAAL Liveness E[]φ (A φ)

84 in UPPAAL Passed (A φ) Liveness E[]φ (A φ) ST WS Unexplored

85 in UPPAAL Passed (A φ) Liveness E φ (A φ) ST WS Unexplored

86 in UPPAAL Passed (A φ) Liveness E φ (A φ) ST WS Unexplored

87 in UPPAAL Passed (A φ) Liveness E φ (A φ) ST WS Unexplored

88 in UPPAAL Passed (A φ) Liveness E φ (A φ) ST WS Unexplored?

89 in UPPAAL Passed (A φ) Liveness E φ (A φ) ST WS Unexplored???

90 Liveness E φ (A φ) in UPPAAL Passed (A φ) ST WS Unexplored [FORMATS05] Extensions allowing for automatic synthesis of smallest bound t such that A t φ holds

91 Verification Options

92 Verification Options Search Order Depth First Breadth First State Space Reduction None Conservative Aggressive State Space Representation DBM Compact Form Under Approximation Over Approximation Diagnostic Trace Some Shortest Fastest Extrapolation Hash Table size Reuse

93 State Space Reduction However, Passed list useful for efficiency No Cycles: Passed list not needed for termination

94 State Space Reduction Cycles: Only symbolic states involving loop-entry points need to be saved on Passed list

95 To Store or Not To Store 117 states total 81 states entrypoint 9 states Time OH less than 10% Behrmann, Larsen, Pelanek 2003 Audio Protocol

96 To Store or Not to Store Behrmann, Larsen, Pelanek 2003

97 Over-approximation Convex Hull y x Convex Hull TACAS04: An EXACT method performing as well as Convex Hull has been developed based on abstractions taking max constants into account distinguishing between clocks, locations and &

98 Under-approximation Bitstate Hashing Waiting Init n,z n,z m,u Passed Final

99 Under-approximation Bitstate Hashing Waiting Init n,z n,z m,u Passed Final Hashfunction F Passed= Bitarray UPPAAL 8 Mbits

100 Modelling Patterns

101 Variable Reduction Reduce size of state space by explicitely resetting variables when they are not used! Automatically performed for clock variables (active clock reduction)

102 Clock Reduction x<7 x is only active in location S1 x:=0 S Definition x is inactive at S if on all path from S, x is always reset before being tested. x:=0 x<5 x>3

103 Synchronous Value Passing

104 Atomicity To allow encoding of control structure (foror while-loops, conditionals, etc.) without erroneous interleaving To allow encoding of multicasting. Heavy use of committed locations.

105 Bounded Liveness Intent: Check for properties that are guaranteed to hold eventually within some upper (time) bound. Provide additional information (with a valid bound). More efficient verification. φ leadsto t ψ reduced to A (b z t) with bool b set to true and clock z reset when φ starts to hold. When ψ starts to hold, set b to false.

106 Bounded Liveness The truth value of b indicates whether or not ψ should hold in the future. φ b=true z=0 φ b=false ψ b=false ψ A[] (b imply z t) b --> not b (for non zenoness) E<> b (for meaningful check) b true, check z t

107 Timers Parametric timer: (re-)start(value) start! var=value expired? active (bool) active go? (bool+urgent chan) time-out event timeout? Declare to with a tight range.

108 Zenoness Problem: UPPAAL does not check for zenoness directly. A model has zeno behavior if it can take an infinite amount of actions in finite time. That is usually not a desirable behavior in practice. Zeno models may wrongly conclude that some properties hold though they logically should not. Rarely taken into account. Solution: Add an observer automata and check for non-zenoness, i.e., that time will always pass.

109 Zenoness x 1 Zeno OK x x==1 1 x=0 x 1 Detect by adding the observer: Constant (10) can be anything (>0), but choose it well w.r.t. your model for efficiency. Clocks x are local. and check the property ZenoCheck.A --> ZenoCheck.B

110 Compositionality & Abstraction

111 The State Explosion Problem Sys a b c a b c a a a b c b c b c a a a b c b c b c sat ϕ Model-checking is is either EXPTIME-complete or or PSPACE-complete (for TA s this is is true even for for a single TA)

112 Abstraction ϕ ϕ Sys sat Abs Sys sat Abs a c b a c b a c b a c b a c b a c b a c b a c b ϕ sat Sys ϕ sat Abs REDUCE TO Preserving safety properties

113 Compositionality Sys b b a a a a c b c b c b c a a a a c b c b c b c Sys 1 Sys 2 Abs 1 Abs Sys 1 Sys 1 Sys2 Sys Sys 1 Sys 2 2 Abs Abs Abs Abs1 Abs2 Abs Sys Abs 1 Abs2 Abs Abs 2

114 Abstraction & Compositionality dealing w stateexplosion a c b a c b a c b a c b a c b a c b a c b a c b A A C C A C A C p p p Concrete Abstract trace inclusion

115 Abstraction Example a1 a2 a3 a4 a5 a b

116 Example Continued abstracted by

117 Proving abstractions using reachability Applied to IEEE 1394a Root contention protocol (Simons, Stoelinga) B&O Power Down Protocol (Ejersbo, Larsen, Skou, FTRTFT2k) A[] not TestAbstPoP1.BAD Recognizes all the BAD computations of PoP1 Henrik Ejersbo Jensen PhD Thesis 1999

118 Further Optimizations

119 Datastructures for Zones Difference Bounded Matrices (DBMs) Minimal Constraint Form [RTSS97] Clock Difference Diagrams [CAV99] PW List [SPIN03] x1 x2 x x3 2

120 Datastructures for Zones Difference Bounded Matrices (DBMs) Minimal Constraint Form [RTSS97] Clock Difference Diagrams [CAV99] PW List [SPIN03] -4 x1 x Alexandre -2 2 David Elegant x0 RUBY 1bindings x3 for easy implementations 5

121 Zone Abstractions [TACAS03,TACAS04] Abstraction taking maximum constant into account necessary for termination Utilization of distinction between lower and upper bounds Utilization of location-dependency

122 LU Abstraction [TACAS04] THEOREM For any state in the LU- abstraction there is a state in the original set simulating it LU abstraction is exact wrt reachability

123 Zone abstractions Classical Loc. dep. Max Loc. dep. LU Convex Hull

124 Symmetry Reduction Exploitation of full symmetry may give factorial reduction Many timed systems are inherently symmetric Computation of canonical state representative using swaps. [Formats 2003]

125 Symmetry Reduction Exploitation of full symmetry may give factorial reduction Many timed systems are inherently symmetric Computation of canonical state representative using swaps. [Formats 2003] SWAP: 1 2 ; 3 4

126 Symmetry Reduction [Formats 2003]

127 Symmetry Reduction UPPAAL 3.6 [Formats 2003] Iterators for (i: int[0,4]) { } Quantifiers Selection forall (i: int[0,4]) a[i]==0 select i: int[0,4]; guard... Template sets process P[4](...) { } Scalar set based symmetry reduction Compact state-space representations Priorities Gerd Behrmann 10 Martijn Henriks, Nijmegen U

128 D-UPPAAL Gerd Behrmann Distributed implementation of UPPAAL on PC-cluster [CAV'00, PDMC'02, STTT'03]. WWW frontend available Applications Synthesis of Dynamic Voltage Scaling strategies (CISS). Ad-hoc mobile real-time protocol (Leslie Lamport) - 25GB in 3 min! Running on NorduGrid. Local cluster: 50 CPUs and 50GB of RAM To be used as inspiration for verification GRID platform within ARTIST2 NoE.

129 D-UPPAAL Gerd Behrman Distributed implementation of UPPAAL on PC-cluster [CAV'00, PDMC'02, STTT'03]. WWW frontend available. Applications Synthesis of Dynamic Voltage Scaling strategies (CISS). Ad-hoc mobile real-time protocol (Leslie Lamport) - 25GB in 3 min! Running on NorduGrid. Local cluster: 50 CPUs and 50GB of RAM To be used as inspiration for verification GRID platform within ARTIST2 NoE.

130 D-UPPAAL Gerd Behrman Distributed implementation of UPPAAL on PC-cluster [CAV'00, PDMC'02, STTT'03]. Applications Synthesis of Dynamic Voltage Scaling strategies (CISS). Ad-hoc mobile real-time protocol (Leslie Lamport) - 25GB in 3 min! Running on NorduGrid. Local cluster: 50 CPUs and 50GB of RAM To be used as inspiration for verification GRID platform within ARTIST2 NoE.

Symbolic Real Time Model Checking. Kim G Larsen

Symbolic Real Time Model Checking. Kim G Larsen Smbolic Real Time Model Checking Kim G Larsen Overview Timed Automata Decidabilit Results The UPPAAL Verification Engine Datastructures for zones Liveness Checking Algorithm Abstraction and Compositionalit

More information

UPPAAL tutorial What s inside UPPAAL The UPPAAL input languages

UPPAAL tutorial What s inside UPPAAL The UPPAAL input languages UPPAAL tutorial What s inside UPPAAL The UPPAAL inut languages 1 UPPAAL tool Develoed jointly by Usala & Aalborg University >>8,000 downloads since 1999 1 UPPAAL Tool Simulation Modeling Verification 3

More information

Models for Efficient Timed Verification

Models for Efficient Timed Verification Models for Efficient Timed Verification François Laroussinie LSV / ENS de Cachan CNRS UMR 8643 Monterey Workshop - Composition of embedded systems Model checking System Properties Formalizing step? ϕ Model

More information

Formal methods & Tools. UPPAAL Implementation Secrets. Kim Guldstrand Larsen & UCb

Formal methods & Tools. UPPAAL Implementation Secrets. Kim Guldstrand Larsen & UCb Formal methods & Tools UPPAAL Implementation Secrets Kim Guldstrand Larsen BRICS@Aalborg & FMT@Twente Collaborators @UPPsala Wang Yi Paul Pettersson Johan Bengtsson Fredrik Larsson Alexandre David Tobias

More information

for System Modeling, Analysis, and Optimization

for System Modeling, Analysis, and Optimization Fundamental Algorithms for System Modeling, Analysis, and Optimization Stavros Tripakis UC Berkeley EECS 144/244 Fall 2013 Copyright 2013, E. A. Lee, J. Roydhowdhury, S. A. Seshia, S. Tripakis All rights

More information

Timed Automata. Semantics, Algorithms and Tools. Zhou Huaiyang

Timed Automata. Semantics, Algorithms and Tools. Zhou Huaiyang Timed Automata Semantics, Algorithms and Tools Zhou Huaiyang Agenda } Introduction } Timed Automata } Formal Syntax } Operational Semantics } Verification Problems } Symbolic Semantics & Verification }

More information

Analysis of a Boost Converter Circuit Using Linear Hybrid Automata

Analysis of a Boost Converter Circuit Using Linear Hybrid Automata Analysis of a Boost Converter Circuit Using Linear Hybrid Automata Ulrich Kühne LSV ENS de Cachan, 94235 Cachan Cedex, France, kuehne@lsv.ens-cachan.fr 1 Introduction Boost converter circuits are an important

More information

Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods

Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods Sanjit A. Seshia and Randal E. Bryant Computer Science Department Carnegie Mellon University Verifying Timed Embedded Systems

More information

Folk Theorems on the Determinization and Minimization of Timed Automata

Folk Theorems on the Determinization and Minimization of Timed Automata Folk Theorems on the Determinization and Minimization of Timed Automata Stavros Tripakis VERIMAG Centre Equation 2, avenue de Vignate, 38610 Gières, France www-verimag.imag.fr Abstract. Timed automata

More information

Controller Synthesis with UPPAAL-TIGA. Alexandre David Kim G. Larsen, Didier Lime, Franck Cassez, Jean-François Raskin

Controller Synthesis with UPPAAL-TIGA. Alexandre David Kim G. Larsen, Didier Lime, Franck Cassez, Jean-François Raskin Controller Synthesis with UPPAAL-TIGA Alexandre David Kim G. Larsen, Didier Lime, Franck Cassez, Jean-François Raskin Overview Timed Games. Algorithm (CONCUR 05). Strategies. Code generation. Architecture

More information

Modelling Real-Time Systems. Henrik Ejersbo Jensen Aalborg University

Modelling Real-Time Systems. Henrik Ejersbo Jensen Aalborg University Modelling Real-Time Systems Henrik Ejersbo Jensen Aalborg University Hybrid & Real Time Systems Control Theory Plant Continuous sensors actuators Task TaskTask Controller Program Discrete Computer Science

More information

Timed Automata: Semantics, Algorithms and Tools

Timed Automata: Semantics, Algorithms and Tools Timed Automata: Semantics, Algorithms and Tools Johan Bengtsson and Wang Yi Uppsala University {johanb,yi}@it.uu.se Abstract. This chapter is to provide a tutorial and pointers to results and related work

More information

Time(d) Petri Net. Serge Haddad. Petri Nets 2016, June 20th LSV ENS Cachan, Université Paris-Saclay & CNRS & INRIA

Time(d) Petri Net. Serge Haddad. Petri Nets 2016, June 20th LSV ENS Cachan, Université Paris-Saclay & CNRS & INRIA Time(d) Petri Net Serge Haddad LSV ENS Cachan, Université Paris-Saclay & CNRS & INRIA haddad@lsv.ens-cachan.fr Petri Nets 2016, June 20th 2016 1 Time and Petri Nets 2 Time Petri Net: Syntax and Semantic

More information

TCTL model-checking of Time Petri Nets

TCTL model-checking of Time Petri Nets 1 TCTL model-checking of Time Petri Nets Hanifa Boucheneb 1, Guillaume Gardey 2,3 and Olivier H. Roux 2 Affiliations : 1 : École polytechnique de Montréal, C.P. 6079, succ. Centre-ville Montréal H3C3A7

More information

TIMED automata, introduced by Alur and Dill in [3], have

TIMED automata, introduced by Alur and Dill in [3], have 1 Language Inclusion Checking of Timed Automata with Non-Zenoness Xinyu Wang, Jun Sun, Ting Wang, and Shengchao Qin Abstract Given a timed automaton P modeling an implementation and a timed automaton S

More information

Adding Symmetry Reduction to Uppaal

Adding Symmetry Reduction to Uppaal Adding Symmetry Reduction to Uppaal Martijn Hendriks 1 Gerd Behrmann 2 Kim Larsen 2 Peter Niebert 3 Frits Vaandrager 1 1 Nijmegen Institute for Computing and Information Sciences, University of Nijmegen,

More information

A Brief Introduction to Model Checking

A Brief Introduction to Model Checking A Brief Introduction to Model Checking Jan. 18, LIX Page 1 Model Checking A technique for verifying finite state concurrent systems; a benefit on this restriction: largely automatic; a problem to fight:

More information

Specification and Model Checking of Temporal Properties in Time Petri Nets and Timed Automata

Specification and Model Checking of Temporal Properties in Time Petri Nets and Timed Automata Specification and Model Checking of Temporal Properties in Time Petri Nets and Timed Automata WOJCIECH PENCZEK ICS PAS, Warsaw, Poland joint work with Agata Półrola University of Lodz, Poland Many thanks

More information

Recent results on Timed Systems

Recent results on Timed Systems Recent results on Timed Systems Time Petri Nets and Timed Automata Béatrice Bérard LAMSADE Université Paris-Dauphine & CNRS berard@lamsade.dauphine.fr Based on joint work with F. Cassez, S. Haddad, D.

More information

MODEL CHECKING TIMED SAFETY INSTRUMENTED SYSTEMS

MODEL CHECKING TIMED SAFETY INSTRUMENTED SYSTEMS TKK Reports in Information and Computer Science Espoo 2008 TKK-ICS-R3 MODEL CHECKING TIMED SAFETY INSTRUMENTED SYSTEMS Jussi Lahtinen ABTEKNILLINEN KORKEAKOULU TEKNISKA HÖGSKOLAN HELSINKI UNIVERSITY OF

More information

Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1

Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Borzoo Bonakdarpour and Sandeep S. Kulkarni Software Engineering and Network Systems Laboratory, Department of Computer Science

More information

The algorithmic analysis of hybrid system

The algorithmic analysis of hybrid system The algorithmic analysis of hybrid system Authors: R.Alur, C. Courcoubetis etc. Course teacher: Prof. Ugo Buy Xin Li, Huiyong Xiao Nov. 13, 2002 Summary What s a hybrid system? Definition of Hybrid Automaton

More information

Overview. Discrete Event Systems Verification of Finite Automata. What can finite automata be used for? What can finite automata be used for?

Overview. Discrete Event Systems Verification of Finite Automata. What can finite automata be used for? What can finite automata be used for? Computer Engineering and Networks Overview Discrete Event Systems Verification of Finite Automata Lothar Thiele Introduction Binary Decision Diagrams Representation of Boolean Functions Comparing two circuits

More information

Scaling BDD-based Timed Verification with Simulation Reduction

Scaling BDD-based Timed Verification with Simulation Reduction Scaling BDD-based Timed Verification with Simulation Reduction Truong Khanh Nguyen 1,Tian Huat Tan 2, Jun Sun 2, Jiaying Li 2, Yang Liu 3, Manman Chen 2, Jin Song Dong 4 Autodesk 1 Singapore University

More information

Using non-convex approximations for efficient analysis of timed automata: Extended version

Using non-convex approximations for efficient analysis of timed automata: Extended version Using non-convex approximations for efficient analysis of timed automata: Extended version Frédéric Herbreteau, D. Kini, B. Srivathsan, Igor Walukiewicz To cite this version: Frédéric Herbreteau, D. Kini,

More information

Directed Model Checking (not only) for Timed Automata

Directed Model Checking (not only) for Timed Automata Directed Model Checking (not only) for Timed Automata Sebastian Kupferschmid March, 2010 Model Checking Motivation Embedded Systems Omnipresent Safety relevant systems Pentium bug Ariane 5 Errors can be

More information

Algorithms and Data Structures for Efficient Timing Analysis of Asynchronous Real-time Systems

Algorithms and Data Structures for Efficient Timing Analysis of Asynchronous Real-time Systems University of South Florida Scholar Commons Graduate Theses and Dissertations Graduate School 1-1-2013 Algorithms and Data Structures for Efficient Timing Analysis of Asynchronous Real-time Systems Yingying

More information

Robust Controller Synthesis in Timed Automata

Robust Controller Synthesis in Timed Automata Robust Controller Synthesis in Timed Automata Ocan Sankur LSV, ENS Cachan & CNRS Joint with Patricia Bouyer, Nicolas Markey, Pierre-Alain Reynier. Ocan Sankur (ENS Cachan) Robust Control in Timed Automata

More information

Reachability-Time Games on Timed Automata (Extended Abstract)

Reachability-Time Games on Timed Automata (Extended Abstract) Reachability-Time Games on Timed Automata (Extended Abstract) Marcin Jurdziński and Ashutosh Trivedi Department of Computer Science, University of Warwick, UK Abstract. In a reachability-time game, players

More information

Time and Timed Petri Nets

Time and Timed Petri Nets Time and Timed Petri Nets Serge Haddad LSV ENS Cachan & CNRS & INRIA haddad@lsv.ens-cachan.fr DISC 11, June 9th 2011 1 Time and Petri Nets 2 Timed Models 3 Expressiveness 4 Analysis 1/36 Outline 1 Time

More information

Linear Temporal Logic and Büchi Automata

Linear Temporal Logic and Büchi Automata Linear Temporal Logic and Büchi Automata Yih-Kuen Tsay Department of Information Management National Taiwan University FLOLAC 2009 Yih-Kuen Tsay (SVVRL @ IM.NTU) Linear Temporal Logic and Büchi Automata

More information

Abstractions and Decision Procedures for Effective Software Model Checking

Abstractions and Decision Procedures for Effective Software Model Checking Abstractions and Decision Procedures for Effective Software Model Checking Prof. Natasha Sharygina The University of Lugano, Carnegie Mellon University Microsoft Summer School, Moscow, July 2011 Lecture

More information

Symmetry Reductions. A. Prasad Sistla University Of Illinois at Chicago

Symmetry Reductions. A. Prasad Sistla University Of Illinois at Chicago Symmetry Reductions. A. Prasad Sistla University Of Illinois at Chicago Model-Checking Concurrent PGM Temporal SPEC Model Checker Yes/No Counter Example Approach Build the global state graph Algorithm

More information

Efficient Model-Checking of Weighted CTL with Upper-Bound Constraints

Efficient Model-Checking of Weighted CTL with Upper-Bound Constraints Software Tools for Technology Transfer manuscript No. (will be inserted by the editor) Efficient Model-Checking of Weighted CTL with Upper-Bound Constraints Jonas Finnemann Jensen, Kim Guldstrand Larsen,

More information

IMITATOR: A Tool for Synthesizing Constraints on Timing Bounds of Timed Automata

IMITATOR: A Tool for Synthesizing Constraints on Timing Bounds of Timed Automata ICTAC 09 IMITATOR: A Tool for Synthesizing Constraints on Timing Bounds of Timed Automata Étienne ANDRÉ Laboratoire Spécification et Vérification LSV, ENS de Cachan & CNRS Étienne ANDRÉ (LSV) ICTAC 09

More information

Optimal & Real Time Scheduling. using Model Checking Technology. Kim G. Larsen

Optimal & Real Time Scheduling. using Model Checking Technology. Kim G. Larsen Optimal & Real Time Scheduling using Model Checking Technology Kim G. Larsen AIPS a partial observation New community New faces New techniques April 2002 June 2005 IST-2001-35304 Academic partners: Nijmegen

More information

Symbolic Model Checking

Symbolic Model Checking Symbolic Model Checking Ken McMillan 90 Randal Bryant 86 Binary Decision Diagrams 1 Combinatorial Circuits 2 Combinatorial Problems Sudoku Eight Queen 3 Control Programs A Train Simulator, visualstate

More information

Timed Automata VINO 2011

Timed Automata VINO 2011 Timed Automata VINO 2011 VeriDis Group - LORIA July 18, 2011 Content 1 Introduction 2 Timed Automata 3 Networks of timed automata Motivation Formalism for modeling and verification of real-time systems.

More information

Modeling & Control of Hybrid Systems. Chapter 7 Model Checking and Timed Automata

Modeling & Control of Hybrid Systems. Chapter 7 Model Checking and Timed Automata Modeling & Control of Hybrid Systems Chapter 7 Model Checking and Timed Automata Overview 1. Introduction 2. Transition systems 3. Bisimulation 4. Timed automata hs check.1 1. Introduction Model checking

More information

Bounded Model Checking with SAT/SMT. Edmund M. Clarke School of Computer Science Carnegie Mellon University 1/39

Bounded Model Checking with SAT/SMT. Edmund M. Clarke School of Computer Science Carnegie Mellon University 1/39 Bounded Model Checking with SAT/SMT Edmund M. Clarke School of Computer Science Carnegie Mellon University 1/39 Recap: Symbolic Model Checking with BDDs Method used by most industrial strength model checkers:

More information

Liveness in L/U-Parametric Timed Automata

Liveness in L/U-Parametric Timed Automata Liveness in L/U-Parametric Timed Automata Étienne André and Didier Lime [AL17] Université Paris 13, LIPN and École Centrale de Nantes, LS2N Highlights, 14 September 2017, London, England Étienne André

More information

A Modal Specification Theory for Timing Variability

A Modal Specification Theory for Timing Variability University of Pennsylvania ScholarlyCommons Technical Reports (CIS) Department of Computer & Information Science 11-13-2013 A Modal Specification Theory for Timing Variability Andrew King University of

More information

Timed Automata: Semantics, Algorithms and Tools

Timed Automata: Semantics, Algorithms and Tools Timed Automata: Semantics, Algorithms and Tools Johan Bengtsson and Wang Yi Uppsala University Email: {johanb,yi}@it.uu.se Abstract. This chapter is to provide a tutorial and pointers to results and related

More information

Temporal logics and explicit-state model checking. Pierre Wolper Université de Liège

Temporal logics and explicit-state model checking. Pierre Wolper Université de Liège Temporal logics and explicit-state model checking Pierre Wolper Université de Liège 1 Topics to be covered Introducing explicit-state model checking Finite automata on infinite words Temporal Logics and

More information

Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1

Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Borzoo Bonakdarpour and Sandeep S. Kulkarni Software Engineering and Network Systems Laboratory, Department of Computer Science

More information

An introduction to Uppaal and Timed Automata MVP5 1

An introduction to Uppaal and Timed Automata MVP5 1 An introduction to Uppaal and Timed Automata MVP5 1 What is Uppaal? (http://www.uppaal.com/) A simple graphical interface for drawing extended finite state machines (automatons + shared variables A graphical

More information

Computation Tree Logic (CTL) & Basic Model Checking Algorithms

Computation Tree Logic (CTL) & Basic Model Checking Algorithms Computation Tree Logic (CTL) & Basic Model Checking Algorithms Martin Fränzle Carl von Ossietzky Universität Dpt. of Computing Science Res. Grp. Hybride Systeme Oldenburg, Germany 02917: CTL & Model Checking

More information

CS357: CTL Model Checking (two lectures worth) David Dill

CS357: CTL Model Checking (two lectures worth) David Dill CS357: CTL Model Checking (two lectures worth) David Dill 1 CTL CTL = Computation Tree Logic It is a propositional temporal logic temporal logic extended to properties of events over time. CTL is a branching

More information

Beyond Lassos: Complete SMT-Based Bounded Model Checking for Timed Automata

Beyond Lassos: Complete SMT-Based Bounded Model Checking for Timed Automata Beyond Lassos: Complete SMT-Based ed Model Checking for d Automata Roland Kindermann, Tommi Junttila, and Ilkka Niemelä Aalto University Department of Information and Computer Science P.O.Box 15400, FI-00076

More information

3-Valued Abstraction-Refinement

3-Valued Abstraction-Refinement 3-Valued Abstraction-Refinement Sharon Shoham Academic College of Tel-Aviv Yaffo 1 Model Checking An efficient procedure that receives: A finite-state model describing a system A temporal logic formula

More information

Symbolic Reachability Analysis of Lazy Linear Hybrid Automata. Susmit Jha, Bryan Brady and Sanjit A. Seshia

Symbolic Reachability Analysis of Lazy Linear Hybrid Automata. Susmit Jha, Bryan Brady and Sanjit A. Seshia Symbolic Reachability Analysis of Lazy Linear Hybrid Automata Susmit Jha, Bryan Brady and Sanjit A. Seshia Traditional Hybrid Automata Traditional Hybrid Automata do not model delay and finite precision

More information

Lecture 6: Reachability Analysis of Timed and Hybrid Automata

Lecture 6: Reachability Analysis of Timed and Hybrid Automata University of Illinois at Urbana-Champaign Lecture 6: Reachability Analysis of Timed and Hybrid Automata Sayan Mitra Special Classes of Hybrid Automata Timed Automata ß Rectangular Initialized HA Rectangular

More information

MODEL CHECKING. Arie Gurfinkel

MODEL CHECKING. Arie Gurfinkel 1 MODEL CHECKING Arie Gurfinkel 2 Overview Kripke structures as models of computation CTL, LTL and property patterns CTL model-checking and counterexample generation State of the Art Model-Checkers 3 SW/HW

More information

Layered Composition for Timed Automata

Layered Composition for Timed Automata Layered Composition for Timed Automata Ernst-Rüdiger Olderog and Mani Swaminathan Department of Computing Science University of Oldenburg, Germany {olderog, mani.swaminathan}@informatik.uni-oldenburg.de

More information

Synchronized Recursive Timed Automata

Synchronized Recursive Timed Automata Synchronized Recursive Timed Automata Yuya Uezato 1 and Yasuhiko Minamide 2 1 University of Tsukuba uezato@score.cs.tsukuba.ac.jp 2 Tokyo Institute of Technology minamide@is.titech.ac.jp Abstract. We present

More information

The State Explosion Problem

The State Explosion Problem The State Explosion Problem Martin Kot August 16, 2003 1 Introduction One from main approaches to checking correctness of a concurrent system are state space methods. They are suitable for automatic analysis

More information

Verification of Polynomial Interrupt Timed Automata

Verification of Polynomial Interrupt Timed Automata Verification of Polynomial Interrupt Timed Automata Béatrice Bérard 1, Serge Haddad 2, Claudine Picaronny 2, Mohab Safey El Din 1, Mathieu Sassolas 3 1 Université P. & M. Curie, LIP6 2 ENS Cachan, LSV

More information

Clock Matrix Diagrams

Clock Matrix Diagrams Clock Matrix Diagrams U N I V E R S I T A S S A R A V I E N I S S Bachelor s Thesis Daniel Fass daniel@react.cs.uni-sb.de Reactive Systems Group Department of Computer Science Universität des Saarlandes

More information

Binary Decision Diagrams

Binary Decision Diagrams Binary Decision Diagrams Literature Some pointers: H.R. Andersen, An Introduction to Binary Decision Diagrams, Lecture notes, Department of Information Technology, IT University of Copenhagen Tools: URL:

More information

Discrete abstractions of hybrid systems for verification

Discrete abstractions of hybrid systems for verification Discrete abstractions of hybrid systems for verification George J. Pappas Departments of ESE and CIS University of Pennsylvania pappasg@ee.upenn.edu http://www.seas.upenn.edu/~pappasg DISC Summer School

More information

Controller Synthesis for MTL Specifications

Controller Synthesis for MTL Specifications Controller Synthesis for MTL Specifications Patricia Bouyer, Laura Bozzelli, and Fabrice Chevalier LSV, CNRS & ENS Cachan, France {bouyer,bozzelli,chevalie}@lsv.ens-cachan.fr Abstract. We consider the

More information

A New Numerical Abstract Domain Based on Difference-Bound Matrices

A New Numerical Abstract Domain Based on Difference-Bound Matrices A New Numerical Abstract Domain Based on Difference-Bound Matrices Antoine Miné École Normale Supérieure de Paris, France, mine@di.ens.fr, http://www.di.ens.fr/~mine Abstract. This paper presents a new

More information

SFM-11:CONNECT Summer School, Bertinoro, June 2011

SFM-11:CONNECT Summer School, Bertinoro, June 2011 SFM-:CONNECT Summer School, Bertinoro, June 20 EU-FP7: CONNECT LSCITS/PSS VERIWARE Part 3 Markov decision processes Overview Lectures and 2: Introduction 2 Discrete-time Markov chains 3 Markov decision

More information

Symmetry Reduction and Compositional Verification of Timed Automata

Symmetry Reduction and Compositional Verification of Timed Automata Symmetry Reduction and Compositional Verification of Timed Automata Hoang Linh Nguyen University of Waterloo Waterloo, Canada Email: nhoangli@uwaterloo.ca Richard Trefler University of Waterloo Waterloo,

More information

Control Synthesis of Discrete Manufacturing Systems using Timed Finite Automata

Control Synthesis of Discrete Manufacturing Systems using Timed Finite Automata Control Synthesis of Discrete Manufacturing Systems using Timed Finite utomata JROSLV FOGEL Institute of Informatics Slovak cademy of Sciences ratislav Dúbravská 9, SLOVK REPULIC bstract: - n application

More information

The efficiency of identifying timed automata and the power of clocks

The efficiency of identifying timed automata and the power of clocks The efficiency of identifying timed automata and the power of clocks Sicco Verwer a,b,1,, Mathijs de Weerdt b, Cees Witteveen b a Eindhoven University of Technology, Department of Mathematics and Computer

More information

Lecture 11: Timed Automata

Lecture 11: Timed Automata Real-Time Systems Lecture 11: Timed Automata 2014-07-01 11 2014-07-01 main Dr. Bernd Westphal Albert-Ludwigs-Universität Freiburg, Germany Contents & Goals Last Lecture: DC (un)decidability This Lecture:

More information

Synthesising Certificates in Networks of Timed Automata

Synthesising Certificates in Networks of Timed Automata Synthesising Certificates in Networks of Timed Automata Bernd Finkbeiner Hans-Jörg Peter Saarland University {finkbeiner peter}@cs.uni-saarland.de Sven Schewe University of Liverpool sven.schewe@liverpool.ac.uk

More information

Model checking the basic modalities of CTL with Description Logic

Model checking the basic modalities of CTL with Description Logic Model checking the basic modalities of CTL with Description Logic Shoham Ben-David Richard Trefler Grant Weddell David R. Cheriton School of Computer Science University of Waterloo Abstract. Model checking

More information

Real-Time Systems. Lecture 10: Timed Automata Dr. Bernd Westphal. Albert-Ludwigs-Universität Freiburg, Germany main

Real-Time Systems. Lecture 10: Timed Automata Dr. Bernd Westphal. Albert-Ludwigs-Universität Freiburg, Germany main Real-Time Systems Lecture 10: Timed Automata 2013-06-04 10 2013-06-04 main Dr. Bernd Westphal Albert-Ludwigs-Universität Freiburg, Germany Contents & Goals Last Lecture: PLC, PLC automata This Lecture:

More information

As Soon As Probable. O. Maler, J.-F. Kempf, M. Bozga. March 15, VERIMAG Grenoble, France

As Soon As Probable. O. Maler, J.-F. Kempf, M. Bozga. March 15, VERIMAG Grenoble, France As Soon As Probable O. Maler, J.-F. Kempf, M. Bozga VERIMAG Grenoble, France March 15, 2013 O. Maler, J.-F. Kempf, M. Bozga (VERIMAG Grenoble, France) As Soon As Probable March 15, 2013 1 / 42 Executive

More information

Symbolic Model Checking with ROBDDs

Symbolic Model Checking with ROBDDs Symbolic Model Checking with ROBDDs Lecture #13 of Advanced Model Checking Joost-Pieter Katoen Lehrstuhl 2: Software Modeling & Verification E-mail: katoen@cs.rwth-aachen.de December 14, 2016 c JPK Symbolic

More information

QEES lecture 5. Timed Automata. Welcome. Marielle Stoelinga Formal Methods & Tools

QEES lecture 5. Timed Automata. Welcome. Marielle Stoelinga Formal Methods & Tools QEES lecture 5 Timed Automata Welcome Marielle Stoelinga Formal Methods & Tools Agenda 1. Solution to exercises 2. Timed Automata @ QEES content of 4 lectures 3. Formal definitions 4. Work on Assignment:

More information

ESE601: Hybrid Systems. Introduction to verification

ESE601: Hybrid Systems. Introduction to verification ESE601: Hybrid Systems Introduction to verification Spring 2006 Suggested reading material Papers (R14) - (R16) on the website. The book Model checking by Clarke, Grumberg and Peled. What is verification?

More information

Assertions and Measurements for Mixed-Signal Simulation

Assertions and Measurements for Mixed-Signal Simulation Assertions and Measurements for Mixed-Signal Simulation PhD Thesis Thomas Ferrère VERIMAG, University of Grenoble (directeur: Oded Maler) Mentor Graphics Corporation (co-encadrant: Ernst Christen) October

More information

Model Checking with CTL. Presented by Jason Simas

Model Checking with CTL. Presented by Jason Simas Model Checking with CTL Presented by Jason Simas Model Checking with CTL Based Upon: Logic in Computer Science. Huth and Ryan. 2000. (148-215) Model Checking. Clarke, Grumberg and Peled. 1999. (1-26) Content

More information

Introduction to Temporal Logic. The purpose of temporal logics is to specify properties of dynamic systems. These can be either

Introduction to Temporal Logic. The purpose of temporal logics is to specify properties of dynamic systems. These can be either Introduction to Temporal Logic The purpose of temporal logics is to specify properties of dynamic systems. These can be either Desired properites. Often liveness properties like In every infinite run action

More information

Laboratoire Spécification & Vérification. Language Preservation Problems in Parametric Timed Automata. Étienne André and Nicolas Markey

Laboratoire Spécification & Vérification. Language Preservation Problems in Parametric Timed Automata. Étienne André and Nicolas Markey Language Preservation Problems in Parametric Timed Automata Étienne André and Nicolas Markey June 2015 Research report LSV-15-05 (Version 1) Laboratoire Spécification & Vérification École Normale Supérieure

More information

On Model Checking for Visibly Pushdown Automata

On Model Checking for Visibly Pushdown Automata Japan Institute of Advanced Industrial Science and Technology Research Center for Specification and Verification LATA 2012 On Model Checking for Visibly Pushdown Automata Nguyen Van Tang and Hitoshi Ohsaki

More information

Automated Verification of a Parametric Real-Time Program: The ABR Conformance Protocol

Automated Verification of a Parametric Real-Time Program: The ABR Conformance Protocol Automated Verification of a Parametric Real-Time Program: The ABR Conformance Protocol Béatrice Bérard and Laurent Fribourg LSV Ecole Normale Supérieure de Cachan & CNRS 61 av. Pdt. Wilson - 94235 Cachan

More information

Overview. overview / 357

Overview. overview / 357 Overview overview6.1 Introduction Modelling parallel systems Linear Time Properties Regular Properties Linear Temporal Logic (LTL) Computation Tree Logic syntax and semantics of CTL expressiveness of CTL

More information

Experiments in the use of tau-simulations for the components-verification of real-time systems

Experiments in the use of tau-simulations for the components-verification of real-time systems Experiments in the use of tau-simulations for the components-verification of real-time systems Françoise Bellegarde, Jacques Julliand, Hassan Mountassir, Emilie Oudot To cite this version: Françoise Bellegarde,

More information

Guest lecturer: Prof. Mark Reynolds, The University of Western Australia

Guest lecturer: Prof. Mark Reynolds, The University of Western Australia Università degli studi di Udine Corso per il dottorato di ricerca: Temporal Logics: Satisfiability Checking, Model Checking, and Synthesis January 2017 Lecture 01, Part 02: Temporal Logics Guest lecturer:

More information

Formal Verification of Mobile Network Protocols

Formal Verification of Mobile Network Protocols Dipartimento di Informatica, Università di Pisa, Italy milazzo@di.unipi.it Pisa April 26, 2005 Introduction Modelling Systems Specifications Examples Algorithms Introduction Design validation ensuring

More information

An Introduction to Timed Automata

An Introduction to Timed Automata An Introduction to Timed Automata Patricia Bouer LSV CNRS & ENS de Cachan 6, avenue du Président Wilson 943 Cachan France email: bouer@lsv.ens-cachan.fr Introduction Explicit timing constraints are naturall

More information

A Boolean Approach to Unbounded, Fully Symbolic Model Checking of Timed Automata

A Boolean Approach to Unbounded, Fully Symbolic Model Checking of Timed Automata A Boolean Approach to Unbounded, Fully Symbolic Model Checking of Timed Automata Sanjit A. Seshia Randal E. Bryant March 2003 CMU-CS-03-117 School of Computer Science Carnegie Mellon University Pittsburgh,

More information

Formal Verification Techniques. Riccardo Sisto, Politecnico di Torino

Formal Verification Techniques. Riccardo Sisto, Politecnico di Torino Formal Verification Techniques Riccardo Sisto, Politecnico di Torino State exploration State Exploration and Theorem Proving Exhaustive exploration => result is certain (correctness or noncorrectness proof)

More information

Robust Reachability in Timed Automata: A Game-based Approach

Robust Reachability in Timed Automata: A Game-based Approach Robust Reachability in Timed Automata: A Game-based Approach Patricia Bouyer, Nicolas Markey, and Ocan Sankur LSV, CNRS & ENS Cachan, France. {bouyer,markey,sankur}@lsv.ens-cachan.fr Abstract. Reachability

More information

Hourglass Automata. Yuki Osada, Tim French, Mark Reynolds, and Harry Smallbone

Hourglass Automata. Yuki Osada, Tim French, Mark Reynolds, and Harry Smallbone Hourglass Automata Yuki Osada, Tim French, Mark Reynolds, and Harry Smallbone The University of Western Australia. yuki.osada@research.uwa.edu.au, {tim.french,mark.reynolds}@uwa.edu.au, 21306592@student.uwa.edu.au

More information

Timed Automata with Observers under Energy Constraints

Timed Automata with Observers under Energy Constraints Timed Automata with Observers under Energy Constraints Patricia Bouyer-Decitre Uli Fahrenberg Kim G. Larsen Nicolas Markey LSV, CNRS & ENS Cachan, France Aalborg Universitet, Danmark /9 Introduction The

More information

New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations

New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations (Extended Abstract) Gaoyan Xie, Cheng Li and Zhe Dang School of Electrical Engineering and

More information

Sanjit A. Seshia EECS, UC Berkeley

Sanjit A. Seshia EECS, UC Berkeley EECS 219C: Computer-Aided Verification Explicit-State Model Checking: Additional Material Sanjit A. Seshia EECS, UC Berkeley Acknowledgments: G. Holzmann Checking if M satisfies : Steps 1. Compute Buchi

More information

Techniques to solve computationally hard problems in automata theory

Techniques to solve computationally hard problems in automata theory Techniques to solve computationally hard problems in automata theory Richard Mayr University of Edinburgh, UK IST Vienna, 4. Nov. 2014 Resources: www.languageinclusion.org Mayr (Edinburgh) Hard Problems

More information

MODEL-CHECKING IN DENSE REAL-TIME SHANT HARUTUNIAN

MODEL-CHECKING IN DENSE REAL-TIME SHANT HARUTUNIAN MODEL-CHECKING IN DENSE REAL-TIME SHANT HARUTUNIAN 1. Introduction These slides are for a talk based on the paper Model-Checking in Dense Real- Time, by Rajeev Alur, Costas Courcoubetis, and David Dill.

More information

Chapter 4: Computation tree logic

Chapter 4: Computation tree logic INFOF412 Formal verification of computer systems Chapter 4: Computation tree logic Mickael Randour Formal Methods and Verification group Computer Science Department, ULB March 2017 1 CTL: a specification

More information

Patricia Bouyer-Decitre. Nicolas Markey

Patricia Bouyer-Decitre. Nicolas Markey Real-Time Model Checking Patricia Bouyer-Decitre Kim G. Larsen Nicolas Markey Timed Automata.. and Prices and Games Patricia Bouyer-Decitre Kim G. Larsen Nicolas Markey Model Checking System Description

More information

Double Header. Model Checking. Model Checking. Overarching Plan. Take-Home Message. Spoiler Space. Topic: (Generic) Model Checking

Double Header. Model Checking. Model Checking. Overarching Plan. Take-Home Message. Spoiler Space. Topic: (Generic) Model Checking Double Header Model Checking #1 Two Lectures Model Checking SoftwareModel Checking SLAM and BLAST Flying Boxes It is traditional to describe this stuff (especially SLAM and BLAST) with high-gloss animation

More information

Verification and Performance Evaluation of Timed Game Strategies

Verification and Performance Evaluation of Timed Game Strategies Verification and Performance Evaluation of Timed Game Strategies Alexandre David 1, Huixing Fang 2, Kim G. Larsen 1, and Zhengkui Zhang 1 1 Department of Computer Science, Aalborg University, Denmark {adavid,kgl,zhzhang}@cs.aau.dk

More information

Combining Symbolic Representations for Solving Timed Games

Combining Symbolic Representations for Solving Timed Games Combining Symbolic Representations for Solving Timed Games Rüdiger Ehlers 1, Robert Mattmüller 2, and Hans-Jörg Peter 1 1 Reactive Systems Group Saarland University, Germany {ehlers peter}@cs.uni-saarland.de

More information