Investigation of manufacturing variations of planar InP/InGaAs avalanche photodiodes for optical receivers

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1 Microelectronics Journal 35 (2004) Investigation of manufacturing variations of planar InP/InGaAs avalanche photodiodes for optical receivers Bongyong Lee a, Hongil Yoon a, Kyung Sook Hyun b, Yong Hwan Kwon c, Ilgu Yun a, * a Semiconductor Engineering Laboratory, Department of Electrical and Electronic Engineering, Centre for Information Technology of Yonsei University, Yonsei University, 134, Shinchon-Dong, Seodaemun-Ku, Seoul , South Korea b School of Electronics and Information Engineering, Sejong University, Seoul, South Korea c Telecommunication Basic Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon , South Korea Received 20 March 2004; revised 16 April 2004; accepted 26 April 2004 Available online 8 June 2004 Abstract Planar InP/InGaAs avalanche photodiodes are widely used for high-speed optical receivers in optical fiber communication systems. Even though these avalanche photodiodes offer the excellent characteristics in high-speed operation, the performance metrics are affected by manufacturing parameter variations considerably. In this paper, the effects of manufacturing variations on the device performance are investigated. In order to build a photodiode model, the test structures were fabricated and the measured current voltage characteristics were compared with the simulated data to verify the model. After the model verification, the variations of the breakdown voltage and punchthrough voltage according to the different manufacturing parameters such as multiplication layer width and charge sheet density are examined. Based on the results, the manufacturability of the avalanche photodiodes can be improved by analyzing the manufacturing variations. q 2004 Elsevier Ltd. All rights reserved. PACS: T; D Keywords: Avalanche photodiode; Modeling; Manufacturing variation; Optical receiver 1. Introduction The InP/InGaAs planar avalanche photodiode (APD) is the one of key components in optical fiber communication systems. Many researches have been focused on the performance improvement of APDs via bandgap engineering and optimization of device structures using III V compound semiconductors. Various APD structures have been developed such as InP/InGaAs separated absorption, grading, charge, and multiplication (SAGCM) structure [1], d-doped SAGM structure [2], and InAlAs/InGaAs superlattice structure [3], SACM structure adopting quantum-dot resonant-cavity [4], and floating guard ring (FGR) structure [5]. Even if these structures have offered large gainbandwidth product and high performances at 1.3 and 1.55 mm wavelength, the performance metrics are severely * Corresponding author. Tel.: þ ; fax: þ address: iyun@yonsei.ac.kr (I. Yun). influenced by the manufacturing parameter variations. Hyun et al. studied about the breakdown characteristics of InP/ InGaAs APD with p i n multiplication layer, and Park et al. calculated the effective thickness of a multiplication layer width in APD [6,7]. Yuan et al. [8] reported on impact ionization characteristics of III V semiconductors for a wide range of multiplication region thickness. In our works, the effects of manufacturing parameter variations on the device performance are examined. The test structures of planar InP/InGaAs APDs were fabricated and current voltage ði VÞ characteristics were measured, which were compared with the simulated data to build the model. Based on the modeling results, the variations of the manufacturing parameters such as multiplication layer width (MLW) and charge sheet density (C p ) on the performance metrics such as the breakdown voltage (V br ) and the punch-through voltage are investigated using the model parameters /$ - see front matter q 2004 Elsevier Ltd. All rights reserved. doi: /j.mejo

2 636 B. Lee et al. / Microelectronics Journal 35 (2004) Test structure description The schematic diagram of planar InP/InGaAs APD test structure is shown in Fig. 1. The epitaxial structure was grown by the metal organic chemical vapor deposition (MOCVD) growth technique at the Electronics and Telecommunications Research Institute. The three InGaAsP layers are inserted to avoid hole accumulation in heterointerface between the InP charge plate layer and the InGaAs absorption layer. The thickness and doping concentrations of InP/InGaAs epitaxial layers are summarized in Table 1. Fig. 2 shows the cross-sectional view of scanning electron microscopy images for grown epitaxial layer test structures with different InGaAs absorption layer thickness. The InGaAs absorption layer thicknesses of the test structures 1 and 2 are 1 and 0.8 mm, respectively. After the epitaxial growth of the test structure, the p n junction is formed using the recess etching in the active region and the single diffusion process. P-side electrode and n-side electrode were made by metallization process using Ti Pt Au alloy and Cr/Au alloy, respectively. It is found that InP cap layer is shown on top of the epitaxial layer, which protects p þ - InGaAs layer during cooling-down process in MOCVD growth. At later process, the InGaAs top layer is etched out using the selective etchant. Table 1 Structural parameters of APD test structures Layer Thickness (mm) Doping or charge density p-inp cm 23 n 2 -InP (multiplication) cm 23 n-inp (charge plate) cm 22 n 2 -InGaAsP (lg ¼ 1:1 mm) cm 23 n 2 -InGaAsP (lg ¼ 1:3 mm) cm 23 n 2 -InGaAsP (lg ¼ 1:5 mm) cm 23 n-ingaas (absorption) 0.8 (test structure 1) cm (test structure 2) n þ -InP substrate cm 23 semiconductor and band structure depending on positions. This module is widely adopted to simulate hetero-junction devices. The luminous module enables simulation for optical devices. In addition, the Fermi Dirac model was used for carrier statistics model and the Selberherr model was used for impact ionization [11]. For the impact ionization process simulation, the coefficients of impact ionization process were extracted based on the literature by Cook et al. [12]. During the simulation, Newton s numerical analysis method was used for deriving solutions of Poisson s and continuity equations. 3. Modeling scheme The objective of APD simulation was to use simulated data as a supplemental aid to experimental data for understanding the effect of manufacturing variations on APD performances [9]. The simulation was performed using Silvaco simulation software packages [10]. Test structure was constructed and analyzed by the ATLAS device simulator with structural information. Two modules and two models were used in APD simulation. The Blaze module enables 2D simulation of III V, II VI compound 4. Results and discussion 4.1. APD modeling Fig. 3 shows the typical measured data of dark and light currents as a function of reverse bias for both APD test structures using HP 4145B parameter analyzer. Even though the test devices are fabricated using the same epitaxial structure and manufacturing processes, the variation of I V characteristics is observed. The punch-through voltage (V ph ), which is defined as the voltage when the InGaAs absorption layer is fully depleted, varies from 13.4 to 15.4 V for test structure 1 and from 13.4 to 16.2 V for test Fig. 1. Schematic design of planar InP/InGaAs APD structure. Fig. 2. Cross-sectional scanning electron microscopy (SEM) images of APDs: (a) test structure 1 and (b) test structure 2.

3 B. Lee et al. / Microelectronics Journal 35 (2004) Fig. 3. Measured dark and light I V characteristics for (a) test structure 1 and (b) test structure 2. Fig. 4. Measured and simulated results of I V characteristics for (a) test structure 1 and (b) test structure 2. structure 2. In addition, the V br, which is defined as the voltage where the dark current exceeds 100 ma, varies from 34.3 to 36.1 V for test structure 1 and from 35.2 to 38.4 V for test structure 2. It can be explained that these variation can be originated from the diffusion depth variation (same as MLW variation) and the charge sheet density variation. It is also observed that the dark current have some noise currents induced by measurement system. However, all the measured dark currents show below several na s at operating voltage, which are low enough to operate as a photodetector. In order to investigate the manufacturing parameter variation, the mean value of the variation for each test structure is considered as a reference model. In order to build the APD model, the optimization of structural parameters is performed using the measured I V data and the simulated data. Fig. 4 shows the modeling results of I V characteristics for both test structures. When the APD is in Mode I, it operates as a hybrid region of p i n photodiode and APD. In this region, the device performance corresponds to a p i n photodiode with a larger depletion region. Mode II corresponds to the classic behavior associated with APD [13]. In order to understand the distinctions of each mode, it is useful to examine the APD behavior as the bias is increased. While the electric filed intensity grows with the increased bias, n 2 -InP multiplication layer is depleted rapidly, and then n 2 -InP charge plate layer is also depleted. If the stronger bias is applied, the depletion region starts to extend into the n 2 -InGaAs absorption layer until the layer is fully depleted. When the electric field in the multiplication region is reached the critical electric field, the avalanche process starts to occur, which generates excess carriers considerably. They are added to the primary device current flow so that the total current level is raised exponentially. Based on the results in Fig. 4, it is shown that the modeling results are matched well with the measured data in Mode II indicating that the punch-through voltage and the V br are accurately modeled. However, the difference is observed between the measured data and the simulated data in Mode I. It is due to the defect level of the device causing this difference in Mode I, which is not considered in the simulation. After the model verification, the effects of manufacturing parameter variation on the device characteristics were investigated. The manufacturing parameters such as absorption layer thickness, charge sheet density, and multiplication layer width were crucial in APD operation and these parameters

4 638 B. Lee et al. / Microelectronics Journal 35 (2004) Table 2 Summary of manufacturing parameters Manufacturing parameter Variation range Unit Absorption layer thickness 0.6, 1.0 mm Multiplication layer width mm Charge sheet density cm 22 require to be controlled precisely. Therefore, these parameter variations are examined by observing the V ph and the V br characteristics. The summary of manufacturing parameters are shown in Table 2. Fig. 5 presents the influences of absorption layer thickness variation. There is a trade-off between quantum efficiency and device operation speed for the layer thickness variation, since the quantum efficiency is inversely proportional to the device operation speed. It is observed that the V br is increased with the layer thickness increases. It is due to the increase of carrier passing time through the layer. The increased carrier passing time requires the larger bias to attain enough electric field intensity to occur avalanche multiplication process so that it results in the increase of V br. On the other hand, V ph holds almost consistent since the absorption layer is lightly doped and the depletion width increase with increasing the reverse bias is almost negligible within the sub-micron range. The results of the charge sheet density variations are presented in Fig. 6. It is observed that the V ph is increased with the increase of charge sheet density, whereas the V br is decreased. If the charge sheet density is increased, the more bias is needed to deplete into the InGaAs absorption layer. However, in contrast with the V ph, the V br is decreased as the charge sheet density is increased since the built-in potential is proportional to the charge sheet density. As the built-in potential increased, it provides larger electric field, which can occur avalanche process at the smaller bias resulting in the lower V br. Fig. 6. The punch-through and breakdown voltage characteristics as a function of charge sheet density. The results of multiplication layer width variations are shown in Fig. 7. The V br and V ph are increased with the increase of multiplication layer width. It is due to the electric field is dependent on the structure as well as bias voltage. As the layer thickness is increased, maximum electric field intensity (E m ) and hetero-interface electric field intensity ðe h Þ are decreased in Fig. 8. In order to obtain enough high electric field intensity occurring the avalanche process, the more bias is required. As a result, the punchthrough and V br are increased Effect of manufacturing variation Section 4.1 examined about the effect of single manufacturing parameter variations on APD performances. In this section the effect of manufacturing variations on the APD performances for two differently grown test structures were investigated. The two structures have fixed InGaAs absorption layer thickness in Fig. 2. Hence, effects of charge sheet density variation and the multiplication layer width variation on APD performances were focused. Fig. 5. The punch-through and breakdown voltage characteristics as a function of InGaAs absorption layer thickness. Fig. 7. The punch-through and breakdown voltage characteristics as a function of multiplication layer width.

5 B. Lee et al. / Microelectronics Journal 35 (2004) Table 4a Summary of APD simulation results: test structure 1 Run Measured data Modeled data (V) V ph (V) V br (V) V ph (V) V br (V) Table 4b Summary of APD simulation results: test structure 2 Fig. 8. The electric field intensity versus the multiplication layer width variation. Based on the modeling results in Section 4.1, the effect of manufacturing parameter variation can be extracted from the simulations of the following datasets summarized in Table 3 since the datasets contains the whole variation ranges of the punch-through and V br. Based on the design matrix shown in Table 3, the modeling results of the punchthrough and V br with respect to the designed datasets are summarized in Table 4. It is observed that the modeled data match the measured data pretty well. Using the modeling results, the variations of charge sheet density and the multiplication layer width is shown in Fig. 9. For the epitaxial layer growth, the initial design values of charge sheet density and multiplication layer width are optimized to be cm 22 and 0.3 mm, respectively. It is observed that the charge sheet density and multiplication layer width shows variations compared with the desired design value. For the test structure 1, the charge sheet density varies from to cm 22 with the mean value of about cm 22 and the multiplication layer width varies from 0.21 to 0.26 mm with the mean value of about 0.24 mm. For the test structure 2, the charge sheet density varies from to cm 22 with the mean value of about cm 22 and the multiplication layer width varies from 0.28 to 0.35 mm with the mean value of about 0.32 mm. The variation of charge sheet density for each structure is due to the wafer-to-wafer variation, which is affected by the different process conditions involved during the epitaxial layer growth. The variation of the multiplication layer width Run Measured data Modeled data (V) V ph (V) V br (V) V ph (V) V br (V) is affected by either the doping vaiation of undoped InP layer prepared for the diffusion or the diffusion process variation, which ultimately determined the multiplication layer width. It is also observed that the variation of manufacturing parameters is slightly increased as the Table 3 Design matrix of APD simulation Run Test structure 1 Test structure 2 V ph (V) V br (V) V ph (V) V br (V) Fig. 9. The variation results of charge sheet density and multiplication layer width for (a) test structure1 and (b) test structure 2.

6 640 B. Lee et al. / Microelectronics Journal 35 (2004) InGaAs absorption layer thickness is decreased. Since the desired InGaAs layer thickness is decreased for the highspeed operation, it can be concluded that the precise control of manufacturing variation is crucial for APD performance. 5. Conclusion The modeling and effects of manufacturing parameter variations on planar InP/InGaAs APD have been investigated. The measured I V data were used in comparison with the simulated data to verify the model. After the model validation, the effects of the manufacturing parameter variations on the APD performance were characterized by observing the breakdown voltage and punch-through voltage. It is observed that the variations of the manufacturing parameters such as the absorption layer thickness, charge sheet density and multiplication layer width are severely impacted on the characteristics of APDs. It can be concluded that the APD performance is severely impacted by the manufacturing variations and these variations are required to be precisely controlled. Furthermore, this approach could provide device designers with the ability to understand the manufacturability of various design options and enables process engineers to determine the effects of process modifications. This will potentially improve the parametric yield and manufacturability prior to high-volume manufacturing. Acknowledgements This work was supported by the Brain Korea 21 Project in References [1] L.E. Tarof, D.G. Knight, K.E. Fox, C.J. Miner, N. Puetz, H.B. Kim, Planar InP/InGaAs avalanche photodetectors with partial charge sheet in device periphery, Appl. Phys. Lett. 57 (7) (1990) [2] R. Kuchibhotla, J.C. Campbell, C. Tsai, W.T. Tsang, F.S. Choa, Delta-doped SAGM avalanche photodiodes, IEEE Trans. Electron Devices 38 (12) (1991) [3] I. Watanabe, S. Sugou, H. Ishikawa, T. Anan, K. Makita, M. Tsuji, K. Taguchi, High-speed and low-dark-current flip-chip InAlAs/InAl- GaAs quaternary well superlattice APDs with 120 GHz gainbandwidth product, IEEE Photonics Technol. Lett. 5 (6) (1993) [4] P. Yuan, O. Baklenov, H. Nie, A.L. Holmes, B.G. Streetman, Highspeed quantum-dot resonant-cavity SACM avalanche photodiodes operating at 1.06 mm, 57th Annual Device Research Conference Digest, 1999, pp [5] Y. Liu, S.R. Forrest, J. Hladky, M.J. Lange, G.H. Olsen, D.E. Ackley, A planar InP/InGaAs avalanche photodiode with floating guard ring and double diffused junction, IEEE J. Lightwave Technol. 10 (2) (1992) [6] K.-S. Hyun, C.-Y. Park, Breakdown characteristics in InP/InGaAs avalanche photodiode with p i n multiplication layer structure, J. Appl. Phys. 81 (2) (1997) [7] C.-Y. Park, K.-S. Hyun, S.-G. Kang, H.-M. Kim, Effect of multiplication layer width on breakdown voltage in InP/InGaAs avalanche photodiode, J. Appl. Phys. 67 (25) (1995) [8] P. Yuan, C.C. Hansing, K.A. Anselm, C.V. Lenox, H. Nie, A.L. Holmes Jr., B.G. Streetman, J.C. Campbell, Impact ionization characteristics of III V semiconductors for an wide range of multiplication region thickness, IEEE J. Quantum Electron. 36 (2) (2000) [9] I. Yun, G.S. May, Parametric manufacturing yield modeling of GaAs/ AlGaAs multiple quantum well avalanche photodiodes, IEEE Trans. Semicond. Manufact. 12 (2) (1999) [10] ATLAS II User s Manual, Silvaco International, [11] S. Selberherr, Analysis and Simulation of Semiconductor Devices, Springer, New York, [12] L.W. Cook, G.E. Bullman, G.E. Stillman, Electron and hole impact ionization coefficients in InP determined by photomultiplication measurements, Appl. Phys. Lett. 40 (7) (1987) [13] J.N. Haralson II, K.F. Brennan, Novel edge suppression technique for planar avalanche photodiodes, IEEE J. Quantum Electron. 35 (12) (1999)