EE247 Lecture 2 AC Converters Pipelined ACs EECS 247 Lecture 2: ata Converters 24 H.K. Page Pipelined A/ Converters Ideal operation Errors and correction Redundancy igital calibration Implementation Practical circuits Stage scaling EECS 247 Lecture 2: ata Converters 24 H.K. Page 2
Block iagram Stage B Stage 2 B 2 V res2 Stage k B k MSB......LSB Align and Combine ata igital output (B B 2... B k ) Idea: Cascade several low resolution stages to obtain high overall resolution Each stage performs coarse A/ conversion and computes its quantization error, or "residue" EECS 247 Lecture 2: ata Converters 24 H.K. Page 3 Characteristics Number of components (stages) grows linearly with resolution Pipelining Trading latency for conversion speed Latency may be an issue in e.g. control systems Throughput limited by speed of one stage fi Fast Versatile: 8...6bits,...2MS/s Many analog circuit nonidealities can be corrected digitally EECS 247 Lecture 2: ata Converters 24 H.K. Page 4
Concurrent Stage Operation φ φ 2 acquire convert convert acquire...... Stage B Stage 2 B 2 Stage k B k CLK φ φ 2 Align and Combine ata igital output (B B 2... B k ) Stages operate on the input signal like a shift register New output data every clock cycle, but each stage introduces ½ clock cycle latency EECS 247 Lecture 2: ata Converters 24 H.K. Page 5 ata Alignment φ φ 2 acquire convert convert acquire...... Stage B Stage 2 B 2 Stage k B k CLK φ φ 2 out CLK CLK CLK igital shift register aligns subconversion results in time EECS 247 Lecture 2: ata Converters 24 H.K. Page 6
Latency [Analog evices, A 9226 ata Sheet] EECS 247 Lecture 2: ata Converters 24 H.K. Page 7 Pipelined AC Analysis Ignore timing and use simple static model Stage B Stage 2 B 2 V res2 Stage k B k out Let's first look at "twostage pipeline" E.g.: Two cascaded 2bit ACs to get 4 bits of total resolution EECS 247 Lecture 2: ata Converters 24 H.K. Page 8
Two Stage Example 2bit AC out = ε q 2bit AC Using only one AC: output contains large quantization error "Missing voltage" or "residue" (ε q ) Idea: Use second AC to quantize and add ε q??? ε q [LSB] out.5.5 2 3 2 3 AC Input Voltage [LSB] EECS 247 Lecture 2: ata Converters 24 H.K. Page 9 Two Stage Example 2bit AC Coarse 2bit AC 2bit AC ε q Fine ε q ε q2 out = ε q ε q ε q2 Use AC to compute missing voltage Add quantized representation of missing voltage Why does this help? How about ε q2? EECS 247 Lecture 2: ata Converters 24 H.K. Page
Two Stage Example ε q /2 2 2 Second AC Fine First AC Coarse Fine AC is reused 2 2 times Fine AC's full scale range needs to span only LSB of coarse quantizer Vref 2 Vref ε q2 = = 2 2 2 2 2 2 EECS 247 Lecture 2: ata Converters 24 H.K. Page Two Stage Pipelined AC Transfer Function out Coarse (MSB) Fine (LSB) EECS 247 Lecture 2: ata Converters 24 H.K. Page 2
Two Stage (22) Pipelined AC EECS 247 Lecture 2: ata Converters 24 H.K. Page 3 Cascading More Stages /2 B /2 (BB2) /2 (BB2B3) B bits B 2 bits B 3 bits AC AC AC LSB of last stage becomes very small Impractical to generate several EECS 247 Lecture 2: ata Converters 24 H.K. Page 4
ain Elements B bits 2 B B 2 bits 2 B2 B 3 bits 2 B3 AC AC AC Practical pipelines use single Precision requirements decrease down the pipe Advantageous for noise, matching (later) EECS 247 Lecture 2: ata Converters 24 H.K. Page 5 Complete Pipeline Stage V res Bbit AC Bbit AC Residue Plot E.g.: B=2 =2 2 =4 V res ε q EECS 247 Lecture 2: ata Converters 24 H.K. Page 6
Errors We cannot build perfect ACs, ACs and gain elements How can we tolerate/correct errors? Let's first look at subac errors Assumptions: Ideal AC, ideal gain elements EECS 247 Lecture 2: ata Converters 24 H.K. Page 7 AC Model,AC ε q V res2 V res(n) 2 n ε q2 ε q(n) 2 (n) n ε qn out / d / d2 / d(n) out ε = q2 2 q( n ) ( n ) qn Vin, AC ε q... n 2 n d d d 2 d ( n ) dj dj j= j= ε ε EECS 247 Lecture 2: ata Converters 24 H.K. Page 8
AC Model If the "Analog" and "igital" gains match exactly, we get: out ε qn = Vin, AC n j j= n BAC Bn = j= log 2 j EECS 247 Lecture 2: ata Converters 24 H.K. Page 9 Observations The aggregate AC resolution is independent of subac resolution Effective stage resolution B j =log 2 ( j ) Conversion error does not (directly) depend on subac errors! Only error term in out contains quantization error of last stage So why do we care about subac errors? o back to two stage example EECS 247 Lecture 2: ata Converters 24 H.K. Page 2
SubAC Errors,AC B bits AC V res qn out = Vin, AC n j j= out = V in, AC ε ε q2 Vref ε q2 rows outside ½ LSB bounds EECS 247 Lecture 2: ata Converters 24 H.K. Page 2 SubAC Errors Ideal 2Stage Pipelined AC 2Stage Pipelined AC with Coarse AC Comp. Offset EECS 247 Lecture 2: ata Converters 24 H.K. Page 22
st Stage Comparator Offset Problem: exceeds 2 nd pipeline stage overload range V res2 Overall AC Transfer Curve First stage AC Levels: ( = ) Ideal comparator threshold:,, Comparator threshold including offset:,.3, Missing Code! EECS 247 Lecture 2: ata Converters 24 H.K. Page 23 Three Ways to eal with Errors... All involve "subac redundancy" Redundancy in stage that produces errors Choose gain for 2 nd stage < 2 B Higher resolution subac Redundancy in succeeding stage(s) EECS 247 Lecture 2: ata Converters 24 H.K. Page 24
() ain for 2 nd stage < 2 B,AC B bits AC Choose slightly less than 2 B Effective stage resolution becomes noninteger B eff =log 2 ε q2 Ref: A. Karanicolas et. al., JSSC 2/993 EECS 247 Lecture 2: ata Converters 24 H.K. Page 25 Correction Through Redundancy enlarged residuum still within input range of next stage V res2 Overall AC Transfer Curve If =2 only Bit resolution from first stage (3 Bit total) EECS 247 Lecture 2: ata Converters 24 H.K. Page 26
(2) Higher Resolution SubAC,AC B bits AC Keep precise power of two (e.g. keep =4) Add extra decision levels in subac (e.g. add extra bit to st stage) E.g. B =B eff ε q2 Ref: Singer et. al., VSLI996 EECS 247 Lecture 2: ata Converters 24 H.K. Page 27 (3) OverRange Accommodation Through Increase in Following Stage Resolution,AC B bits AC No redundancy in stage with errors Add extra decision levels in succeeding stage ε q2 Ref: Opris et. al., JSSC 2/998 EECS 247 Lecture 2: ata Converters 24 H.K. Page 28
Redundancy The preceding analysis applies to any stage in an an nstage pipeline Can always look at pipeline as a single stage backend AC B bits B 2 bits B 3 bits B 4 bits B bits B 2 B 3 B 4 bits EECS 247 Lecture 2: ata Converters 24 H.K. Page 29 Redundancy In literature, subac redundancy schemes are often called "digital correction" a misnomer! No error correction takes place We can tolerate subac errors as long as: The residues stay "within the box", or Another stage downstream "returns the residue to within the box" before it reaches last quantizer Let's calculate tolerable errors for popular ".5 bits/stage" topology EECS 247 Lecture 2: ata Converters 24 H.K. Page 3
.5 /Stage Example Comparators placed strategically to minimize overhead =2 B eff =log 2 2= /8 B=log 2 (2)=.589... Ref: Lewis et. al., JSSC 3/992 EECS 247 Lecture 2: ata Converters 24 H.K. Page 3 3Stage.5bps Pipelined AC V res3 V res2 Overall Transfer Curve All three stages Comparator with offset Overall transfer curve No missing codes Some NL error Ref: S. Lewis et al, A b 2Msample/s Analogtoigital Converter, J. SolidState Circ., pp. 358, March 992. EECS 247 Lecture 2: ata Converters 24 H.K. Page 32
Amplifier Offset V os AC AC V os V res V os Input referred converter offset usually no problem Equivalent subac offset easily accommodated through redundancy EECS 247 Lecture 2: ata Converters 24 H.K. Page 33 ain Errors,AC ε q V res V res2 V res(n) δ 2 n ε q2 ε q(n) 2 (n) n ε qn out /( d δ) / d2 / d(n) = V ε out in, AC q d δ δ ε ε ε q2 2 qn ( ) ( n ) qn... n 2 n d d2 d( n ) dj dj j= j= EECS 247 Lecture 2: ata Converters 24 H.K. Page 34
Interstage ain Error First Stage Residue (ain Error) Converter Transfer Function (ain Error) Vres out.5.5.5.5 Vin Vin.2 Transfer Function Error(ain Error) out(ideal) out.2.5.5 Vin EECS 247 Lecture 2: ata Converters 24 H.K. Page 35 ain Errors ain error can be compensated in digital domain "igital Calibration" Problem: Need to measure/calibrate digital correction coefficient Example: Calibrate bit first stage Objective: Measure in digital domain EECS 247 Lecture 2: ata Converters 24 H.K. Page 36
AC Model Backend back bit AC bit AC = = V res = ( V V ) in AC V V AC AC ( = ) = ( = ) = V ref / 2 EECS 247 Lecture 2: ata Converters 24 H.K. Page 37 Calibration Step = const. () Backend back () bit AC M U X bit AC V () res () back = = ( Vin Vref / 2) ( V V / 2) in V ref ref store EECS 247 Lecture 2: ata Converters 24 H.K. Page 38
Calibration Step 2 = const. (2) Backend back (2) bit AC M U X bit AC V (2) res (2) back = = ( Vin ) ( V ) in V ref store EECS 247 Lecture 2: ata Converters 24 H.K. Page 39 Calibration Evaluate () back (2) back () back = = (2) back ( V V / 2) in ( V ) in V V ref ref ref = 2 EECS 247 Lecture 2: ata Converters 24 H.K. Page 4
Accuracy Bootstrapping,AC ε q V res2 V res(n) 2 n ε q2 ε q(n) 2 (n) n ε qn out / d / d2 / d(n) ε = q2 2 q( n ) ( n ) qn out Vin, AC ε q... n 2 n d d d 2 d ( n ) dj dj j= j= Highest sensitivity to gain errors in frontend stages ε ε EECS 247 Lecture 2: ata Converters 24 H.K. Page 4 "Accuracy Bootstrapping" irection of Calibration Sufficiently Accurate Stage Stage 2 Stage 3 Stage k B n bits Calibration in opposite direction... Ref: A. N. Karanicolas et al. "A 5b Msample/s digitally selfcalibrated pipeline AC," IEEE J. Of SolidState Circuits, pp. 275, ec. 993 E.. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined ACs," TCAS II, pp. 4353, March 995 L. Singer et al., "A 2 b 65 MSample/s CMOS AC with 82 db SFR at 2 MHz," ISSCC 2, igest of Techn. Papers., pp. 389 EECS 247 Lecture 2: ata Converters 24 H.K. Page 42
AC Errors Backend B bit B bit AC AC out / ε AC back Can be corrected digitally as well Same calibration concept as gain errors EECS 247 Lecture 2: ata Converters 24 H.K. Page 43 AC Calibration Step = const. Backend B bit AC M U X B bit AC ε AC () out / back ε AC () equivalent to offset ignore EECS 247 Lecture 2: ata Converters 24 H.K. Page 44
AC Calibration Step 2...2 B = const. Backend B bit AC M U X B bit AC ε AC (...2 B ) out /...2 B Cal. Register back Stepping through AC codes...2 B yields all incremental correction values EECS 247 Lecture 2: ata Converters 24 H.K. Page 45 Calibration Hardware igital is "free" and easier to build than precise analog circuits... Ref: E.. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined ACs," TCAS II, pp. 4353, March 995 EECS 247 Lecture 2: ata Converters 24 H.K. Page 46
Amplifier Nonlinearity V OS a 3 V 3 V IN 2 3 V RES AC AC εac εac EECS 247 Lecture 2: ata Converters 24 H.K. Page 47 a 3 V X 3 Amplifier Nonlinearity V X 2 3 V RES Backend p 2 B a = 3 3 (2?) 3 (...) B,corr ε( B, p 2 ) 3 ε(b,p2) = p2b 3p2 B 2p2 B... 2 5 3 7 Ref: B. Murmann and B. E. Boser, "A 2b, 75MS/s Pipelined AC using OpenLoop Residue Amplification," ISSCC ig. Techn. Papers, pp. 328329, 23. EECS 247 Lecture 2: ata Converters 24 H.K. Page 48
Measurement Results (a) without calibration INL [LSB] RN= RN= 2 3 4 Code (b) with calibration.5 (b) with calibration INL [LSB] 2 3 4 Code.5 2 3 4 Code EECS 247 Lecture 2: ata Converters 24 H.K. Page 49