Research Article On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing

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1 VLSI Desgn, Artcle ID 46597, 8 pages Research Artcle On the Use of an Algebrac Sgnature Analyzer for Mxed-Sgnal Systems Testng Vadm Geurkov and Lev Krschan Department of Electrcal and Computer Engneerng, Ryerson Unversty, 5 Vctora Street, Toronto, ON, Canada M5B 2K Correspondence should be addressed to Vadm Geurkov; vgeurkov@ee.ryerson.ca Receved May 24; Revsed 7 October 24; Accepted 2 October 24; Publshed 6 November 24 Academc Edtor: M. Renovell Copyrght 24 V. Geurkov and L. Krschan. Ths s an open access artcle dstrbuted under the Creatve Commons Attrbuton Lcense, whch permts unrestrcted use, dstrbuton, and reproducton n any medum, provded the orgnal work s properly cted. We propose an approach to desgn of an algebrac sgnature analyzer that can be used for mxed-sgnal systems testng. The analyzer does not contan carry propagatng crcutry, whch mproves ts performance as well as fault tolerance. The common desgn technque of a sgnature analyzer for mxed-sgnal systems s based on the rules of an arthmetc fnte feld. The applcaton of ths technque to the systems wth an arbtrary radx s a challengng task and the devces desgned possess hgh hardware complexty. The proposed technque s smple and applcable to systems of any sze and radx. The hardware complexty s low. The technque can also be used n arthmetc/algebrac codng and cryptography.. Introducton Sgnature analyss has been wdely used for dgtal and mxedsgnal systems testng [ 2]. Mxed-sgnal systems consst of both dgtal and analog crcuts; however the sgnature analyss method s only applcable to the subset of these systems that have dgtal outputs (such as analog-to-dgtal converters, measurement nstruments, etc.). Sgnature analyss can be employed as an external test soluton or can be embedded nto the system under test. In the bult-n mplementaton, a crcut under test (CUT) of dgtal or mxed-sgnal nature s fed by test stmul, whle the output responses are compacted by a sgnature analyzer (SA), as llustrated n Fgure. The actualsgnaturescomparedaganstthefault-freecrcut s sgnature and a pass/fal decson s made. A sgnature of a fault-free crcut s referred to as a reference sgnature. If the CUT s of a dgtal nature, the SA essentally consttutes a crcut that computes an algebrac remander. The reference sgnature has only one, punctual value, and the decson makng crcut conssts of a smple dgtal comparator. If the CUT s of a mxed-sgnal nature, the SA computes an arthmetc resdue. In ths case, the reference sgnature becomes an nterval valueandthedecsonmakngcrcut uses a wndow comparator. Desgn methods for an algebrac sgnature analyzer have been well developed n error-control codng []. A remander calculatng crcut for an arbtrary base (bnary or nonbnary) can be readly desgned for a dgtal CUT of any sze. In contrast, t s much harder to desgn a resdue calculatng crcut, specfcally for a nonbnary base [4]. Furthermore, due to the presence of carry propagatng crcutry, the mplementaton complexty and error vulnerablty of the resdue calculatng crcut are hgher compared to the remander calculatng crcut. Weproposeanapproachtodesgnofanalgebracsgnature analyzer that can be used for mxed-sgnal systems testng. Due to an algebrac nature, the analyzer does not contan carry propagatng crcutry. Ths helps to mprove ts error mmunty, as well as performance. 2. A Conventonal Sgnature Analyzer An algebrac sgnature analyzer s desgned on the bass of a polynomal dvson crcut, as shown n Fgure 2 [,, 5]. Ths crcut dvdes the ncomng sequence of nonbnary symbols (dgts), a m,...,a,a,treatedasapolynomal: a(y)=a m y m a ya ()

2 2 VLSI Desgn Test stmul Crcut under test Output Sgnature responses analyzer Actual sgnature Reference sgnature Decson makng crcut Pass fal Fgure : Bult-n sgnature analyss of a crcut under test. α j α k Fgure : A symbolc presentaton of a one-stage algebrac sgnature analyzer. α α p p t t p p s t s s a m a a a (j) 2 a (j) a (j) a () 2 a () a () Fgure 2: A t-stage polynomal dvson crcut. Fgure 4: A logc level presentaton of the algebrac -nput sgnature analyzer. by the polynomal The remander p(y)=p t y t p yp, t m. (2) s(y)=s t y t s ys () consttutes a CUT sgnature. Each dgt, a, m,consstsn bts and s consdered to be an element of the feld GF(2 n ). The degree of the polynomal (2), or the number of stages, t,nfgure2, depends on the desred probablty of undetected error n the sequence of ncomng dgts. For long sequences wth ndependent errors, ths probablty s estmated as P nd 2 tn. In practce, n 8 andevenfortheone-stagecrcut, P nd 2 (8) =.9, whch s qute low. Therefore, a multple-nput sgnature analyzer normally contans only one stage. Such an analyzer s presented n Fgure [4], where α s a prmtve element of the feld GF(2 n ),thats,arootofa prmtve polynomal g(x) = g n x n g xg. Each element of the feld can be represented by a power of α. Let α be the ncomng dgt and α j the content of the analyzer. Then, each operatonal cycle of the analyzer s descrbed by the expresson α j α α =α k. (4) Wthout a loss of generalty, we wll consder a -bt sgnature regster (n = ), wth α beng a prmtve element of GF(2 ), n partcular a root of a prmtve polynomal g(x) = x x.then,asymbolcschemeoffgure wll transfer to the logc level crcut of Fgure 4,where α l =a (l) 2 x2 a (l) xa(l), a(l) {, }, 2, l 6. Ths expresson ndcates the relatonshp between the power and vector representatons of a feld element, as reflected n Table (where x=α). If the prelmnary cleared analyzer receves, for example, the followng sequence of -bt output responses from (5) Table : Three representatons for the elements of GF(2 ) generated by g(x) = x x.hereg(α) =. Power Polynomal Vector representaton representaton representaton α l a (l) 2 α2 a (l) α a (l) α a (l) 2 a(l) a(l) α α α α α 2 α 2 α α α α 4 α 2 α α 5 α 2 α α α 6 α 2 α adgtalcut,α 5, α 6, α 4, α 2, α, α, then after the 6th shft ts content wll become ((((( α α 5 )αα 6 )αα 4 )αα 2 )αα )αα =α. (6) The power representaton of the feld element, α, corresponds to the vector representaton,, whch s the actual sgnature of the CUT. In contrast to a dgtal CUT, the output responses of a mxed-sgnal CUT are dstorted even n a fault-free case. Small permssble varatons n the responses cause a sgnfcant devaton of the fnal sgnature. For example, f n the abovesequenceofoutputresponsestheleastsgnfcantbt nthefrstresponsechangesfromto(.e.,thevector changes to, or power α 5 changes to α 4 ), then the actual sgnaturewllchangefromto(orfromα to α 6 n power form). Apparently, the conventonal SA represented n Fgures and 4 cannot be employed for mxed-sgnal crcuts testng. In the known methods, output responses of mxedsgnal crcuts are compacted by a crcut referred to as a modulo adder (or accumulator, or dgtal ntegrator) [4 8]. It should be noted that a modulo adder s a specal case of a resdue computng crcut [4]. A resdue computng crcut s represented n Fgure 5. Herea j s the current content of

3 VLSI Desgn b a j a j a Fgure5:Asymbolcpresentatonofaone-stagearthmetcsgnature analyzer. c 2 a j 2 a 2 the regster, a s the ncomng (arthmetc) symbol, and b s the base of the system. Ths crcut dvdes the ncomng sequence of symbols, a m,...,a,a,treatedasanumber: C c a j a a=a m b m a ba (7) by the modulus c p=p t b t p bp, t m. (8) a j a As n the case wth the algebrac SA, we consder a snglestage devce; that s, t =, p = p < b = 2 n,wheren s thenumberofbtsoccupedbythesymbol.theresdue,s, consttutes a sgnature. An operatonal cycle of the crcut n Fgure 5 can be descrbed by the expresson a j ba =a j (modp). (9) Although the crcuts of Fgures and 5 look smlar, ther mplementaton s qute dfferent. In general case, the desgnng procedure for the arthmetc crcuts s more complcated and ther hardware complexty s greater. As an example, Fgure 6 represents the crcut that computes a modulo 5 resdue of the ncomng sequence of -bt symbols treated as an octal number [4]. Here a s the ncomng octal dgt and C s a combnatonal crcut whch generates the followng next state sgnals: c 2 =a j aj a a a 2 aj (aj a a 2 aj a a 2 ), c =a j 2 a 2 (a a )aj 2 a 2 (aj a aj a ) a j (aj a 2 )aj (a a 2 ), c =a j a (aj a 2 )aj a 2 (aj a a ) a j 2 aj a 2 (aj a a a aj a ). () Each shft of ths crcut mplements the operaton a j 8 a (mod 5). In addton to hgh hardware complexty, the arthmetc compactor contans carry propagatng crcutry (shown n red color n Fgure 6) that delays the operaton and aggravates theeffectofasnglefault. Below, we desgn an algebrac crcut that can be employed for mxed-sgnal data compacton. It does not contan carry propagatng crcutry. Fgure 6: A -nput arthmetc compactor.. A Novel Approach Polynomal () n conjuncton wth the reference sgnature can be consdered as a code word of the code whose mnmal dstance s defned by the g(x).thedstanceheresthehammng dstance. Ths dstance characterzes algebrac errordetectng propertes of the code and s not convenent for arthmetc errors that occur n mxed-sgnal systems. Indeed, a small permssble devaton of the data to be compacted causes the reference sgnature to span the entre space. Under these condtons, the decson makng crcut n Fgure must be able to compare the actual sgnature wth the entre set of possble reference sgnatures. Ths ncreases the analyzer complexty. To decrease the complexty, an arthmetc SA treats the sequence of output responses from a mxed-sgnal crcut as a number (7). In conjuncton wth the reference resdue, ths s consdered as a code word of an arthmetc errorcontrol code. The propertes of ths code depend on the arthmetc mnmal dstance whch n turn depends on the modulus p. The arthmetc resdue calculatng analyzer does not search the entre space, snce the space of arthmetc reference sgnatures s now contguous. To make a decson, t employs a wndow comparator. Ths smplfes the crcutry. However, the hardware complexty of the arthmetc SA can stll be qute hgh, as t was llustrated above. In the rest of ths paper, we wll show how to desgn an algebrac SA, whch generates a contguous space of algebrac reference sgnatures. In order to be contguous, the space of sgnatures must be ordered. A sgnature can be represented n the vector or power forms. We wll use the power exponent as the crteron for orderng the sgnature set. The dstance between two vectors (sgnatures) wll be evaluated as the arthmetc dfference between the correspondng exponents. For example,

4 4 VLSI Desgn α j α j α Fgure 7: A symbolc form of an algebrac SA for a mxed-sgnal CUT... 2 n 2 n 2 MUX the dstance between the sgnatures and wll be 5, because the exponents of powers α 6 and α dffer by 5. We can nterpret these exponents as output responses of a mxedsgnal CUT, snce they possess arthmetc propertes. At the same tme, the correspondng vectors (sgnatures) possess algebrac propertes. Therefore, arthmetc data s mapped nto algebrac data. Fgure 7 represents the crcut whch performs the mappng and computes an algebrac sgnature. The crcut of Fgure 7 can be obtaned from the crcut of Fgure by the followng transform: α j α =(α j α) α =(α j α) α ( α k ) =α j αα jk =α j αα l. () SncethefntefeldGF(2 n ) s closed and errors are ndependent, ths mappng wll not change the probablty of undetected error. The logc level mplementaton of the crcut of Fgure 7 s more complex compared to the crcut of Fgure,butts less complex than that of the crcut of Fgure 5. Pror to desgnng the crcut, we have to make a few observatons. The frst observaton s that α j α =( (α j α)α )α. (2) Let us denote an output response from a mxed-sgnal CUT by. Thesecond observaton s that the response can be consdered as an exponent of the power, that s, α. Essentally, ths means that the arthmetc values are mapped nto algebrac values α. Based on these observatons, we can desgn a sgnature analyzer n the way shown n Fgure 8. Hereαs a prmtve element of a fnte feld GF(2 n ); n concdes wth the bt-length of the output responses. The lower and upper nputs of the multplexer n Fgure 8 are connected together, snce α 2n = α n GF(2 n ). Consderng the case when the analyzer s fed by -bt data, ts more detaled mplementaton wll have the form of Fgure 9. Here the buses consst of lnes, as ndcated by the approprate number. The ntal content of the SA before the shft s α j,ora 2 x 2 a xa n the polynomal form (we have omtted the superscrpts for the sake of smplcty). The notatons a k and a k, where ndex k can be one of,, and 2, ndcate the present and next states, respectvely. α j2n 2 α α j α α j α j α Fgure 8: A more detaled symbolc form of the SA. α j α j α j6 α j5 α j4 α j α j2 α j α j(7) a 2 a way α j 4 -bt MUX 2 a 2 a a Fgure 9: A regster transfer level mplementaton of the SA. α j a α j Amultplerbyα n GF(2 ) s realzed bearng n mnd that g(x) = x x, α corresponds to x,and (a 2 x 2 a xa )xmod g (x) =(a 2 x a x 2 a x) mod g (x) =a 2 (x) a x 2 a x =a x 2 (a 2 a )xa 2. () ThsoperatonsshownbycrosslnesnFgure9. The multplexer nputs and 7 are ted together, because α 7 = α n the feld GF(2 ). In order to demonstrate how to use ths analyzer, we wll assume that t receves only two values from a CUT, n partcular j and. Snce the CUT s of a mxed-sgnal nature, there s an unavodable (and thereby permtted) devaton of these values by ± (the greater tolerances can also be consdered). The analyzer wll map the receved data nto α j± and α ±, respectvely. If we assume that the ntal content of the SA s (versus for a conventonal SA), then after the frst shft the content becomes α α j± =α j±.afterthe second shft, t changes to α j± α ± =α j±2. Ths expresson s derved usng the nterval arthmetc rules. It states that for the fault-free CUT the actual result must match one of

5 VLSI Desgn 5 the values from the nterval [α j 2,α j2 ], that s, one of the followng: α j 2,α j,α j,α j,α j2. (4) To further smplfy the SA operaton, we wll assume that nstead of α (.e., ) the ntal SA content s α (j).we wll refer to ths value as the seed value. Then, by the same reasonng, the SA content after two shfts wll match one of the followng powers: α 2,α,α,α,α 2. (5) Due to the closure property of the feld GF(2 ),thspower set s equvalent to α 5,α 6,α,α,α 2. (6) Consequently, the decson makng crcut n Fgure wll work as follows. If the actual sgnature does not match any value from set (6), the CUT s consdered to be faulty. Snce these values are ordered (and surround the power α ), the decson makng crcut can employ a comparator, thereby reducngthehardwarecomplextyofthesa. As n any sgnature analyzer, some errors n the CUT output responses may escape detecton. The alasng rate can be estmated as descrbed n [6] and wll concde wth the alasng rate of the conventonal analyzer. Example. Let us consder a -bt CUT, whch s fed by two nput stmul. Under the fault-free operaton, the CUT produces the output responses j = ± and = ±. Therefore, the seed value wll be α (j) =α (56) =α =α, or n the vector form. If the CUT s fault-free, then after 2 shfts the SA content must match one of the elements n set (6). For example, f the actual responses are = (or α 6 )and = (or α 7 )(.e.,thevaratonsarewthn the tolerance bounds), the sgnature wll be α α 6 α 7 = α 2 whch belongs to set (6). And the decson makng crcut wll generate a pass sgnal. The valdty of such a decson s determned by the alasng rate. Let us assume that a fault n the CUT has made the followng changes n the output responses: (α 6 α )and (α 7 α 4 ). Then the actual sgnature wll become α α α 4 =α. Ths element does not belong to set (6), so the fault s detected. There are two dstnct ways of desgnng the decson makng crcut dependng on the optmzaton crtera (tme or hardware overhead). Hardware Overhead. If performance s paramount and tme overhead s not desrable, the followng approach can be employed. Let m bethenumberofoutputresponses.allofthe 2m α-multpler outputs (see Fgure 8)thatbelongtoset (6) areconnectedtothefrstnputsofthe2m comparators of a smlar type. The second nputs of these comparators are shared and fed by the vector. If the CUT s fault-free, one of the comparators wll produce a logc sgnal. The logc OR of the comparator outputs wll consttute a pass/fal sgnal. n {... Fgure : An n-bt comparator. The above procedure s based on the fact that the faultfree CUT produces one of the sgnatures from set (6).If the actual sgnature s α, the comparator connected drectly to the sgnature regster produces a logc, thus ndcatng that the CUT s fault-free. If the actual sgnature s α 6, then the product α 6 α, generated at the output of the frst α-multpler, equals, whch s detected by the next comparator. The same reasonng apples to the rest of the sgnatures from set (6). The logc dagram of the n-bt comparator s shown n Fgure. Tme Overhead. If tme overhead s allowed, the hardware complexty can be further reduced. In terms of mplementaton, t s more convenent to use the followng seed value: α (jm),wherem s the number of output responses. For the above example, α () =α,andset(6) wll transform to α 2,α,α 4,α 5,α 6. (7) After the last output response has been shfted n, the SA contnues to shft ts content 2m more tmes, whle the nput s forced to. Ths ensures that the SA content s multpled by α wth each shft. For the above example, 2m = 5. If, wthn ths tme, the match wth an element of set (7) has been determned, the CUT s consdered to be fault-free. Otherwse, t s faulty. If the CUT s fault-free and ts output responses have not exceeded ther tolerances, then whle cyclng through the states durng the extra 2m shfts, the output of the multplexer n Fgure 8 wll go through the power α or vector. The match wth the vector s detected by the comparator of Fgure connected to the multplexor s output. The comparator output s actually producng a pass/fal sgnal. The mplementaton complexty of the crcut of Fgure 8 ncreases sgnfcantly wth the growth of the data wdth, n. Therefore, ths crcut can only be mplemented for the output responses wth relatvely low values of n.forgreatervaluesof n, wewllmodfythecrcutoffgure8 to the one shown n Fgure. The modfed crcut contans bnary-weghted stages and s more economcal n terms of hardware. The complexty of the multpler α s comparable wth that of the multpler α, whereasthenumberofmultplersdrops from 2 n to n. The economy ncreases wth the growth of n. Forthecaseof-btdata,thecrcutofFgure transfers to the one shown n Fgure 2. Ths crcut operates much n the same way. The α -multplers structure s determned from the followng expressons: x(a 2 x 2 a xa ) mod g (x) =a x 2 (a 2 a )xa 2,

6 6 VLSI Desgn α 2n α 2 α αj Fgure : A bnary-weghted verson of the SA.. α j V cc R2 S Sw V cc V R n V Freescale 9S2DG28 A7 A6 A5 A4 A A2 A A Str Altera DE2 Cyclone II 2C5 D α 4 α 2 α a 2 a a α j a 2 a a $FF Fgure : The expermental setup. $FE Fgure 2: A regster transfer level mplementaton of the -bt SA. Code $FD $4 x 2 (a 2 x 2 a xa ) mod g (x) =(a 2 a )x 2 (a 2 a )xa, x 4 (a 2 x 2 a xa ) mod g (x) =(a 2 a a )x 2 (a a )x(a 2 a ). 4. Expermental Results (8) The expermental setup to test the proposed method of sgnature analyss s shown n Fgure. The setup ncludes the mcrocontroller system board Adapt9S2D (Technologcal Arts Inc.) based on Freescale s 9S2DG28 mcrocontroller and the Altera DE2 Development board based on the Cyclone II EP2C5F672C6 feld-programmable gate-array (FPGA) devce. We have selected 6 nput test stmul (voltages V n ) equally dstrbuted over the range ( 5.2)V and appled them to the analog-to-dgtal converter (ADC) of the 9S2 mcrocontroller (whch served as a mxed-sgnal system). Each nput voltage, V n, was measured by a hgh-precson voltmeter and regarded as a nomnal test nput value. The crcut n Fgure operates as follows. Every tme the swtch Sω s closed, the system performs 8 measurements of the same test sgnal and averages the result by accumulatng the sum of the eght 8-bt measurements and shftng t rght three tmes, whch elmnates nose. The ADC transfer characterstc s presented n Fgure 4 [7]. Accordng to ths characterstc, each converson result for a properly operatng devce can devate from the nomnal value by ±, whch s an mplcaton of the fact that the permssble $ $2 $ $ a b (mv) Fgure 4: 9S2 ADC transfer functon. dfferental nonlnearty can range from.5 to.5 LSB (see shadowed boxes n Fgure 4). For example, f V n = 4 mv, the converson result can be $, $2, or$ (n the worst case, the ponts a and b concde). Therefore, each of the thrty-two 8-bt average results contans an error of at most ± count. The test stmul have been selected equal to the mdponts of the quantzaton bns, thereby ncreasng the uncertanty and worsenng the probablty of undetected error.iftheteststmulwouldhavebeenselectedatthe transton ponts of the characterstc, the probablty of undetected error (alasng rate) would mprove. Ths follows from the observaton that each converson would result n 2 possble values as opposed to possble values n the prevous case. As soon as average values of the converson results are computed by the mcrocontroller, they are transferred to the DE2board.Thetransferofeachdatumsaccompanedbya hgh-to-low transton of the strobe sgnal Str.The Str sgnal serves as a clock for the state machne that mplements the sgnature analyzer (n ts 8-bt confguraton). The sgnature, D, V n

7 VLSI Desgn 7 Table 2: Relatonshp between nput test stmul and output responses. Input voltage Output code mv Mn Nom. Max No fault Fault Fgure 5: All output code devatons are wthn the tolerance bounds. Fgure 6: Some of the output code devatons exceed the tolerance bounds. Fgure 7: The combnaton s detected: ADC s operatng properly. s dsplayed on a two-dgt7-segment dsplay n hexadecmal form. The frst experment was performed on the properly operatng devce. In the second experment, the average results were corrupted dgtally n the mcrocontroller (thereby smulatng random faults n the ADC) and sent to the analyzer. The analyzer has correctly dentfed the faulty devce. The relatonshp between nput voltages and output codes s presented n Table 2. Based on ths table and takng nto consderaton that g(x) = x 8 x 4 x x 2, the seed value s calculated as follows: = 984 = 99 mod (2 8 ) = 99, α 99 =α 56 =, Seed Value =α 56 α 6 =α 4 = = 6. (9) In addton to test experments, the operaton of the analyzer (the DE2 part of the test setup) was smulated usng Altera Quartus II software. Based on the two experments represented n Table 2, the sgnatures that correspond to fault-free and faulty ADCs are, respectvely, 2 and 2 (n decmal form). The process of calculaton of these sgnatures s demonstrated n Fgures 5 and 6. Fgures7 and 8 represent the fault detecton process. The actual fnal sgnatures are shfted addtonally 2 tmes. If the value appears n the analyzer durng these shfts, the system s fault-free. Otherwse t s faulty. The smulaton results matched the expermental results. 5. Concluson We examned an algebrac sgnature analyss method that can be employed for mxed-sgnal crcuts testng. We demonstrated how to desgn the approprate devce. Ths devce does Fgure 8: The combnaton s not detected: ADC s faulty. not produce arthmetc carres and s therefore less prone to errors. The absence of carry propagatng crcutry also contrbutes to the hgher performance of the devce. The proposed scheme can also be used n arthmetc and algebrac error-control codng, as well as cryptography. Conflct of Interests The authors declare that there s no conflct of nterests regardng the publcaton of ths paper. References [] R. Frohwerk, Sgnature analyss: a new dgtal feld servce method, Hewlett-Packard Journal,vol.28, no.9,pp.2 8, 977. [2]G.J.Starr,J.Qn,B.F.Dutton,C.E.Stroud,F.F.Da,and V. P. Nelson, Automated generaton of bult-n self-test and measurement crcutry for mxed-sgnal crcuts and systems, n Proceedngsofthe5thIEEEInternatonalSymposumon Defect and Fault Tolerance n VLSI Systems (DFT 9), pp. 9, October 29. [] D.K.PradhanandS.K.Gupta, Anewframeworkfordesgnng and analyzng BIST technques and zero alasng compresson, IEEE Transactons on Computers, vol.4,no.6,pp.74 76, 99. [4] C.Stroud,J.Morton,T.Islam,andH.Alassaly, Amxed-sgnal bultn self-test approach for analog crcuts, n Proceedngs of the Southwest Symposum on Mxed-Sgnal Desgn,pp.96 2, 2.

8 8 VLSI Desgn [5] N.Nag,A.Chatterjee,H.Yoon,andJ.A.Abraham, Sgnature analyss for analog and mxed-sgnal crcut test response compacton, IEEE Transactons on Computer-Aded Desgn of Integrated Crcuts and Systems,vol.7,no.6,pp ,998. [6] N. Nag, A. Chatterjee, and J. A. Abraham, Sgnature analyzer for analog and mxed-sgnal crcuts, n Proceedngs of the IEEE Internatonal Conference on Computer Desgn: VLSI n Computers and Processors, pp , October 994. [7] S.Mr,M.Lubaszewsk,V.Lberal,andB.Courtos, Bult-n self-test approaches for analogue and mxed-sgnal ntegrated crcuts, n Proceedngs of the IEEE 8th Mdwest Symposum on Crcuts and Systems,vol.2,pp.45 5,RodeJanero,Brazl, August 995. [8] J. Rajsk and J. Tyszer, The analyss of dgtal ntegrators for test response compacton, IEEE Transactons on Crcuts and Systems II: Analog and Dgtal Sgnal Processng, vol.9,no.5, pp.29,992. [9]L.WeandL.Ja, Anapprachtoanalongandmxed-sgnal BIST based-on pseudorandom testng, n Proceedngs of the IEEE Internatonal Conference on Communcatons, Crcuts and Systems, (ICCCAS 8), pp , Fujan, Chna, May 28. [] F. Cors, C. Marzocca, and G. Matarrese, Defnng a BISTorented sgnature for mxed-sgnal devces, n Proceedngs of the IEEE Southwest Symposum on Mxed-Sgnal Desgn, pp , 2. [] S. Demdenko, V. Pur, V. Yarmolk, and A. Shmdman, Bst module for mxed-sgnal crcuts, n Proceedngs of the IEEE Internatonal Symposum on Defect and Fault Tolerance n VLSI Systems, pp , 998. [2] T. Damarla, Implementaton of sgnature analyss for analog and mxed sgnal crcuts, U.S. Patent , 22. []W.W.PetersonandJ.Weldon,Error Correctng Codes, MIT Press, Cambrdge, Mass, USA, 2nd edton, 972. [4] V. Geurkov, Optmal choce of arthmetc compactors for mxed-sgnal systems, n Proceedngs of the IEEE Internatonal Symposum on Defect and Fault Tolerance n VLSI and Nanotechnology Systems (DFT 2), pp , October 22. [5] S.LnandD.Costello,Error Control Codng, Pearson Educaton, Upper Saddle Rver, NJ, USA, 24. [6] V. Geurkov, V. Krschan, L. Krschan, and R. Sedaghat, Concurrent testng of analog-to-dgtal converters, -manager s Journal on Electroncs Engneerng,vol.,no.,pp.8 4,2. [7] MC9S2DT28 Devce User Gude, V2., Motorola, May 24,

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