High rate soft output Viterbi decoder

Transcription

1 High rate soft output Viterbi decoder Eric Lüthi, Emmanuel Casseau Integrated Circuits for Telecommunications Laboratory Ecole Nationale Supérieure des Télécomunications de Bretagne BP Brest Cedex FRANCE Abstract This paper presents the architecture of a high rate soft output Viterbi decoder ( Mb/s, 8 states, R=/), using the "radix" trellis method to speed up the rate of a decoder using the Viterbi algorithm and the a posteriori weighting algorithm. The size of this circuit is roughly twice that of the original soft output Viterbi decoder while the speed is increased by a factor of. Because of its performances, this circuit is very attractive for satellite digital communication systems and is at the root of "turbo-codes" [], which are a class of convolutional codes whose performances, in terms of bit error rate, are close to the Shannon limit. Introduction To improve the performance of digital communication systems, it is often useful to have a decoder which provides a reliability estimate of each decoded decision. In the case of convolutional codes, the Viterbi algorithm [] finds the path, in a trellis, corresponding to the series nearest to the series received, according to the a posteriori maximum likelihood criterion. At the end of the 8's, some modifications of this algorithm were proposed to get an estimate of the reliability of each decoded decision [3,4]. However these modifications were quite complicated for area-efficient implementation. A simplification of the weighting procedure, proposed by Berrou-Adde [5], which does not affect the reliability of the estimate, has recently made the de of a VLSI circuit possible [6]. However, for high data rate applications (typically more than 8 Mb/s), such as satellite transmissions, the power dissipation would be high with this method and, moreover, the Viterbi algorithm has to be altered. The decoded decisions are actually considered in "packets" of length M instead of one by one. This method allows a working frequency M times lower for some basic functions of Viterbi decoding and also for the weighting process, which is essential for the considered rates. The paper is structured in the following way : section briefly presents the Berrou-Adde algorithm used for the weighting process associated with the Viterbi algorithm. The "radix" trellis principle is formulated in section, then section 3 gives a description of the soft output Viterbi decoder architecture. We conclude by indicating performance. ) The a posteriori weighting algorithm In this presentation we suppose that the reader is familiar with the Viterbi algorithm that we consider in the case of binary codes for which the decoder has to select one of two paths for each of the states, where is the code memory. Let us call Ms(k,m) the accumulated metric of the survivor path at time k and state m, and Mc(k,m) the accumulated metric of the over path (concurrent path) linked to node m. Because the two paths give two opposite decisions and because the Viterbi algorithm chooses one of these two paths as the survivor, the difference Ms(k,m)-Mc(k,m) called the "concurrence" measure CM k (m) can be ased as a first estimate of the weight of the decision given by the survivor at state m about the decoded bit d(k). The greater the concurrence measure, the more reliable the choice of the survivor. However we can notice that if CM k (m)=, there is no particular reason to choose one path as the survivor instead of the other path. Therefore, if the previous decisions (d(k-), d(k-),...) on the survivor path and those on the concurrent path are opposite, the associated weight might be wrong. Thus a process called revision improves the basic weighting method by taking into account any eventual mistake in the choice of the survivor paths and updating if necessary the reliability of previous weights. To reduce the complexity of the revision process, the Berrou-Adde algorithm, the so called a posteriori ED&TC /96 $ IEEE

2 weighting algorithm, proceeds in two steps. The first decoding step is the Viterbi decoding. Every time k, the trace-back operation in a path memory T of length L (truncation length) provides a decision d(k-l) of the decoded bit and the associated state N(k-L). Assuming L is sufficiently large, the final survivor state no longer changes and it is thus possible to perform the revision process with a second trellis T' of length L' on a single path returning from state N(k-L). Since the concurrence measure CM k-l (N(k-L)) is given to be the first estimate of the weight w(k-l) of decision d(k-l), computations of the are therefore repeated L clock periods later and CM k-l (N(k-L)) is selected from concurrence measures according to the state N(k-L). This temporary weight is then stored in a shift register of length L' and acts as the updating weight for all the contents of this shift register - that is to say the previous weights - according to the following procedure : - if the decision d(k-l-x) with x=,...,l' on the survivor path in trellis T' is different from that on the concurrent path and if w(k-l) = CM k-l (N(k-L)) < w(k-l-x), then w(k-l-x) = w(k-l). The weight w(k-l-l') provided at the output of the shift register, which has been revised L' times maximum, constitutes the definitive weight attributed to the binary decision d(k-l-l') available at the output of trellis T' and relative to time k-l-l'. From a practical point of view, since the weighting process is done in a serial and pipelined manner with the Viterbi decoding, it does not lower the speed of the decoder. Furthermore, the size of the Viterbi decoder including the Berrou-Adde revision process is only twice that of a classical Viterbi decoder, which is suitable for cost-effective VLSI implementation. ) Radix trellis principle A convolutional encoder is a discrete-time Markov process in which transitions take place from the state of time n.t to the new state of time (n+).t. However, it is also possible to deal with this process in periods of time M.T (M=,,3,...) considering all the transitions from one state to another between instants k.m.t and (k+).m.t as a single collapsed transition. Thus, the original trellis, denoted T, can be reconstructed only considering all of the k.m.t instants of a radix- M trellis denoted T M (figure ). Collapsing the trellis does not affect decoder performance since the associated Viterbi decoder considers each collapsed transition made up of M transitions of the original trellis. Obviously, the decoder provides M decisions per decoding step instead of the usual one decision. k.t (k+4).t (k+8).t 4 Figure : Radix trellis T and T 4 for = 3) Radix-4 soft output Viterbi decoder The complexity of the Viterbi algorithm (with M=) does not allow high data rate Viterbi decoders to be deed despite advances in VLSI technology (typically 4 Mb/s for worst case process conditions, =3-4, 6- level soft decision input with.8 µm CMOS technology). Theoretically, very high speed Viterbi decoders can be developed using the radix method. However, the more the trellis is collapsed, the more complex the hardware. In fact, decoder complexity increases with the number M of collapsed transitions linked to a state of the radix trellis due to computations and selections of the accumulated. The following table presents the complexity factor and the theoretical speed-up factor of a Viterbi decoder for different values of M. M M C S S/C complexity ideal speed-up Thus, according to the speed-up/complexity ratio, M= is very attractive for area-efficient VLSI implementation. In this case, the size of the circuit is not excessively increased while increasing the decoded data rate by two. In practice, the speed-up factor is also almost two [7]. Moreover, although the a posteriori weighting process does not lower the speed of Viterbi decoders, it is not directly well suited for high rates because of power dissipation problems due to the speed of the trace-back operation associated with the revision. However, this process can be achieved at a rate M times lower with the radix trellis method as described above. The radix trellis principle thus offers two advantages for soft Viterbi decoding : it allows the decoded data rate to be increased on the one hand, and the power dissipation to be reduced on the other. Time

3 Since M= is attractive for area-efficient Viterbi decoding, the weighting algorithm and the architecture of a soft output radix-4 Viterbi decoder is presented below. 3.) The weighting algorithm Since 4 collapsed transitions link a state with a radix-4 trellis, the Viterbi algorithm has to select one of 4 paths as the survivor and we get thus 3 concurrent paths instead of one as is usual. This selection provides two decisions. The easiest way to weight these decisions is to consider them as a single decision, asing them the same weight. The a posteriori algorithm can then be applied directly, giving as a first estimate of the weight the smallest of the 3 concurrence measures associated with the survivor state. It then updates previous weights, doing a trace-back operation with the survivor path and the concurrent path associated with the smallest concurrence measure. The reliability estimate can however be noticeably improved if each of the two decoded decisions has its own weight. Let us consider the example of a 4-state trellis in figure. Assuming N (k'-l f ) is the final survivor state of path memory T of length L f where k'= (k+)/ is the new time index associated with the radix-4 trellis, and assuming SP is the survivor path, we get two main concurrent paths denoted CP and CP respectively starting from states N (k'-l f ) and N (k'-l f ). N (k'--lf) N (k'--lf) SP CP CP second trellis T'. Then, every decoding step the revision algorithm is the following : - revision of w (k'-l f -x) : case : if d (k'-l f -x).d' (k'-l f -x) < then w (k'-l f -x) = min(w (k'-l f ), w (k'-l f -x)) ; case : if d (k'-l f -x).d'' (k'-l f -x) < then w (k'-l f -x) = min(w (k'-l f ), w (k'-l f -x)) ; - revision of w (k'-l f -x) : case : if d (k'-l f -x).d' (k'-l f -x) < then w (k'-l f -x) = min(w (k'-l f ), w (k'-l f -x)) ; case : if d (k'-l f -x).d'' (k'-l f -x) < then w (k'-l f -x) = min(w (k'-l f ), w (k'-l f -x)). Furthermore, before applying this algorithm, the concurrence measure w (k'-l f ) has to be revised by w (k'-l f ) if d (k'-l f ) and d'' (k'-l f ) are opposite. Simulations suggest that the truncation length L f and L' f are not modified using the radix-4 principle. Thus L f is 4 or 5 times the constraint length K=+ for an R=/ coding rate (usual truncation length of Viterbi decoders) while L' f is still half the value of L f. This weighting algorithm, where each decision has its own dedicated weight, is more complex than that with one single weight associated with two decisions. It is thus relevant for applications where the reliability estimate is of major interest. 3.) Architecture of the radix-4 soft output Viterbi decoder A soft output Viterbi decoder implementing the a posteriori weighting algorithm is made up of four main blocks : a transition metric unit, an ACS unit, a memory unit - like a classical Viterbi decoder - and a weighting unit. These units are presented below in the case of a radix-4 trellis. ' time memorization level Figure : Radix-4 weighting principle scheme The concurrence measures CM k'-lf (N (k'-l f )) and CM k'-lf (N (k'-l f )) can then be the first estimates of weights w (k'-l f ) and w (k'-l f ) of decisions d (k'-l f ) and d (k'-l f ). The revision process in this case compares the decisions on the survivor and two-concurrent paths and updates the previous weights if necessary. Let us call d' (k'-l f -x) and d' (k'-l f -x) the decisions on path CP and d'' (k'-l f -x) and d'' (k'-l f -x) the decisions on path CP with x=,...,l' f where L' f is the length of the a) Radix-4 transition metric unit With a radix-4 trellis, there are 6 radix-4 transition every decoding step. Two radix- transition metric units TMU are dedicated to the computations of the transition associated with the q -level input samples (X k,y k ) : one for even times k and one for odd times k (figure 3). Each radix- transition metric unit thus computes 4 radix- transition every time k'= (k+)/, which makes the calculation of the 6 radix-4 transition possible in a transition metric adder denoted TMA.

4 Xk, Yk.q ) Xk', Yk' q Xk', Yk' q TMU TMU 4.q 4.q TMA radix-4 transition 6.(q+) Figure 3 : Radix-4 transition metric unit b) Radix-4 ACS unit Since 4 transitions link a state with a radix-4 trellis, an Add-Compare-Select processor (ACS) is used for each state to compute the 4 associated accumulated and to select the most likely one. The structure of an ACS is thus : 4 adders, comparator to compare the 4 accumulated and one 4: multiplexer (figure 4). This comparator can be implemented in two different ways : - 3 comparators of two, connected like a tree ; - 6 comparators comparing the 6 possible pairs of accumulated, and additional logic to determine the final result. The first solution requires a smaller area but leads to a longer time delay. As far as speed is concerned, the second solution is the better one. radix-4 transition state (q+) (q+) (q+) (q+) decisions {d (k',m),d (k',m)} state In the case of a radix-4 trellis, since two decisions are provided per decoding step, two register exchange circuits placed in parallel can be used. For instance, for path memory T, decisions associated with even times k are stored in a path memory T of length L f /, while decisions associated with odd times k are stored in another path memory T of length L f /. From a practical point of view, the total truncation length is not modified. However, the REA thus operates at half the data rate which ificantly reduces power consumption. Register exchange circuits use multiplexed flip-flops as memory cells. 4: multiplexers are used with a radix-4 trellis whereas : multiplexers are used with a radix- trellis. Furthermore, there are twice the number of wires between two register exchange cells and multiplexer selection leads as usual. The radix-4 REA area is thus roughly 4 % bigger than the classical one. d) Radix-4 weighting unit According to the concurrence measure given as a first estimate of the weight of a decision provided by the Viterbi decoder, the revision process updates the weights of previous decisions comparing decisions on the survivor and concurrent paths from the final survivor state determined with classical Viterbi decoding. In order to compute the two concurrence measures w (k'-l f ) and w (k'-l f ) associated with the two decisions of each radix-4 decoding step, the computations of the accumulated are repeated and the corresponding are selected with state N (k'-l f ) and decisions d (k'-l f ) and d (k'-l f ) (figure 5). An additional radix-4 transition metric unit and an ACS unit are thus necessary for the weighting unit. accumulated from the second ACS unit 3.w : multiplexer 4.w.w.w.w comparator w w d'' (k'-lf) soustractor soustra- ctor Figure 4 : Radix-4 ACS processor d (k'-lf) d (k'-lf) c) Radix-4 path memory unit The path memory unit makes the trace-back operation possible with the decisions provided by the ACS processors. The Register Exchange Algorithm (REA) [8] is very well suited to high speed Viterbi decoder path storage. Furthermore, register exchange circuits are suitable for comparing every decision on the survivor and the concurrent paths of the second trellis T' for the revision process. Figure 5 : Concurrence measure circuit Since two decisions are provided every decoding step, the temporary weights are stored in a shift register of length L' f / with two weights per level (w (k'-l f -x) and w (k'-l f -x)). As discussed in section c, the second trellis T' is made up of two register exchange trellises T' and T' of length L' f / which ificantly reduces power consumption. Further logic finally performs the revision

5 process described in section 3. (figure 6). Every decoding step, two decisions d (k'-l f -L' f ) and d (k'-l f -L' f ) of weight w (k'-l f -L' f ) and w (k'-l f - L' f ) are thus respectively available at the outputs of trellises T' and T' and at the outputs of the shift register. accumulated from the second ACS unit 3.w d (k'-lf) d (k'-lf) concurrence measures circuit revision logic shift register x (L'f)/ W Lf+Lf' W Lf+Lf' (k') (k') survivor path and the 3 concurrent paths), instead of the 3 paths mentioned in this paper. In fact, increasing the severity of the revision process introduced with this additional concurrent path may be a useful way to detect a wrong survivor path. This modification increases the weighting area to less than 5 % whereas the Viterbi decoding part is not modified. This solution is currently being developed for decoders using the turbo-code principle [], turbo-codes being a class of convolutional codes whose performances in terms of Bit Error Rate (BER) are close to the Shannon limit. Finally, if we want to have higher data rates, radix-8 Viterbi decoding is feasible if a slight loss of quality of the weighting reliability is accepted, because of necessary simplifications of the revision process for cost-effective VLSI implementation. comparison comparison References from trellises {T,T} SEL' SEL'' N (k'+-lf) x trellis T' trellis T' shifting shifting Figure 6 : Radix-4 revision scheme d (k'-lf-l'f) d (k'-lf-l'f) From a practical point of view, this revision scheme including the radix-4 transition metric unit and ACS unit is twice more complex to implement than the original one. Twice as many gates are necessary whereas the number of revision wires used is multiplied by 3. Conclusion Using the radix-4 trellis principle it is possible to implement a Viterbi decoder which operates at nearly twice the data rate of a classical Viterbi decoder. This method applied to the Berrou-Adde weighting algorithm makes it possible to de with the COMPASS tool a Mb/s (for worst case process conditions), 6-level decision input/output, R=/, 8 state Viterbi decoder using.6 µm CMOS technology. The size of the circuit is roughly twice that of the original decoder for a data rate multiplied by : the estimated area of the radix-4 soft output Viterbi decoder is 8.8 mm² whereas it is 4.5 mm² for the original circuit (radix-). The proposed revision algorithm does not alter the weighting reliability of the original one. It is however possible to slightly improve this reliability doing a traceback with all paths linked to the final survivor state (the [] C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error correcting coding and decoding : turbocodes", IEEE ICC' 93, Vol. /3, pp. 64-7, Geneva, May 993. [] A. J. Viterbi, "Error bounds for convolutional codes and an asymptotically optimum decoding algorithm", IEEE Trans. Inform. Theory, Vol. IT-3, pp. 6-69, April 967. [3] G. Battail, " Pondération des symboles décodés par l'algorithme de Viterbi" (in French), Annales des Télécommunications, N -, pp. 3-38, Jan.-Feb [4] J. Hagenauer, P. Hoeher, " A Viterbi algorithm with softdecision outputs and its applications", Proc. GLOBECOM '89, pp , Dallas, Texas, Nov [5] C. Berrou, P. Adde, "Procédé de décodage d'un code convolutif à maximum de vraisemblance et pondération des décisions, et décodeur correspondant" (in French), French patent N 9 579, 3 April 99. [6] "CAS593 : turbo encoder/decoder" Data sheet, COMATLAS, Chateaubourg, France, Nov [7] P. J. Black, H. Meng, "A 4-Mb/s, 3-State, Radix-4 Viterbi Decoder", IEEE Journal of solid-state circuits, VOL. 7, N, Dec. 99. [8] E. Paaske, S. Pedersen, J. Sparso, "An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders", Integration, the VLSI journal, N, pp. 79-9, Dec 99.