NB4N11M. 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator

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1 NB4NM. V. Gb/s Multi Level Clock/ata Input to CML Receiver/ Buffer/ Translator escription The NB4NM is a differential to clock/data distribution/translation chip with CML output structure, targeted for high speed clock/data applications. The device is functionally equivalent to the EP, LVEP, SG or 7LM devices. evice produces two identical differential output copies of clock or data signal operating up to. GHz or. Gb/s, respectively. As such, NB4NM is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVS (See Table ). The CML outputs are 6 ma open collector (See Figure 8) which requires resistor (R L ) load path to V TT termination voltage. The open collector CML outputs must be terminated to V TT at power up. ifferential outputs produces current mode logic (CML) compatible levels when receiver loaded with 0 or loads connected to.8 V,. V or. V supplies (see Figure 9). This simplifies device interface by eliminating a need for coupling capacitors. The device is offered in a small 8 pin TSSOP package. Application notes, models, and support documentation are available at Features Maximum Input Clock Frequency >. GHz Maximum Input ata Rate >. Gb/s Typically ps of RMS Clock Jitter Typically 0 ps of ata ependent Gb/s, R L = 4 ps Typical Propagation elay 0 ps Typical Rise and Fall Times Operating Range: V CC =.0 V to.6 V with V EE = 0 V and V TT =.8 V to.6 V Functionally Compatible with Existing. V /. V LVEL, LVEP, EP, and SG evices These are Pb Free evices* 8 T SUFFIX CASE 948R MARKING IAGRAM* 8 EM ALYW A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AN800/. Figure. Functional Block iagram 0 0 ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 0 of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. Semiconductor Components Industries, LLC, 0 November, 0 Rev. Publication Order Number: NB4NM/

2 NB4NM 0 8 V CC V EE Figure. Pinout (Top View) and Logic iagram Table. Pin escription Pin Name I/O escription 0 CML Output Noninverted differential output. Typically receiver terminated with 0 resistor to V TT. Open collector CML outputs must be terminated to V TT at powerup. 0 CML Output Inverted differential output. Typically receiver terminated with 0 resistor to V TT. Open collector CML outputs must be terminated to V TT at powerup. CML Output Noninverted differential output. Typically receiver terminated with 0 resistor to V TT. Open collector CML outputs must be terminated to V TT at powerup. 4 CML Output Inverted differential output. Typically receiver terminated with 0 resistor to V TT. Open collector CML outputs must be terminated to V TT at powerup. V EE Negative supply voltage. 6 LVPECL, CML, HSTL, LVCMOS, LVS, LVTTL Input 7 LVPECL, CML, HSTL, LVCMOS, LVS, LVTTL Input Inverted differential input. Noninverted differential input. 8 V CC Positive supply voltage.

3 NB4NM Table. ATTRIBUTES Characteristics Value ES Protection Human Body Model Machine Model > 000 V > 70 V Moisture Sensitivity (Note ) 8 TSSOP Level Flammability Rating Oxygen Index: 8 to 4 UL 94 V 0. in Transistor Count 97 Meets or exceeds JEEC Spec EIA/JES78 IC Latchup Test. For additional information, see Application Note AN800/. Table. MAXIMUM RATINGS Symbol Parameter Condition Condition Rating Unit V CC Positive Power Supply V EE = 0. V 4 V V EE Negative Power Supply V CC = +0. V 4 V V I Positive Input Negative Input V EE = 0 V V CC = 0 V V I = V CC +0.4 V V I = V EE 0.4 V 4 4 V V V O Output Voltage Minimum Maximum V EE V CC + mv mv T A Operating Temperature Range 40 to +8 C T stg Storage Temperature Range 6 to +0 C JA Thermal Resistance (Junction to Ambient) (Note ) 0 lfpm 00 lfpm 90 0 C/W C/W JC Thermal Resistance (Junction to Case) SP (Note ) 4 to 44 C/W T sol Wave Solder < 60 C 6 C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. JEEC standard multilayer board SP ( signal, power) with 8 filled thermal vias under exposed pad.

4 NB4NM Table 4. C CHARACTERISTICS, CLOCK Inputs, CML Outputs V CC =.0 V to.6 V, V EE = 0 V, T A = 40 C to +8 C Symbol Characteristic Min Typ Max Unit I CC Power Supply Current (Inputs and Outputs Open) ma R L = 0, V TT =.6 V to. V V OH Output HIGH Voltage (Note ) V TT 60 V TT 0 V TT mv V OL Output LOW Voltage (Note ) V TT 00 V TT 800 V TT 640 mv V O ifferential Output Voltage Magnitude mv R L =, V TT =.6 V to. V % V OH Output HIGH Voltage (Note ) V TT 60 V TT 0 V TT mv V OL Output LOW Voltage (Note ) V TT 0 V TT V TT mv V O ifferential Output Voltage Magnitude mv R L = 0, V TT =.8 V % V OH Output HIGH Voltage (Note ) V TT 70 V TT 0 V TT mv V OL Output LOW Voltage (Note ) V TT 00 V TT 800 V TT 640 mv V O ifferential Output Voltage Magnitude mv R L =, V TT =.8 V % V OH Output HIGH Voltage (Note ) V TT 8 V TT 0 V TT mv V OL Output LOW Voltage (Note ) V TT 00 V TT V TT mv V O ifferential Output Voltage Magnitude mv IFFERENTIAL INPUT RIVEN SINGLE ENE (Figures 4 and 6) V th Input Threshold Reference Voltage Range (Note ) V EE V CC mv V IH Single ended Input HIGH Voltage V th + 00 V CC + mv V IL Single ended Input LOW Voltage V EE V th 00 mv IFFERENTIAL INPUTS RIVEN IFFERENTIALLY (Figures and 7) V IH ifferential Input HIGH Voltage V EE V CC + mv V IL ifferential Input LOW Voltage V EE V CC 00 mv V CMR Input Common Mode Range (ifferential Configuration) V EE V CC mv V I ifferential Input Voltage Magnitude ( V IH V IL ) (Note 7) 00 V CC V EE mv C IN Input Capacitance (Note 7). pf NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 00 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously.. CML outputs require R L receiver termination resistors to V TT for proper operation. Outputs must be connected through R L to V TT at power up. The output parameters vary : with V TT. 4. Input parameters vary : with V CC.. V th is applied to the complementary input when operating in single ended mode. 6. V CMR (MIN) varies : with V EE, V CMR max varies : with V CC. 7. Parameter guaranteed by design and evaluation but not tested in production. 4

5 NB4NM Table. AC CHARACTERISTICS V CC =.0 V to.6 V, V EE = 0 V; (Note 8) Symbol V OUTPP V OUTPP Characteristic Output Voltage Amplitude (R L = 0 ) f in GHz (See Figure ) f in. GHz f in.ghz Output Voltage Amplitude (R L = ) f in GHz (See Figure ) f in. GHz f in.ghz 40 C C 8 C Min Typ Max Min Typ Max Min Typ Max f ATA Maximum Operating ata Rate Gb/s t PLH, t PHL Propagation elay to Output 0. GHz ps Unit mv mv t SKEW uty Cycle Skew (Note 9) Within evice Skew evice to evice Skew (Note ) t JITTER V INPP RMS Random Clock Jitter R L = 0 and R L = (Note ) f in = 70 MHz f in =. GHz f in =. GHz Peak to Peak ata ependent Jitter R L = 0 f ATA =. Gb/s (Note ) f ATA =. Gb/s Peak to Peak ata ependent Jitter R L = f ATA =. Gb/s (Note ) f ATA =. Gb/s Input Voltage Swing/Sensitivity (ifferential Configuration) (Note 0) t r Output Rise/Fall 0. GHz, t f (% 80%) mv ps ps ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 00 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured by forcing V INPP (MIN) from a 0% duty cycle clock source. All output loaded with an external R L = 0 and R L = to V TT. Outputs must be connected through R L to V TT at power up. Input edge rates 0 ps (% 80%). 9. uty cycle skew is measured between differential outputs using the deviations of the sum of T pw and T 0. GHz. 0.V INPP (MAX) cannot exceed V CC V EE. Input voltage swing is a single ended measurement operating in differential mode.. Additive RMS jitter with 0% duty cycle clock signal..additive peak to peak data dependent jitter with input NRZ data signal (PRBS ).. evice to device skew is measured between outputs under identical 0. GHz OUTPUT VOLTAGE AMPLITUE (mv) R L = R L = INPUT CLOCK FREUENCY (GHz) (V CC V EE =. V V TT =. C V in = 00 mv) Figure. Output Voltage Amplitude (V OUTPP ) versus Input Clock Frequency (f IN ) at Ambient Temperature (Typical) OUTPUT VOLTAGE AMPLITUE (mv) R L = 0 R L = INPUT CLOCK FREUENCY (GHz) (V CC V EE =.0 V V TT =.7 C V in = 00 mv)

6 NB4NM NB4NM TIME (ps) C TIME (ps) 8 C C C INPUT CLOCK FREUENCY (GHz) Figure 4. ata ependent Jitter vs. Frequency and Temperature (V CC V EE =. V; V TT =. C; V IN = 00 mv; PRBS ; R L = C C INPUT CLOCK FREUENCY (GHz) Figure. ata ependent Jitter vs. Frequency and Temperature (V CC V EE =. V; V TT =. C; V IN = 00 mv; PRBS ; R L = TIME (ps) 40 t P TIME (ps) 40 t P TEMPERATURE ( C) Figure 6. Typical Propagation elay vs. Temperature (V CC V EE =. V; V TT =. C; V in = 00 mv; R L = 0 ) 00 V EE 0. V V CC V EE V CC + 0. V INPUT OFFSET VOLTAGE (V) Figure 7. Typical Propagation elay vs. Input Offset Voltage (V CC V EE =. V; V TT =. C; V in = 00 mv R L = 0 ) CURRENT (ma) 0 0 I CC TEMPERATURE ( C) Figure 8. Supply Current vs. Temperature 6

7 NB4NM VOLTAGE (0 mv/div) J = ps VOLTAGE (00 mv/div) J = ps TIME (66.8 ps/div) TIME (66.8 ps/div) Figure 9. Typical ifferential Output Waveform at 70 Mb/s (R L = 0 Left Plot, R L = Right Plot, V in = 00 mv, System J = 4 ps) VOLTAGE (0 mv/div) J = ps VOLTAGE (00 mv/div) J = ps TIME (. ps/div) TIME (. ps/div) Figure 0. Typical ifferential Output Waveform. Gb/s (R L = 0 Left Plot, R L = Right Plot, V in = 00 mv, System J = ps) VOLTAGE (0 mv/div) J = ps VOLTAGE (00 mv/div) J = 7 ps TIME (80 ps/div) TIME (80 ps/div) Figure. Typical ifferential Output Waveform. Gb/s (R L = 0 Left Plot, R L = Right Plot, V in = 00 mv, System J = 4 ps) 7

8 NB4NM V INPP = V IH () V IL () V OUTPP = V OH () V OL () t PHL t PLH Figure. AC Reference Measurement V TT 0 0 UT river evice Z = 0 Z = 0 Receiver evice Figure. Typical Termination for Output river and evice Evaluation V th V th Figure 4. ifferential Input riven Single Ended Figure. ifferential Inputs riven ifferentially V CC Vthmax V th V IHmax V ILmax V IH V th V IL V CC V CMmax V CMR V IHCLKmax V ILCLKmax V I = V IH V IL V IHtyp V ILtyp V thmin GN V IHmin V ILmin V CMmax GN V IHmin V ILmin Figure 6. V th iagram Figure 7. V CMR iagram 8

9 NB4NM V CC Input ES. k R C R. k C Input ES. k. k IN IN Input ES Input ES Internal Current Source 6 ma Current Source V EE Input V EE Output Figure 8. CML Input and Output Structure 9

10 NB4NM V TTA = V CCA V CC =. V NB4NM Z = 0 Z = V CCA =.8 V. V or. V Receiver A V TTB = V CCB V TTB = V CCB 0 0 Z = 0 Z = 0 V CCB =.8 V. V or. V 0 0 Receiver B V EE = 0 V V TTC = V CCC V CC =. V Z = V CCC =.8 V. V or. V NB4NM Z = 7 Receiver C V TT = V CC Z = 00 Z = 00 V CC =.8 V. V or. V Receiver V EE = 0 V Figure 9. Typical Examples of the Application Interface ORERING INFORMATION NB4NMTG NB4NMTRG evice Package Shipping (Pb Free) (Pb Free) 00 Units / Rail 00 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR80/. 0

11 NB4NM PACKAGE IMENSIONS T SUFFIX PLASTIC TSSOP PACKAGE CASE 948R 0 ISSUE A 0. (0.006) T 0. (0.006) T L U U S X L/ PIN IENT S 8 8x A V K REF (0.004) M T U S V S B U F 0. (0.00) M NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.M, 98.. CONTROLLING IMENSION: MILLIMETER.. IMENSION A OES NOT INCLUE MOL FLASH. PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0. (0.006) PER SIE. 4. IMENSION B OES NOT INCLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXCEE 0. (0.00) PER SIE.. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. 0.0 (0.004) T SEATING PLANE C G ETAIL E ETAIL E W MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.6 BSC 0.06 BSC K L 4.90 BSC 0.9 BSC M ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 6, Phoenix, Arizona 808 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, Meguro ku, Tokyo, Japan 00 Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. NB4NM/