CHAPTER 8 UNSYMMETRICAL FAULTS

Transcription

1 CHAPTER 8 UNSYMMETRCAL FAULTS The sequence circuits and the sequence networks developed in the previous chapter will now be used or inding out ult current during unsymmetrical ults. Speciically we are going to discuss the ollowing three types o ults: Single-line-to-ground (LG) ult Line-to-line (LL) ult Double-line-to-ground (LG) ult For the calculation o ult currents, we shall make the ollowing assumptions: The power system is balanced beore the ult occurs such that o the three sequence networks only the positive sequence network is active. Also as the ult occurs, the sequence networks are connected only through the ult location. The ult current is negligible such that the pre-ult positive sequence voltages are same at all nodes and at the ult location. All the network resistances and line charging capacitances are negligible. All loads are passive except the rotating loads which are represented by synchronous machines. Based on the assumptions stated above, the ulted network will be as shown in Fig. 8. where the voltage at the ulted point will be denoted by and current in the three ulted phases are, and c. We shall now discuss how the three sequence networks are connected when the three types o ults discussed above occur. Fig. 8. Representation o a ulted segment. 8. SNGLE-LNE-TO-GROUND FAULT Let a LG ult has occurred at node k o a network. The ulted segment is then as shown in Fig. 8. where it is assumed that phase-a has touched the ground through an impedance Z. Since the system is unloaded beore the occurrence o the ult we have (8.) c

2 3.35 Fig. 8. Representation o LG ult. Also the phase-a voltage at the ult point is given by Z (8.) ka From (8.) we can write a a (8.3) 3 a a Solving (8.3) we get (8.4) 3 This implies that the three sequence currents are in series or the LG ult. Let us denote the zero, positive and negative sequence Thevenin impedance at the ulted point as Z kk, Z kk and Z kk respectively. Also since the Thevenin voltage at the ulted phase is we get three sequence circuits that are similar to the ones shown in Fig We can then write ka ka ka Z Z kk Z kk kk (8.5) Then rom (8.4) and (8.5) we can write ka ka + ka + ka ( Zkk + Zkk + Zkk ) (8.6) Again since ka ( + + ) Z Z Z 3 we get rom (8.6)

3 3.36 Zkk + Zkk + Zkk + 3Z (8.7) The Thevenin equivalent o the sequence network is shown in Fig Fig. 8.3 Thevenin equivalent o a LG ult. Example 8.: A three-phase Y-connected synchronous generator is running unloaded with rated voltage when a LG ult occurs at its terminals. The generator is rated k, MA, with subsynchronous reactance o. per unit. Assume that the subtransient mutual reactance between the windings is.5 per unit. The neutral o the generator is grounded through a.5 per unit reactance. The equivalent circuit o the generator is shown in Fig We have to ind out the negative and zero sequence reactances. Fig. 8.4 Unloaded generator o Example 8.. Since the generator is unloaded the internal ems are E an. E. E. bn cn Since no current lows in phases b and c, once the ult occurs, we have rom Fig. 8.4

4 3.37 (. +.5) 4. Then we also have n X n. From Fig. 8.4 and (7.34) we get a b E E c bn cn + n + n Thereore a.4 C From (7.38) we can write Z ω(l s + M s ).5. Then rom Fig. 7.7 we have Also note rom (8.4) that E.7.5 an a Z.3333 Thereore rom Fig. 7.7 we get a Z g 3Zn a a Z.5 a (.3.5). 5 Comparing the above two values with (7.37) and (7.39) we ind that Z indeed is equal to ω(l s M s ) and Z is equal to ω(l s + M s ). Note that we can also calculate the ult current rom (8.7) as ( ).3333

5 LNE-TO-LNE FAULT The ulted segment or an L-L ult is shown in Fig. 8.5 where it is assumed that the ult has occurred at node k o the network. n this the phases b and c got shorted through the impedance Z. Since the system is unloaded beore the occurrence o the ult we have (8.8) Fig. 8.5 Representation o L-L ult. Also since phases b and c are shorted we have (8.9) c Thereore rom (8.8) and (8.9) we have C 3 ( ) ( ) a a a a (8.) We can then summarize rom (8.) (8.) Thereore no zero sequence current is inected into the network at bus k and hence the zero sequence remains a dead network or an L-L ult. The positive and negative sequence currents are negative o each other. Now rom Fig. 8.5 we get the ollowing expression or the voltage at the ulted point Z (8.) kb kc Again kb kc kb ( ) + ( ) kb + kb kc + ( a a) + ( a a ) ka ( a a)( ) ka kb kb ka kc kc ka kc kc (8.3)

6 3.39 Moreover since and, we can write ( a a) + a + a (8.4) Thereore combining (8.)-(8.4) we get Z (8.5) ka ka Equations (8.) and (8.5) indicate that the positive and negative sequence networks are in parallel. The sequence network is then as shown in Fig From this network we get (8.6) Zkk + Zkk + Z Fig. 8.6 Thevenin equivalent o an LL ult. Example 8.: Let us consider the same generator as given in Example 8.. Assume that the generator is unloaded when a bolted (Z ) short circuit occurs between phases b and c. Then we get rom (8.9) c. Also since the generator is unloaded, we have. Thereore rom (7.34) we get bn bn an E an. E.5. 5 E cn cn Also since bn cn, we can combine the above two equations to get Then c c C We can also obtain the above equation rom (8.6) as

7 3.4 Also since the neutral current n is zero, we can write a. and b c bn.5 Hence the sequence components o the line voltages are a C Also note that a a which are the same as obtained beore. 8.3 DOUBLE-LNE-TO-GROUND FAULT The ulted segment or a LG ult is shown in Fig. 8.7 where it is assumed that the ult has occurred at node k o the network. n this the phases b and c got shorted through the impedance Z to the ground. Since the system is unloaded beore the occurrence o the ult we have the same condition as (8.8) or the phase-a current. Thereore 3 3 ( + + ) ( + ) + c c 3 c (8.7) Fig. 8.7 Representation o LG ult. Also the voltages o phases b and c are given by kb kc ( b + c ) 3Z Z (8.8)

8 3.4 Thereore ka C ka kb kb 3 ka ka + + ka + kb ( a + a ) kb ( ) a + a kb (8.9) We thus get the ollowing two equations rom (8.9) (8.) ka ka 3 ka ka + kb ka + ka + ka + (8.) kb Substituting (8.8) and (8.) in (8.) and rearranging we get Z (8.) ka ka ka 3 Also since we have + (8.3) + we get The Thevenin equivalent circuit or LG ult is shown in Fig From this igure (8.4) l Zkk + Zkk ( Zkk + 3Z ) Zkk ( Zkk + 3Z ) Zkk + Zkk + Zkk + 3Z The zero and negative sequence currents can be obtained using the current divider principle as Zkk Zkk + Zkk + 3Z (8.5) Z kk + 3Z Zkk + Zkk + 3Z (8.6) Fig. 8.8 Thevenin equivalent o a LG ult.

9 3.4 Example 8.3: Let us consider the same generator as given in Examples 8. and 8.. Let us assume that the generator is operating without any load when a bolted LG ult occurs in phases b and c. The equivalent circuit or this ult is shown in Fig From this igure we can write E bn cn n E n n n n c ( ). 5 + c c Fig. 8.9 Equivalent circuit o the generator in Fig. 8.4 or a LG ult in phases b and c. Combining the above three equations we can write the ollowing vector-matrix orm c Solving the above equation we get b c Hence i. C We can also obtain the above values using (8.4)-(8.6). Note rom Example 8. that Then ( ).3 and Z Z Z.5, Z

10 Now the sequence components o the voltages are Also note rom Fig. 8.9 that and b c. Thereore a a a.5 a ( + ). 99 Ean + n +.5 c a C which are the same as obtained beore. 8.4 FAULT CURRENT COMPUTATON USNG SEQUENCE NETWORKS n this section we shall demonstrate the use o sequence networks in the calculation o ult currents using sequence network through some examples. Example 8.4: Consider the network shown in Fig. 8.. The system parameters are given below: Generator G: 5 MA, k, X X X %, X 7.5% Motor M: 4 MA, k, X X X %, X %, X n 5% Transormer T : 5 MA, k / ky, X % Transormer T : 5 MA, k / ky, X % Transmission line: X X 4. Ω, X 6.5 Ω We shall ind the ult current or when a (a) LG, (b) LL and (c) LG ult occurs at bus-.

11 3.44 Fig. 8. Radial power system o Example 8.4. Let us choose a base in the circuit o the generator. Then the per unit impedances o the generator are: X., X G X G G The per unit impedances o the two transormers are X T X T..75 The MA base o the motor is 4, while the base MA o the total circuit is 5. Thereore the per unit impedances o the motor are X 5..5, X M , M X M X n For the transmission line Thereore X Z base 4Ω 5 4.., L X L X L.5.65 Let us neglect the phase shit associated with the Y/ transormers. Then the positive, negative and zero sequence networks are as shown in Figs Fig. 8. Positive sequence network o the power system o Fig. 8..

12 3.45 Fig. 8. Negative sequence network o the power system o Fig. 8.. Fig. 8.3 Zero sequence network o the power system o Fig. 8.. From Figs. 8. and 8. we get the ollowing Y bus matrix or both positive and negative sequences Y Y bus bus 5 4 nverting the above matrix we get the ollowing Z bus matrix Z Z bus bus Again rom Fig. 8.3 we get the ollowing Y bus matrix or the zero sequence Y bus nverting the above matrix we get Z bus

13 3.46 Hence or a ult in bus-, we have the ollowing Thevenin impedances Z Z.8, Z Alternatively we ind rom Figs. 8. and 8. that.778 Z Z l Z (a) Single-Line-to-Ground Fault: Let a bolted LG ult occurs at bus- when the system is unloaded with bus voltages being. per unit. Then rom (8.7) we get Also rom (8.4) we get ( ) l.84 per unit per unit Also c. From (8.5) we get the sequence components o the voltages as a a a Thereore the voltages at the ulted bus are a b C c a a a (b) Line-to-Line Fault: For a bolted LL ult, we can write rom (8.6) Then the ult currents are.7778 per unit.8 c C Finally the sequence components o bus- voltages are

14 3.47 a a a Hence ulted bus voltages are a b C c a a a..5.5 (c)double-line-to-ground Fault: Let us assumes that a bolted LG ult occurs at bus-. Then Z l eq Hence rom (8.4) we get the positive sequence current as per unit.8 + Z eq The zero and negative sequence currents are then computed rom (8.5) and (8.6) as.8 ( ).9797 per unit per unit ( ) Thereore the ult currents lowing in the line are c C Furthermore the sequence components o bus- voltages are a a a Thereore voltages at the ulted bus are

15 3.48 a b C c a a a.6954 Example 8.5: Let us now assume that a LG ult has occurred in bus-4 instead o the one in bus-. Thereore Also we have Hence X X.667, X Z l eq Also 3.63 per unit Z eq.667 ( ).63 per unit per unit ( ) Thereore the ult currents lowing in the line are c C We shall now compute the currents contributed by the generator and the motor to the ult. Let us denoted the current lowing to the ult rom the generator side by g, while that lowing rom the motor by m. Then rom Fig. 8. using the current divider principle, the positive sequence currents contributed by the two buses are.5.3 per unit per unit.75 ga ma Similarly rom Fig. 8., the negative sequence currents are given as

16 per unit per unit ga ma Finally notice rom Fig. 8.3 that the zero sequence current lowing rom the generator to the ult is. Then we have ga ma.63 per unit Thereore the ult currents lowing rom the generator side are ga gb gc C and those lowing rom the motor are ma mb mc C ga ga ga ma ma ma t can be easily veriied that adding g and m we get given above. n the above two examples we have neglected the phase shits o the Y/ transormers. However according to the American standard, the positive sequence components o the high tension side lead those o the low tension side by 3, while the negative sequence behavior is reverse o the positive sequence behavior. Usually the high tension side o a Y/ transormer is Y-connected. Thereore as we have seen in Fig. 7.6, the positive sequence component o Y side leads the positive sequence component o the side by 3 while the negative sequence component o Y side lags that o the side by 3. We shall now use this principle to compute the ult current or an unsymmetrical ult. Example 8.6: Let us consider the same system as given in Example 8.5. Since the phase shit does not alter the zero sequence, the circuit o Fig. 8.3 remains unchanged. The positive and the negative sequence circuits must however include the respective phase shits. These circuits are redrawn as shown in Figs. 8.4 and 8.5. Note rom Figs. 8.4 and 8.5 that we have dropped the 3α vis-à-vis that o Fig This is because the per unit impedances remain unchanged when reerred to the either high tension or low tension side o an ideal transormer. Thereore the per unit impedances will also not be altered.

17 3.5 Fig. 8.4 Positive sequence network o the power system o Fig. 8. including transormer phase shit. Fig. 8.5 Negative sequence network o the power system o Fig. 8. including transormer phase shit. Since the zero sequence remains unaltered, these currents will not change rom those computed in Example 8.6. Thus ga and ma. 63 per unit Now the positive sequence ult current rom the generator ga, being on the Y-side o the Y/ transormer will lead ma by 3. Thereore ga per unit ma.46 per unit Finally the negative sequence current ga will lag ma by 3. Hence we have Thereore ga per unit ga gb gc C ma.5786 per unit ga ga ga

18 3.5 Also the ult currents lowing rom the motor remain unaltered. Also note that the currents lowing into the ult remain unchanged. This implies that the phase shit o the Y/ transormers does not aect the ult currents. Example 8.7: Let us consider the same power system as given in Example., the sequence diagrams o which are given in Figs. 7.8 to 7.. With respect to Fig. 7.7, let us deine the system parameters as: Generator G : MA, k, X %, X % Generator G : 3 MA, 8 k, X %, X % Generator G 3 : 3 MA, k, X 5%, X 5% Transormer T : 3 MA, Y/ k, X % Transormer T : Three single-phase units each rated MA, 3Y/5 k, X % Transormer T 3 : 3 MA, / k, X % Line B-C: X X 75 Ω, X Ω Line C-D: X X 75 Ω, X Ω Line C-F: X X 5 Ω, X 75 Ω Let us choose the circuit o Generator 3 as the base, the base MA or the circuit is 3. The base voltages are then same as those shown in Fig..3. Per unit reactances are then computed as shown below. 3 Generator G : X.. 3, X.5 8 Generator G : X.. 3, X.656. Generator G 3 : X., X.5 Transormer T : X.. 5 Transormer T : X Transormer T 3 : X.. 75 Line B-C: X X. 565, X Line C-D: X X. 565, X

19 Line C-F: X X. 375, X Neglecting the phase shits o Y/ connected transormers and assuming that the system is unloaded, we shall ind the ult current or a LG ult at bus- (point C o Fig. 7.7). From Figs. 7.8 and 7.9, we can obtain the positive and negative sequence Thevenin impedance at point C as (veriy) X X.73 per unit Similarly rom Fig. 7., the Thevenin equivalent o the zero sequence impedance is Thereore rom (8.7) we get X.4369 per unit.88 per unit ( ) Then the ult current is per unit.