Implementation of FFT by using MATLAB: SIMULINK on Xilinx Virtex-4 FPGAs: Performance of a Paired Transform Based FFT

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1 Inernaional Journal of Advanced Compuer Research (ISS (prin): ISS (online): ) Implemenaion of FFT by using MATLAB: SIMULIK on Xilinx Virex-4 FPGAs: Performance of a Paired Transform Based FFT Ranganadh arayanam 1, Aryom M. Grigoryan 2, Bindu Tushara D 3 Absrac Discree Fourier Transform is principal mahemaical mehod for he frequency analysis and is having wide applicaions in Engineering and Sciences. Because he DFT is so ubiquious, fas mehods for compuing DFT have been sudied exensively, and coninuous o be an acive research. The way of spliing he DFT gives ou various fas algorihms. In his paper, we presen he implemenaion of wo fas algorihms for he DFT for evaluaing heir performance. One of hem is he popular radix-2 Cooley-Tukey fas Fourier ransform algorihm (FFT) [1] and he oher one is he Grigoryan FFT based on he spliing by he paired ransform [2]. We evaluae he performance of hese algorihms by implemening hem on he Xilinx Virex-4 FPGAs [3], by developing our own FFT processor archiecures. Finally we show ha he Grigoryan FFT is working faser han Cooley- Tukey FFT, consequenly i is useful for higher sampling raes. Operaing a higher sampling raes is a challenge in DSP applicaions. Keywords Frequency analysis, fas algorihms, DFT, FFT, paired ransforms. 1. Inroducion In he recen decades DFT has been playing several imporan roles in advanced applicaions such as image compression and reconsrucion in biomedical images, audiology research for analyzing biomedical brain-sem speech signals, sound filering, daa compression, parial differenial equaions, and muliplicaion of large inegers.. Ranganadh, ECE, Associae Professor, Aurora s Scienific and Technological Insiue, Deparmen of Elecronics & Communicaion Engineering, Ghakesar, Hyderabad, A.P. India. A.M. Grigoryan, ECE, The Universiy of Texas a San Anonio, San Anonio, Texas, USA. Tushara Bindu D., ECE, Assisan Professor, Vignan Insiue of Technology & Science, Deshmukhi (V), R.R. Disric, A.P., Hyderabad, India. 72 The fas algorihms for DFT always look for DFT process o be fas, accurae and simple. Fas is he mos imporan [5]. Since he inroducion of he Fas Fourier Transform (FFT), Fourier analysis has become one of he mos frequenly used ool in signal/image processing and communicaion sysems; The main problem when calculaing he ransform relaes o consrucion of he decomposiion, namely, he ransiion o he shor DFT s wih minimal compuaional complexiy. The compuaion of uniary ransforms is complicaed and ime consuming process. Since he decomposiion of he DFT is no unique, i is naural o ask how o manage spliing and how o obain he fases algorihm of he DFT. The difference beween he lower bound of arihmeical operaions and he complexiy of fas ransform algorihms shows ha i is possible o obain FFT algorihms of various speed [2]. One approach is o design efficien manageable spli algorihms. Indeed, many algorihms make differen assumpions abou he ransform lengh [5]. The signal/image processing relaed o engineering research becomes increasingly dependen on he developmen and implemenaion of he algorihms of orhogonal or non-orhogonal ransforms and convoluion operaions in modern compuer sysems. The increasing imporance of processing large vecors and parallel compuing in many scienific and engineering applicaions require new ideas for designing super-efficien algorihms of he ransforms and heir implemenaions [2]. In his paper we presen he implemenaion echniques and heir resuls for wo differen fas DFT algorihms. The difference beween he algorihm developmen lies in he way he wo algorihms use he spliing of he DFT. The wo fas algorihms considered are radix-2 (Cooley-Tukey FFT) and paired ransform [2] (Grigoryan FFT) algorihms. The implemenaion of he algorihms is done on he Xilinx Virex-4 [3] FPGAs. The performance of he wo algorihms is compared in erms of heir sampling raes and also in erms of heir hardware resource uilizaion. Secion II presens he paired ransform decomposiion used in paired ransform in he developmen of Grigoryan FFT. Secion III presens he implemenaion

2 Inernaional Journal of Advanced Compuer Research (ISS (prin): ISS (online): ) echniques for he radix-2 and paired ransform algorihms on FPGAs. Secion IV presens he resuls. Finally wih he Secion V we conclude he work and furher research. 2. Decomposiion algorihm of he fas DFT using paired ransform In his algorihm he decomposiion of he DFT is done by using he paired ransform [2]. Le { x (n) }, n = 0:(-1) be an inpu signal, >1. Then he DFT of he inpu sequence x (n) is X(k) = 1 n0 nk x ( n), k =0:(-1) (1) W Which is in marix form X = [ F ] x (2) where X(k) and x (n) are column vecors, he marix F = F W, is a permuaion of X. nk n, k(0: 1) W diag{[ F ],[ F ],...,[ F ]}[ ][ ] (3) 1 2 k Which shows he applying ransform is decomposed ino shor ransforms F, i = 1: k. Le S be he i domain of he ransform F he se of sequences f over which F is defined. Le (D; ) be a class of uniary ransforms revealed by a pariion. For any ransform F (D; ), he compuaion is performed by using paired ransform in his paricular algorihm. To denoe his ype of ransform, we inroduce paired funcions [2]. Le p, period, and le 1; np (mod ); p, ( n) n = 0: (-1) (4) 0; oherwise. Le L be a non-rivial facor of he number, and / L W = e 2, hen he complex funcion L L1, k p, p, ; L W L p, k / l k0 (5) = 0: / L 1, p o he period 0: -1 is called L-paired funcion [2]. Basing on his paired funcions he complee sysem of paired funcions can be consruced. The oaliy of he paired funcions in he case of =2 r is rn1 {{ ; 0:(2 1), n 0:( r 1)}, 1} n n 2,2 F (6) 73 ow considering he case of = 2 r 1, where 1 is odd, r 1 for he applicaion of he paired ransform. a) The oaliy of he pariions is ( T 1;2, T 2;2, T 4;2,..., T2 r ;2 b) The spliing of F by he pariion is { F,..., F, F } F / 2, / 4 r / 2 1 c) The marix of he ransform can be represened as 2 [ F ] = L n r F Ln n1 1, L. [ ] [W ][ n / r 1 ] Where he [W ] is diagonal marix of he widdle facors. The seps involved in finding he DFT using he paired ransform are given below: 1) Perform he L-paired ransform g = ( x) over he inpu x 2) Compose r vecors by dividing he se of r1 r-1 oupus so ha he firs L elemens g 1,g 2,..,g L compose he firs vecor X 1, he nex L r-2 elemens g Lr- 1+1,..,g Lr-1+Lr-2 compose he second vecor X 2, ec. 3) Calculae he new vecors Y k, k=1:(r-1) by muliplying elemen-wise he vecors X k by he corresponding urned facors 2 / L1 rk 1, W, W,..., W,( L ),(=Lr-k). Take Y r =X r 4) Perform he L r-k -poin DFT s over Y k, k=1: r 5) Make he permuaion of oupus, if needed. 3. Implemenaion Techniques We have implemened various archiecures for radix-2 and paired ransform processors on Virex-4 FPGAs. As here are embedded dedicaed mulipliers [3] and embedded block RAMs [3] available, we can use hem wihou using disribued logic, which economize some of he CLBs [3]. As we are having Exreme DSP slices on Virex-4 FPGAs, o uilize hem and improve speed performance of hese 2 FFTs and o compare heir speed performances. As mos of he ransforms are applied on complex daa, he arihmeic uni always needs wo daa poins a a ime for each operand (real par and complex par), dual por RAMs are very useful in all hese implemenaion echniques. In he Fas Fourier Transform process he buerfly operaion is he main uni on which he speed of he n )

3 Inernaional Journal of Advanced Compuer Research (ISS (prin): ISS (online): ) whole process of he FFT depends. So he faser he buerfly operaion, he faser he FFT process. The adders and subracors are implemened using he LUTs (disribued arihmeic). The inpus and oupus of all he arihmeic unis can be regisered or nonregisered. We have considered he implemenaion of boh embedded and disribued mulipliers; he laer are implemened using he LUTs in he CLBs. The hree consideraions for inpus/oupus are wih nonregisered inpus and oupus, wih regisered inpus or oupus, and wih regisered inpus and oupus. To implemen buerfly operaion for is speed improvemen and resource requiremen, we have implemened boh muliplicaion procedures basing on he availabiliy of number of embedded mulipliers and design feasibiliy. The various archiecures proposed for implemening radix-2 and paired ransform processors are single memory (pair) archiecure, dual memory (pair) archiecure and muliple memory (pair) archiecures. We applied he following wo bes buerfly echniques for he implemenaion of he processors on he FPGAs [3]. 1. One wih Disribued mulipliers, and Exreme DSP slices wih fully pipelined sages. (Bes in case of performance) 2. One wih embedded mulipliers and Exreme DSP slices and one level pipelining. (Bes in case of resource uilizaion) Single memory (pair) archiecure (shown in Figure 2) is suiable for single snapsho applicaions, where samples are acquired and processed hereafer. The processing ime is ypically greaer han he acquisiion ime. The main disadvanage in his archiecure is while doing he ransform process we canno load he nex coming daa. We have o wai unil he curren daa is processed. So we proposed dual memory (pair) archiecure for faser sampling rae applicaions (shown in Figure 3). In his archiecure here are hree main processes for he ransformaion of he sampled daa. Loading he sampled daa ino he memories, processing he loaded daa, reading ou he processed daa. As here are wo pairs of dual por memories available, one pair can be used for loading he incoming sampled daa, while a he same ime he oher pair can be used for processing he previously loaded sampled daa. For furher sampling rae improvemens we proposed muliple memory (pair) archiecure (shown in Figure 4). This is he bes of all archiecures in case of very high sampling rae applicaions, bu in case of hardware uilizaion i uses lo more resources han any oher archiecure. In his model here is a memory se, one arihmeic uni for each ieraion. The advanage of his model over he previous models is ha we do no need o wai unil he end of all ieraions (i.e. whole FFT process), o ake he nex se of samples o ge he FFT process o be sared again. We jus need o wai unil he end of he firs ieraion and hen load he memory wih he nex se of samples and sar he process again. Afer he firs ieraion he processed daa is ransferred o he nex se of RAMs, so he previous se of RAMs can be loaded wih he nex coming new daa samples. This leads o he increased sampling rae. Coming o he implemenaion of he paired ransform based DFT algorihm, here is no complee buerfly operaion, as ha in case of radix-2 algorihm. According o he mahemaical descripion given in he Secion II, he arihmeic uni is divided ino wo pars, addiion par and muliplicaion par. This makes he main difference beween he wo algorihms, which causes he process of he DFT complees earlier han he radix-2 algorihm. The addiion par of he algorihm for 8-poin ransform is shown in Figure 5. The SIMULIK model diagrams for buerfly operaion for boh FFTs are given below. (a) 74

4 Inernaional Journal of Advanced Compuer Research (ISS (prin): ISS (online): ) From he Reference 4 of IEEE paper (8 and 64 poin FFT) we can be able o prove he same wih Xilinx Virex-II Pro FPGAs also. The resuls along wih 128 poin FFT also given in Table Conclusions and Furher Research (b) Figure 1: SIMULIK models (a) for buerfly diagram for =8 Cooley-Tukey FFT (b) for he addiion par (shown in figure 5) of Paired ransform based FFT: Grigorayn FFT. The archiecures are implemened for he 8-poin, 64-poin, and 128-poin ransforms for Virex-4 FPGAs. The radix-2 FFT algorihm is efficien in case of resource uilizaion and he paired ransform algorihm is very efficien in case of higher sampling rae applicaions. In his paper we have shown ha wih our FFT processors archiecures on Xilinx Virex-4 FPGAs he paired ransform based Grigoryan FFT algorihm is faser and can be used a higher sampling raes han he Cooley-Tukey FFT a an expense of high resource uilizaion. Which is also in accordance wih Virex-II Pro FPGAs implemenaion in he reference number 4 IEEE paper, and we can be able o prove i one more ime wih Virex-4 FPGAs also. As par of fuure research we are implemening for = 256 poin FFTs also. We are uilizing he MAC engines explicily of TMS DSP processors for evaluaing on DSP processors also. We are developing a neural daa acquisiion and processing and RF wireless ransmiing VLSI DSP processor where we will be uilizing our Grigoryan FFT processors. 4. Preliminary Implemenaion Resuls Resuls obained on Virex-4 FPGAs: The hardware modeling of he algorihms is done by using Xilinx s sysem generaor plug-in sofware ool running under SIMULIK environmen provided under he Mahworks s MATLAB sofware. The funcionaliy of he model is verified using he SIMULIK Simulaor and he MODELSIM sofware as well. The implemenaion is done using he Xilinx projec navigaor backend sofware ools. Table 1 shows he implemenaion resuls of he wo algorihms on he Virex-4 FPGAs. From he able we can see ha Grigoryan FFT is always faser han he Cooley-Tukey FFT algorihm. Thus paired-ransform based algorihm can be used for higher sampling rae applicaions. In miliary applicaions, while doing he process, only some of he DFT coefficiens are needed a a ime. For his ype of applicaions paired ransform can be used as i generaes some of he coefficiens earlier, and also i is very fas. 75 Figure 2: Single memory (pair) archiecure

5 Inernaional Journal of Advanced Compuer Research (ISS (prin): ISS (online): ) x(0) x1,0 add operaion x(1) x1,1 subrac operaion x(2) x1,2 x(3) x1,3 x(4) x2,0 x(5) x2,2 x(6) x4,0 x(7) x0,0 Figure 5: Figure showing he addiion par of he 8-poin paired ransform based DFT Figure 3: Dual memory (pair) archiecure Acknowledgmen This is o acknowledge Dr. Parimal A. Pael, Dr. Aryom M. Grigoryan of The Universiy of Texas a San Anonio for heir valuable guidance for he firs par of his research series as Mr. arayanam s Maser s Thesis. Mr. arayanam also would like o acknowledge Universiy of Oawa research faciliy References Figure 4: Muliple memory (pair) archiecure (Transform lengh = = 2 n ) (1,2);(3,4);(5,6) ---- (-,-) memory pairs for each ieraion Buerfly uni for each ieraion. [1] James W. Cooley and John W. Tukey, An algorihm for he machine calculaion of complex Fourier Series, Mah. compu. 19, (1965). [2] Aryom M. Grigoryan and Sos S. Agaian, Spli Manageable Efficien Algorihm for Fourier and Hadamard ransforms Signal Processing, IEEE Transacions on, Volume: 48, Issue: 1, Jan.2000 Pages: [3] Virex-4 Pro plaform FPGAs: deailed descripion hp:// a_shees/ds112.pdf. [4] arayanam Ranganadh, Parimal A Pael and Aryom M. Grigoryan, Case sudy of Grigoryan FFT ono FPGAs and DSPs, IEEE proceedings, ICECT [5] Smih, Seven W. "The scienis and engineers guide o digial signal processing." (1997):

6 Inernaional Journal of Advanced Compuer Research (ISS (prin): ISS (online): ) Table 1: Efficien performance of Grigoryan FFT over Cooley-Tukey FFT, on Virex-4 FPGAs. Table showing he sampling raes and he resource uilizaion summaries for boh he algorihms, implemened on he Virex-4 FPGAs. We have uilized Exreme DSP slices in his, which is making us much faser han Virex-II Pro FPGAs. poins Cooley-Tukey radix-2 FFT Grigoryan Radix-2 FFT % improvemen In speed from Cooley-Tukey o Grigoryan FFT Max. freq. o. of Slice s Exreme DSP slices Max. freq Slices o.of Exreme DSP slices Table 2: Efficien performance of Grigoryan FFT over Cooley-Tukey FFT, on Virex-II Pro FPGAs. Table showing he sampling raes and he resource uilizaion summaries for boh he algorihms, implemened on he Virex-II Pro FPGAs. poins Cooley-Tukey radix-2 FFT Grigoryan Radix-2 FFT % improvemen In speed from Cooley-Tukey o Grigoryan FFT Max. freq. mul. Slices Max.Freq. mul slices

7 Inernaional Journal of Advanced Compuer Research (ISS (prin): ISS (online): ) Mr. Ranganadh arayanam is an associae professor in he deparmen of Elecronics & Communicaions Engineering in Aurora s Scienific and Technological Insiue. Mr.arayanam, was a research suden in he area of Brain Sem Speech Evoked Poenials under he guidance of Dr. Hilmi Dajani of Universiy of Oawa,Canada. He was also a research suden in The Universiy of Texas a San Anonio under Dr. Parimal A Pael,Dr. Aryom M. Grigoryan, Dr Sos Again, Dr. CJ Qian,. in he areas of signal processing and digial sysems, conrol sysems. He worked in he area of Brian Imaging in Universiy of California Berkeley. Mr. arayanam has done some advanced learning in he areas of DA compuing, Sring heory and Unificaion of forces, Faser han he speed of ligh heory wih worldwide repued persons and world s op ranked universiies. Mr. arayanam s research ineress include neurological Signal & Image processing, DSP sofware & Hardware design and implemenaions, neuro echnologies. Dr. Aryom M. Grigoryan received he MSs degree in mahemaics from Yerevan Sae Universiy (YSU), Armenia, USSR, in 1978, in imaging science from Moscow Insiue of Physics and Technology, USSR, in 1980, and in elecrical engineering from Texas A&M Universiy, USA, in 1999, and Ph.D. degree in mahemaics and physics from YUS, in In , he was a senior researcher wih he Deparmen of Signal and Image Processing a Insiue for Problems of Informaics and Auomaion, and Yerevan Sae Universiy, aional Academy Science of Armenia. In he was a Research Engineer wih he Deparmen of Elecrical Engineering, Texas A&M Universiy. In December 2000, he joined he Deparmen of Elecrical Engineering, Universiy of Texas a San Anonio, where he is currenly an Associae Professor. He holds wo paens for developing an algorihm of auomaed 3-D fluorescen in siu hybridizaion spo couning and one paen for fas calculaing he cyclic convoluion. He is he auhor of hree books, hree book-chapers, wo paens, and many journal papers and specializing in he heory and applicaion of fas one- and muli-dimensional Fourier ransforms, ellipic Fourier ransforms, ensor and paired ransforms, uniary heap ransforms, design of robus linear and nonlinear filers, image enhancemen, encoding, compuerized 2-D and 3-D omography, processing biomedical images, and image crypography. Ms. Bindu Tushara D. is currenly an Assisan Professor in Vignan Insiue of Technology & Science (VITS). She is a double gold medallis of Jawaharlal ehru Technological Universiy as he bes ougoing suden of he year She has received medals from Governer of Andhara Pradesh. Her ineress are DSP and Wireless Communicaions. 78