Embedded Systems and Software. A Simple Introduction to Embedded Control Systems (PID Control)

Transcription

1 Embedded Sysems and Sofware A Simple Inroducion o Embedded Conrol Sysems (PID Conrol) Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 1

2 Acknowledgemens The maerial in his lecure is adaped from: F. Vahid and T. Givargis, Embedded Sysem Design A Unified Hardware/Sofware Inroducion, John Wiley & Sons, 2002 (Chaper 9) T. Wesco, PID Wihou a PhD hp:// Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 2

3 Conrol Sysem Terminology Conrol physical sysem (plan) oupu By seing plan inpu Examples Cruise conrol, hermosa, disk drive, chemical processes Difficuly due o Disurbance: wind, road, ire, brake; opening/closing door Human inerface: feel good, feel righ Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 3

4 Conrol Sysem Tracking Reference Inpu a.k.a. Se Poin where we wan he oupu o be This how he sysem racks he reference inpu or se poin For example, here he user urned up he hermosa Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 4

5 Conrol Sysem Tracking Reference Inpu a.k.a. Se Poin where we wan he oupu o be This how he sysem racks he reference inpu or se poin For example, here he user urned up he hermosa Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 5

6 Open-Loop Conrol Sysems Plan Physical sysem o be conrolled: car, plane, disk, heaer, Acuaor Device o conrol he plan: hrole, wing flap, disk moor, Conroller Designed produc o conrol he plan Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 6

7 Open-Loop Conrol Sysems Oupu (v ) Wha we are ineresed in: speed, disk locaion, emperaure Reference Inpu / Se Poin (r ) Desired oupu: speed, desired locaion, desired emperaure Disurbance (w ) Unconrollable inpu o he plan imposed by environmen Wind, bumping he disk drive, door opening 7 Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 7

8 Characerisics of Open Loop Conrol Feed-forward conrol Delay in acual change of he oupu Conroller doesn know how well hings are going Simple Bes use for predicable sysems Examples? Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 8

9 Closed Loop Conrol Sysem Error (e = r v ) Disurbance (w ) Se Poin (r ) + Σ u = F e u Plan Model v Conroller Plan Sensor Conrol Law: Plan Model Sysem Model u = F e v +1 = F(v, u, w ) v +1 = F(v, u, w ) Goal: minimize racking error e Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 9

10 Example Closed Loop Conrol Sysem Conrol Law u P r v Plan Model v 0.7 v u w Error (e = r v ) Disurbance (w ) Se Poin (r ) + Σ u = F e u Plan Model v Conroller Plan Sensor Sysem Model v 1 0.7v 0.5P( r Pv 0. 5Pr w v ) w Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 10

11 Model of he Plan Error (e = r v ) Disurbance (w ) Se Poin (r ) + Σ u = F e u Plan Model v Conroller Plan Sensor Couner-inuiively, i may no necessary o (accuraely) model he plan However, even a simple model can be very helpful Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 11

12 Example Model he car speed a + 1 as a linear combinaion of he speed a (i.e., v ) and he hrole a (i.e., u ) v +1 = Av + Bu Nex, experimenally deermine he model parameers A and B. On fla surface a 50 mph, open he hrole o 40 degrees. Then measure he speed afer one ime uni. Assume he speed is 55 mph. Then 55 = 50A + 40B Repea he experimen, bu now sar a 65 mph and wih he hrole a 50 degrees. Assume he resuling speed afer one ime uni is 70.5 mph. Then 70.5 = 65A + 50B One can now solve hese wo equaions for he wo unknowns A and B, o find A = 0.7 and B = 0.5. One can repea he experimen many imes and deermine, say, average values for A and B. (There are more opimum echniques for dealing wih muliple As and Bs). Regardless, we now have model for he car (plan). v +1 = 0.7v + 0.5u Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 12

13 v v v 0.7v 0. u 0.5P( r w Pv 0. 5Pr w Closed-Loop Conrol v ) w Plan model u P r v Conrol Law (feedback) v Pv 0. Pr0 w0 1 5 Consider fixed se poin and fixed disurbance A P, B 0.5Pr0 w0 v 1 Av B v 1 Av0 B v 2 2 Av B B A v AB B Av1 B A 0 0 v 3 Av 2 B AB B B A v A B AB B A A v n n1 n2 vn A v0 A A 1B v n 0 n n1 n P v P P 1 0. Pr w Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 13

14 Tuning Performance: Finding Proper P Error (e = r v ) Disurbance (w ) Se Poin (r ) + Σ u = P e u Plan Model v Conroller Plan Sensor v n v Pv 0. 5Pr0 w0 u Pr0 v 45 n n1 n P v P P 1 0. Pr w To obain convergence requires To avoid oscillaion requires P 0.6 P 3. 4 P P 1. 4 Reduce he effec of iniial condiions (v 0 ), make ( P) as small as possible P Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 14

15 Error (e = r v ) Disurbance (w ) Se Poin (r ) + Σ u = P e u Plan Model v Conroller Plan Sensor v n v Pv 0. 5Pr0 w0 u Pr0 v 45 n n1 n P v P P 1 0. Pr w v P v 0. 5Pr w Seady sae means v ss = v + 1 = v ss ss 0 0 v 0.5P w0 r ss P P To ge v ss as close as possible o r 0, (perfec racking) le P Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 15

16 Tuning Performance: Finding Proper P Error (e = r v ) Disurbance (w ) Se Poin (r ) + Σ u = P e u Plan Model v Conroller Plan Sensor To obain convergence requires 1 To avoid oscillaion requires P 0.6 P P P 1. 4 Reduce he effec of iniial condiions (v 0 ), make ( P) as small as possible P 1. 4 To ge v ss as close as possible o r 0, (perfec racking) le P Finally, pick P 3. 3 sable, fas, good racking, bu some oscillaion Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 16

17 v v v 70 Analyze Conroller Performance 20mph, r 50 mph, w Pv 0. Pr (3.3) v 0. 5(3.3 r ) v 0.95 v u Pr0 u v v 0 P 3.3 Valid range for conroller is 0-45 o. Thus, wih his P, he acuaor sauraes. Speed (mph) Tracking error ~ 8 mph Significan oscillaion Conrol Poin (i.e., ime) Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 17

18 Analyze Conroller Performance Se P = 1 o avoid oscillaion Valid range for conroller is 0-45 o. Thus, wih his P=1, he acuaor does no saurae. 70 Speed (mph) No oscillaion Tracking error ~ 20 mph Conrol Poin (i.e., ime) Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 18

19 Analyzing he Conroller 70 Se poin (where we wan o be) 60 Speed (mph) P = 1.0 P = 2.5 P = Conrol Poin (i.e., ime) Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 19

20 v v v v 20 mph, r0 50 mph, w0 0 Closed-Loop Performance Pv 0. Pr (3.3) v 0. 5(3.3 r ) 1.95 v w 0 0 Speed (mph) P = 3.3, W = - 5 Change is 5 mph compared o = 33 mph for open-loop conrol 20 P = 3.3, W =+5 P = 3.3, W = Conrol Poin (i.e., ime) Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 20

21 General Conrol Sysem Objecive Causing oupu o rack a reference even in he presence of Measuremen noise Model error Disurbances Merics Sabiliy Oupu remains bounded Performance How well an oupu racks he reference Disurbance rejecion Robusness Abiliy o olerae modeling error of he plan Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 21

22 Performance (generally speaking) Rise ime Time i akes from 10% o 90% Peak ime Overshoo Percenage by which Peak exceed final value Seling ime Time i akes o reach 1% of final value Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 22

23 Difficul May need o be done firs Plan is usually on coninuous ime No discree ime. For example, car speed coninuously reacs o hrole posiion, no a discree inerval Sampling period mus be chosen carefully o ensure nohing ineresing happens in beween sampling inervals Plan is usually non-linear Plan Modeling For example, shock absorber response may need o be 8 h order differenial equaion Ieraive developmen of he plan model and conroller Have a plan model ha is good enough Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 23

24 Conroller Design: P Error (e = r v ) Disurbance (w ) Se Poin (r ) + Σ u = P e u Plan Model v Conroller Plan Sensor Proporional conrol - muliplies he racking error wih a consan P u P r0 v Closed-loop model wih linear plan v Pv 0. Pr0 w0 1 5 P affecs Sabiliy Tracking Disurbance rejecion Large P can lead o overshoo and oscillaion Make P large o reduce racking error Make P large o improve disurbance rejecion Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 24

25 Conroller Design: PD Proporional and Derivaive conrol u u - P conrol, and also consider error over ime v D r v r 1 v1 De e P r Pe Inuiively Wan o push more if error is no reducing fas enough Wan o push less if error is reducing really fas 1 Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 25

26 v u v v v 0. 5u w Plan model Pe PD Conroller De e 1 e r v Conrol Law (feedback) 0.7 v 0. Pr v Dr v r 1 v w 0.7 v 0. 5P Dv 0.5Dv 1 0.5P Dr 0. Dr w Seady sae means v ss = v + 1 = v Assume reference inpu and disurbance are consan, hen he seady-sae speed is v ss 0.5P r P 0 Does no depend on D P can be se for bes racking and disurbance conrol Then D can be se o conrol ransien behavior Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 26

27 PD Conrol Example Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 27

28 Proporional and Inegral conrol Inuiively u u Conroller Design: PI Sum (inegrae) error over ime, and use his o push P conrol, and also inegrae (sum) error v Ir v r 1 v 1 Ie e e P r Pe 1 2 Ensure ha sysem reaches desired seady sae, evenually P conrols disurbance, I conrols seady sae convergence and convergence rae Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 28

29 Conroller Design: PID Proporional, Inegral and Derivaive conrol u u P r Pe - use all 3 ypes of conrol v Ir v r 1 v 1 Dr v r 1 v 1 Ie e e De e Inuiively P considers curren error, conrols disurbance I conrols long-erm error, conrols seady sae convergence and convergence rae D considers how error is changing, conrols ransien response Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 29

30 Examples Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 30

31 Applicaion of PID Conrol More han 90% of all conrollers used in process indusries are PID conrollers. A ypical chemical plan has 100s or more PID conrollers. PID conrollers are widely used in: Chemical plans Oil refineries Pharmaceuical indusries Food indusries Paper mills Elecronic equipmens Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 31

32 Off-The-Shelf PID Conrollers There are many off-he-shelf PID conrollers available Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 32

33 Block Diagram View of PID Conroller Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 33

34 Anoher Block Diagram View of PID Conroller Se desired inpu Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 34

35 Anoher Block Diagram View of PID Conroller Compare acual oupu agains se poin Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 35

36 Anoher Block Diagram View of PID Conroller Use par of he error signal Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 36

37 Anoher Block Diagram View of PID Conroller Use sum of he previous errors Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 37

38 Anoher Block Diagram View of PID Conroller Use rae of change of errors Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 38

39 Anoher Block Diagram View of PID Conroller Updae he process, and repea Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 39

40 Sidebar: Analog PID Conroller Inegral Proporional Summer Derivaive Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 40

41 PID Pseudo Code previous_error = 0 inegral = 0 sar: ge acual_posiion error = sepoin - acual_posiion inegral = inegral + error*d derivaive = (error - previous_error)/d oupu = P*error + I*inegral + D*derivaive previous_error = error wai(d) goo sar Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 41

42 Sofware Coding Main funcion loops forever, during each ieraion Read plan oupu sensor (may require ADC) Read curren desired reference inpu (se poin) Call a rouine PidUpdae, o deermine acuaor value Se acuaor value (may require DAC) Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 42

43 Sofware Coding u Pe I e e e De e Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 43

44 Compuaion u Pe I e e e De e Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 44

45 Analyically deriving P, I, D may no be possible E.g., plan no is no available, or o cosly o obain Ad hoc mehod for geing reasonable P, I, D Sar wih a small P, I = D = 0 PID Tuning Increase D, unil seeing oscillaion, hen reduce D a bi Increase P, unil seeing oscillaion, hen D a bi Increase I, unil seeing oscillaion Ierae unil one can change anyhing wihou excessive oscillaion Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 45

46 Pracical Issues wih Compuer-Based Conrol Quanizaion Overflow Aliasing Compuaion Delay Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 46

47 Quanizaion & Overflow Quanizaion E.g., can sore 0.36 as 4-bi fracional number Can only sore 0.75, 0.59, 0.25, 0.00, -0.25, -050,-0.75, Choose 0.25 Resuls in quanizaion error of 0.11 Sources of quanizaion error Operaions, e.g., 0.50*0.25=0.125 Can use more bis unil inpu/oupu o he environmen/memory ADC resoluion Overflow Can sore = 1.25 as 4-bi fracional number Soluions Use fix-poin represenaion/operaions carefully Time-consuming Use floaing-poin co-processor Cosly Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 47

48 Volage Aliasing Example The poins below are he samples from a sine wave Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 48

49 Volage Reconsrucion of he sine wave Aliasing Example Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 49

50 Volage Bu why no his reconsrucion? Aliasing Example Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 50

51 Volage Aliasing Example Boh (an many ohers) are valid reconsrucions if we don exclude higher frequencies In oher words, if we don eliminae (filer ou) high frequencies, heir samples become undisinguishable from low frequency samples. The high frequencies alias as low frequency signals. Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 51

52 Aliasing Example Sampling a 2.5 Hz (period = 0.4 s) he following signals are indisinguishable y( ) sin 6 y( ) sin Frequency f = 3 Hz Frequency f = 0.5 Hz In fac, wih sampling frequency of 2.5 Hz one can only correcly sample signal below he Nyquis frequency 2.5/2 = 1.25 Hz. Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 52

53 Inheren delay in processing Acuaion occurs laer han expeced Need o characerize implemenaion delay o make sure i is negligible Hardware delay is usually easy o characerize Synchronous design Sofware delay is harder o predic Should organize code carefully so delay is predicable and minimized Wrie sofware wih predicable iming behavior (be like hardware) Time Trigger Archiecure Compuaion Delay Synchronous Sofware Language and/or RTOS Embedded Sysems and Sofware, ECE:3360. The Universiy of Iowa, 2016 Slide 53