Simplified Parallel Architecture for LTE-A Turbo Decoder Implemented on FPGA

Transcription

1 Advances n Crcuts, Systems, Sgnal Prcessng and Telecmmuncatns Smplfed Parallel Archtecture fr LTE-A Turb Decder Implemented n FPGA CRISTIAN ANGHEL, CONSTANTIN PALEOLOGU Telecmmuncatns Department Unversty Pltehnca f Bucharest Iulu Manu, 1-3, Bucharest ROMANIA {canghel, pale}@cmm.pub.r Abstract: - Ths paper descrbes a turb decder fr 3GPP Lng Term Evlutn Advanced (LTE-A) standard, usng a Max LOG MAP algrthm, mplemented n Feld Prgrammable Gate Array (FPGA). Takng advantage f the quadratc permutatn plynmal (QPP) nterleaver prpretes and cnsderng sme FPGA blck memry characterstcs, a smplfed parallel decdng archtecture s prpsed. It shuld be used especally fr large data blcks, when hgh decdng latency s ntrduced by the seral decdng. The parallelzatn factr N s usually a pwer f, the maxmum cnsdered value beng 8. The btaned parallel decdng latency s N tmes lwer than the seral decdng latency. Wth the cst f very lw latency added t ths value, the parallel decdng perfrmances are smlar wth the seral decdng nes. The nvelty f the prpsed parallel archtecture s that nly ne nterleaver s used, ndependently f the N value. Key-Wrds: - LTE-A, turb decder, Max LOG MAP, parallel archtecture, FPGA 1 Intrductn The dscussns arund the channel cdng thery were ntense n the last decades, but even mre nterest arund ths tpc was added nce the turb cdes were fund by Berru, Glaveux, and Thtmajshma [1][][3]. At the begnnng f ther exstence, after prvng the btaned decdng perfrmances, the turb cdes were ntrduced n dfferent standards as recmmendatns, whle cnvlutnal cdes were stll mandatry. The reasn behnd ths decsn was especally the hgh cmplexty f turb decder mplementatn. But the turb cdes became mre attractve nce the supprts fr dgtal prcessng, lke Dgtal Sgnal Prcessr (DSP) r Feld Prgrammable Gate Array (FPGA), were extended mre and mre n terms f prcessng capacty. Nwadays the chps nclude dedcated hardware acceleratrs fr dfferent types f turb decders, but ths apprach makes them standard dependent. The Thrd-Generatn Partnershp Prject (3GPP) [4] s an rganzatn, whch adpted early these advanced cdng technques. Turb cdes were standardzed frm the frst versn f Unversal Mble Telecmmuncatns System (UMTS) technlgy, n The next UMTS releases (after Hgh Speed Packet Access was ntrduced) added supprt fr new and nterestng features, whle turb cdng remaned stll unchanged. Sme mdfcatns were ntrduced by the Lng Term Evlutn (LTE) standard [5][6], nt sgnfcant as vlume, but mprtant as cncept. Whle keepng exactly the same cdng structure as n UMTS, 3GPP prpsed fr LTE a new nterleaver scheme. An UMTS dedcated turb decdng scheme s presented n [7]. Due t the new LTE/ LTE-A nterleaver, the decdng perfrmances are mprved cmpared wth the nes crrespndng t UMTS standard. Mrever, the new LTE nterleaver prvdes supprt fr the parallelzatn f the decdng prcess nsde the algrthm, takng advantage n the man prncple ntrduced by turb decdng,.e., the usage f extrnsc values frm ne turb teratn t anther. The parallel decdng represents ne sftware adaptatn requested by the hgh data rates, whle addtnal hardware changes are als prpsed [8]. There are many parallel decdng archtectures prpsed n the lterature n the last years. The btaned results are evaluated n axes. The frst ne s the decdng perfrmances degradatn ISBN:

2 Advances n Crcuts, Systems, Sgnal Prcessng and Telecmmuncatns ntrduced by the parallel methd cmpared wth the seral decdng scheme and the secnd ne s the amunt f resurces needed fr such parallel archtecture mplementatn. A frst set f parallel archtectures s descrbed n [9]. Startng frm the classcal methd f mplementng the Maxmum A Psterr (MAP) algrthm,.e., gng t trells nce t cmpute the Frward State Metrcs (FSM) and then twce t cmpute the Backward State Metrcs (BSM) and als the Lg Lkelhd Rats (LLR), several slutns t reduce the decdng latency f K clck perds per sem-teratn, where K s the data blck length, are ntrduced. The frst ne reduces the decdng tme t half (nly K) by startng smultaneusly the BSM and FSM cmputatn. After cmputng half f these values, LLR blcks start wrkng n parallel, the nterleaver blck beng als dubled. Anther prpsed scheme elmnates the need fr the secnd nterleaver but ncreases the decdng tme wth K/ cmpared wth the prevus ne, a ttal decdng latency f 3K/ clck perds beng btaned. A secnd set f parallel archtectures takes advantage f the Quadratc Permutatn Plynmal (QPP) nterleaver algebrac-gemetrc prpertes, as descrbed n [10][11]. Here effcent hardware mplementatns f the QPP nterleaver are prpsed, but the parallelzatn factr N represents als the number f used nterleavers n the prpsed archtectures. A thrd apprach cnsst n usng a flded memry t stre smultaneusly all the values needed fr parallel prcessng [1]. But fr ths knd f mplementatn the man challenge s t crrectly dstrbute the data t each decdng unt nce a memry lcatn cntanng all N values was read. Mre precsely, the N decdng unts wrkng n parallel were wrtng ther data n a cncatenated rder t the same lcatn, but when the nterleaved readng s takng place, these values are nt gng n the same rder t the same decdng unt, but nstead they shuld be redstrbuted. T slve ths, an archtecture based n Batcher srtng netwrks s prpsed. But als n ths apprach, N nterleavers are needed t generate all the nterleaved addresses that nput the master netwrk. In ths paper, we ntrduce als a flded memry based apprach, but the man dfference cmparng wth the already exstent slutns descrbed abve s that ur prpsed slutn uses nly ne nterleaver. Addtnally, wth sme multplexng and demultplexng blcks, the parallel archtecture remans clse t the seral ne, nly the Sft Input Sft Output (SISO) decdng unt beng nstantated N tmes. The blck memres numbers and dmensns are unchanged between the tw blck schemes. In terms f decdng perfrmances, wth the cst f a small verhead added, the perfrmances f the seral and parallel decdng archtectures are kept smlar. The paper s rganzed as fllws. Sectn descrbes the LTE cdng scheme wth the new ntrduced QPP nterleaver. Sectn 3 presents the decdng algrthm. In Sectn 4, there are dscussed the mplementatn slutns and the prpsed decdng schemes, fr bth seral and parallel decdng. Sectn 5 presents thrughput and speed results btaned when targetng a XC5VFX70T [13] chp n Xlnx ML507 [14] bard; t als prvdes smulatn curves cmparng the results btaned when usng seral decdng, parallel decdng, and parallel decdng wth verlap. Sectn 6 cntans the cnclusns f ths wrk. LTE Cdng Scheme The cdng scheme presented n 3GPP LTE specfcatn s a classc turb cdng scheme, ncludng tw cnsttuent encders and ne nterleaver mdule. It s descrbed n Fg. 1. One can bserve at the nput f the LTE turb encder the data blck C k. The K bts crrespndng t ths blck are sent as systematc bts at the utput n the steam X k. In the same tme, the data blck s prcessed by the frst cnsttuent encder resultng party bts Z k, whle the nterleaved data blck Ck s prcessed by the secnd cnsttuent encder resultng party bts Z k. Cmbnng the systematc bts and the tw streams f party bts, the fllwng sequence s btaned at the utput f the encder: X 1, Z 1, Z 1, X, Z, Z,, X K, Z K, Z K. At the end f the cdng prcess, n rder t drve back the cnsttuent encders t the ntal state, the swtches frm Fg. 1 are mved frm pstn A t B. Snce the fnal states f the tw cnsttuent encders are dfferent, dependng n the nput data blck, ths swtchng prcedure wll generate tal bts fr each encder. These tal bts have t be transmtted tgether wth the systematc and party bts resultng the fllwng fnal sequence: X K+1, Z K+1, X K+, Z K+, X K+3, Z K+3, X K+1, Z K+1, X K+, Z K+, X K+3, Z K+3. As mentned befre, the nvelty ntrduced by the LTE standard n terms f turb cdng s the nterleaver mdule. The utput bts are rerganzed usng: ISBN:

3 Advances n Crcuts, Systems, Sgnal Prcessng and Telecmmuncatns ( ) X k ( ) Z k 1 ( Z k ) Fg.. LTE turb decder. π( ) Fg. 1. LTE CTC encder. C = C, = 1,,..., K, (1) where the nterlvng functn π appled ver the utput ndex s defned as = 1 + () π( ) ( f f ) md K. The nput blck length K and the parameters f 1 and f are prvded n Table n [5]. 3 Decdng Algrthm The LTE turb decdng scheme s depcted n Fg.. The tw Recursve Systematc Cnvlutnal (RSC) decders use n thery the MAP algrthm. Ths classc algrthm prvdes the best decdng perfrmances, but t suffers frm very hgh mplementatn cmplexty and t can lead t large dynamc range fr ts varables. Fr these reasns, the MAP algrthm s used as a reference fr targeted decdng perfrmances, whle fr real mplementatn new sub-ptmal algrthms have been studed: Lgarthmc MAP (Lg MAP) [15], Maxmum Lg MAP (Max Lg MAP), Cnstant Lg MAP (Cnst Lg MAP) [16], and Lnear Lg MAP (Ln Lg MAP) [17]. Fr the prpsed decdng scheme, the Max Lg MAP algrthm s selected. Ths algrthm reduces the mplementatn cmplexty and cntrls the dynamc range prblem wth the cst f acceptable perfrmances degradatn, cmpared t classc MAP algrthm. The Max Lg MAP algrthm keeps frm Jacb lgarthm nly the frst term,.e., max*( x, y) = ln(e + e ) = x max( x, y) + ln(1 + e ) max( x, y). y y x (3) The LTE turb decder trells dagram cntans 8 states, as depcted n Fg. 3. Each dagram state permts nputs and utputs. The branch metrc between the states S and S j s ( X ) X ( j) ( Z ) Z ( j) γ = V, +,, (4) j k k where X(,j) represents the data bt and Z(,j) s the party bt, bth asscated t ne branch. Als s the LLR fr the nput party bt. When ( Z k ) SISO 1 decder s taken nt dscussn ths nput, whle fr SISO t becmes LLR s ( Z k ) ( Z k ) ( ) ; V(X k )=V 1 (X k ) represents the sum between X k and W(X k ) fr SISO 1 and V(X k )=V (X k ) represents the nterleaved versn f the dfference and W(X k ) fr SISO. In Fg., between 1 W(X k ) s the extrnsc nfrmatn, whle ( ) and 1 X k are the utput LLRs generated by the tw SISOs. In the LTE turb encder case, there are 4 pssble values fr the branch metrcs between states n the trells: γ = 0 0 γ = V 1 γ = ( Zk ) ( X ) ( Z ) γ = V +. k k (5) The decdng prcess s based n gng frward and backward thrugh the trells. ISBN:

4 Advances n Crcuts, Systems, Sgnal Prcessng and Telecmmuncatns metrc fr the state α k S wth 0 k K 1 and 0 7. The frward recursn s ntalzed wth α 0 ( S0 ) = 0 and α 0 ( S ) = 0, > 0. Startng frm the stage k=1 and cntnung thrugh the trells untl the last stage k=k, the un-nrmalzed frward metrcs are gven by S at the stage k s ( ) ( S ) = { 1 ( S 1) ( S ) + } ˆ α max ( α γ ),( α γ ), k j k j k j (8) Fg. 3. LTE turb cder trells. 3.1 Backward recursn The trells s cvered backward and the cmputed metrcs are stred n a nrmalzed frm at each nde f the trells. These stred values are used fr the LLR cmputatn at the trells frward recursn. The backward metrc fr the S state at the k th stage s β k ( S ), where k K + 3 and 0 7. The backward recursn s ntalzed wth β K + 3 ( S0 ) = 0 and β K + 3 ( S ) = 0, > 0. Startng frm the stage k=k+ and cntnung thrugh the trells untl stage k=, the cmputed backward metrcs are { } ( S ) + ( S ) + ( S ) ˆ β = max ( β + γ ),( β + γ ), k k j j k j j where ( S ) ˆk (6) β represents the un-nrmalzed metrc and S j1 and S j are the tw states frm stage k+1 cnnected t the state S frm stage k. After the cmputatn f ˆk β ( S 0 ) value, the rest f the backward metrcs are nrmalzed as ( S ) ˆ ( S ) ˆ ( S ) β = β β (7) k k k and then stred n the dedcated memry. 3. Frward recursn Durng the frward recursn, the trells s cvered n the nrmal drectn, ths prcess beng smlar wth the ne specfc fr Vterb algrthm. In rder t allw the cmputatn f the current stage (k) metrcs, nly the frward metrcs frm the last stage (k 1) have t be stred. The frward 0 where S 1 and S are the tw states frm stage k 1 cnnected t the state S j frm stage k. After the cmputatn f ˆk α ( S 0 ) value, the rest f the frward metrcs are nrmalzed as ( S ) ( S ) ( S ) α = ˆ α ˆ α. (9) k k k Because the frward metrcs α are cmputed fr the stage k, the decdng algrthm can btan n the same tme a LLR estmated fr the data bts X k. Ths LLR s fund the frst tme by cnsderng that the lkelhd f the cnnectn between the state S at stage k 1 and the state S j at stage k s ( j) 1 ( S ) + ( S ) λ, = α + γ β. (10) k k j k j The lkelhd f havng a bt equal t 1 (r 0) s when the Jacb lgarthm f all the branch lkelhds crrespnds t 1 (r 0) and thus: ( X ) λ ( j) λ ( j) = max {, } max {, }, k k k ( S S j ): X = 1 ( S S j ): X = 0 0 (11) where max peratr s recursvely cmputed ver the branches, whch have at the nput a bt f 1 ( S S ) : X 1 ( S S ) : X = 0. { j = } r a bt 0 { j } 4 Prpsed Decdng Scheme 4.1 Seral Decder Blck Scheme Frm the theretcal decdng scheme depcted n Fg. t can be ntced that SISO decder starts wrkng nly after SISO 1 decder fnshes ts jb and vce-versa, the usage f prevusly btaned extrnsc values beng the man prncple f the turb decdng. ISBN:

5 Advances n Crcuts, Systems, Sgnal Prcessng and Telecmmuncatns W(Xk) W(Xk) memry (Xk) memry (Zk) memry + ( ) X k ( ) Z k V1(Xk) memry 1 V1(Xk) 1 V(X k) RSC (SISO1 r SISO) 1 ( X ) 1 k + V(Xk) memry Wrte nrmal Read nterleaved V(Xk) Interleaver V(X k) memry (Z k) memry ( Z k ) (X k) memry Wrte nterleaved Read nrmal Denterleaver (Xk) memry + Xˆ k Fg. 4. Prpsed seral turb decder blck scheme. Als, all the prcessng s based n cmplete data blcks snce the nterleaver r denterleaver prcedures shuld be appled n between. It results that the SISOs are decdng data n nnverlapped tme wndws, s nly ne SISO unt can be used t prcess n a tme-multplexed manner, as ne can bserve n Fg. 4, where a seral decder blck scheme based n the prevus wrk presented n [18] fr a WMAX CTC decder s descrbed. The memry blcks are used fr strng data frm ne sem-teratn t anther and frm ne teratn t anther. The dtted-lne memry blcks are vrtual memres added nly t ease the understandng f the ntrduced ntatns. Als, t shuld be mentned that the Interleaver and Denterleaver blcks are n fact the same, ncludng a blck memry called ILM (Interleaver Memry) and an nterleaver. The ILM s the new apprach ntrduced by the authr cmpared wth the prevus seral mplementatn presented n [19] and the gal s t prepare the archtecture fr parallel decdng als. The memry s wrtten wth the nterleaved addresses each tme a new data blck s receved. The values are then used as read addresses (when nterleaver prcess s ngng) r as wrte addresses (when denterleaver prcess s ngng). Ths ILM, tgether wth the 3 memres frm the left sde f the pcture (fr the nput data) are swtched-buffers, allwng new data t be wrtten whle the prevus ne s stll under decdng prcess. The scheme depcted n Fg. 4 wrks as fllws. SISO 1 reads the memry lcatns crrespndng vectrs. The readng prcess t V 1 (X k ) and ( Z k ) s perfrmed frward and backward and t serves the frst sem-teratn. At the end f ths prcess, SISO reads frward and backward frm the memry blcks crrespndng t V (X k ) and ( Z k ) vectrs n rder t perfrm the secnd semteratn. The vectr V 1 (X k ) s btaned by addng the nput vectr wth the extrnsc nfrmatn vectr W(X k ). Whle readng these memres, SISO 1 starts the decdng prcess. At the utput, the LLRs are avalable and perfrmng the subtractn between them and the delayed extrnsc values already read frm W(X k ) memry, the vectr V (X k ) s cmputed and then stred nt ts crrespndng memry n a nrmal rder. The nterleavng prcess s started (the ntally wrtten ILM s read nw n nrmal rder, s that nterleaved read address fr V (X k ) are btaned) and the re-rdered LLRs V (X k ) are avalable, the crrespndng values fr the 3 tal bts X K+1, X K+, X K+3 beng added at the end f ths sequence. The secnd sem-teratn s ngng. The same SISO unt s used, but readng ths tme data nputs frm the ther memry blcks. As ne can see frm Fg. 4, tw swtchng mechansms are ncluded n the scheme. When n pstn 1, the memry blcks fr V 1 (X k ) and are used, whle n pstn the memry ( ) Z k blcks fr V (X k ) and ( Z k ) becme actve. At the utput f the SISO unt, after each semteratn, K LLRs are btaned. The nes crrespndng t the secnd sem-teratn are memry (the ILM utput, stred n the whch was already avalable fr the V (X k ) nterleaver prcess, s used as wrtng address fr memry, after a delay s added). Readng n a nrmal rder memry and als V (X k ) memry prvdes nputs fr W(X k ) memry and n the same tme allws a new semteratns t start fr SISO 1. S the W(X k ) memry update s made n the same tme wth a new semteratn start. Fg. 5 depcts a tme dagram fr the seral turb decdng and the gray clred ntervals ISBN:

6 Advances n Crcuts, Systems, Sgnal Prcessng and Telecmmuncatns descrbe W(X k ) memry wrtng. One can bserve that the upper 4 memres n the pcture are swtched-buffers, s they are wrtten whle the prevus data blck s stll prcessed. In the pcture R stands fr Read, W represents Wrte, (K 1:0) s the backward trells run, (0:K 1) s the frward trells run and IL means nterleaved read (fr nterleaver prcess) r wrte (fr denterleaver prcess). In rder t be able t handle all the data blck dmensns, the used memry blcks have 6144 lcatns (ths s the maxmum data blck length), except the nes strng the nput data fr RSCs, whch have lcatns, ncludng here als the tal bts. Each memry lcatns s 10 bts wde, the frst bt beng used fr the sgn, the next 6 bts representng the nteger part and the last 3 bts ndcatng the fractnal part. Ths frmat was decded studyng the dynamc range f the varables (fr the nteger part) and the varatns f the decdng perfrmances (fr the fractnal part). The cnsttuent mdules f the SISO blck are the nes presented n Fg. 6. One can ntce bth the un-nrmalzed metrc cmputng blcks ALPHA (frward) and BETA (backward), and the transtn metrc cmputng blck GAMMA, whch n addtn ncludes the nrmalzatn functn (subtract the metrcs fr the frst state frm all the ther metrcs). The L blck cmputes the utput LLRs, whch are nrmalzed by the NORM blck. The MUX- MAX blck selects nputs crrespndng t the frward r backward recursn and cmputes the maxmum functn. The MEM BETA blck stres the backward metrcs, whch are cmputed befre frward metrcs. The metrc nrmalzatn s requred t preserve the dynamc range. V 1 / V ( Zk ) / ( Zk ) Fg. 6. Prpsed SISO blck scheme. Wthut nrmalzatn, the frward and backward metrc wdth shuld be wder n rder t avd saturatn, whch means mre memry blcks, mre cmplex arthmetc (.e., mre used resurces), and lwer frequency (as an verall cnsequence). Hence, reducng the lgc levels by elmnatng the nrmalzng prcedure des nt ncrease the system perfrmances. The ALPHA, BETA, and GAMMA blcks are mplemented n a dedcated way. Each metrc crrespndng t each state s cmputed separately, nt usng the same functn wth dfferent nput parameters. Cnsequently, 16 equatns shuld be used fr transtn metrc cmputatn ( pssble transtns fr each f the 8 states frm a stage). In fact, nly 4 equatns are needed [as ndcated n (5)]; mrever, frm these 4 equatns ne f them leads t zer value, s that the cmputatnal effrt s mnmzed fr ths mplementatn slutn. The nterleaver mdule s used bth fr nterleavng and denterleavng. The nterleaved ndex s btaned based n a mdfed frm f (),.e., ( ) ( ) π = {[ f + f md K ] }md K. (1) 1 1 / SISO MODULES frm ARCHITECTURE Fg. 5. Tme dagram fr seral turb decder. In rder t btan bth functns, ether the nput data s stred n the memry n natural rder and then t s read n nterleaved rder, ether the nput data s stred n the nterleaved rder and then t s read n natural rder. The nterleaved ndex cmputatn s perfrmed n three steps. Frst the value fr ( f1 + f ) md K s cmputed. Ths partal result s multpled by natural rder ndex and then a new mdul K functn s appled. In the frst stage f ths prcess, the remark that the frmula s ncreased wth f fr cnsecutve values f ndex s used. Ths way, a regster value s ncreased wth f at each new ndex. If the resulted value s bgger than K, the value f K s subtracted frm the regster value. Ths ISBN:

7 Advances n Crcuts, Systems, Sgnal Prcessng and Telecmmuncatns prcessng s ne clck perd lng, ths beng the reasn why data s generated n a cntnuus manner. 4. Parallel Decder Blck Scheme The prpsed parallel archtecture s smlar t the seral ne descrbed n Fg. 4, nly that the RSC SISO mdule s nstantated N tmes n the scheme. We prpse an archtecture that cncatenates the N values frm the N RSCs and pnts always at the same memry lcatn, fr all the memres n the scheme. S nstead f havng K lcatns wth 10 bts per lcatn as n the seral archtecture, n the parallel ne each memry cntans K/N lcatns wth 10N bts per lcatns. The man advantage ntrduced by the prpsed seral archtecture s the fact that the nterleaver blck wrks nly nce, befre the decdng tself takng place. The ILM memry s wrtten when a new data blck s receved, whle the prevus ne s stll under decdng. Ths apprach allws a smplfed parallel scheme way f wrk. Knwng the parallelzatn factr N, the ILM memry can be prepared fr the parallel prcessng that fllws. Mre precsely, the ILM memry wll have K/N lcatns, N values beng wrtten at each lcatn. As mentned n [0], a Vrtex 5 blck memry can be cnfgured frm (3k lcatns x 1 bt) t (51 lcatns x 7 bts). In the wrst case scenar when K=6144, based n the N values and keepng the stred values n 10 bts as prevusly mentned, the parallel ILM memry can be (768 lcatns x 80 bts), (1536 lcatns x 40 bts), (307 lcatns x 0 bts), r (6144 lcatns x 10 bts), s stll nly BRAMs are used, as n the case f seral ILM. Fg. 8. Vrtual parallel nterleaver. Fg. 7 descrbes the way ILM wrks. As ne can bserve, whle wrtng prcedure, each ndex frm 0 t K 1 generates a crrespndng nterleaved values. These nterleaved values are wrtten n a nrmal rder n ILM. The frst K/N crrespndng nterleaved values ccupy the frst pstn n each memry lcatns. The secnd K/N values are placed n the secnd pstn f each lcatn, and s n. In rder t perfrm ths prcedure, a true dual prt BRAM s used. Each tme a new pstn n lcatn n s wrtten, the cntent f lcatn n+1 s als read frm the memry, s that the next clck perd the next nterleaved value t be added t the already exstng cntent at that lcatn. When the nterleaver functn s needed durng a semteratn, the ILM s read n a nrmal way, s that the N nterleaved values frm ne lcatn t represent the readng addresses fr V (X k ) memry. But the QPP prpretes guarantee that the N values that shuld be read n the nterleaved way frm the memry are placed at the same memry lcatn, nly that ther pstns shuld be re-arranged befre beng sent t the crrespndng RSCs. Fr smplfyng the representatn, the case f K=40 and N=8 s exemplfed n Fg. 8. On the left ne can see the cntent f V (X k ) memry. Each clumn represents the utupts f ne f the N RSC SISOs. On the rght there s descrbed the cntent f ILM memry. The mnmum values frm each lne f ILM (grey clred crcle n fgure) represents the lne address fr V (X k ) memry. Then, usng a rerderng mdule mplemented wth multplexers and de-multplexers, each pstn frm the read lne s sent t ts crrespndng SISO. Fr example, pstn b frm the frst read lne (ndex 5) s sent t SISO f, whle pstn b frm the secnd read lne (ndex 8) s sent t SISO d. The same prcedure apples als fr denterleaver prcess, nly that the Fg. 7. ILM memry wrtng prcedure. ISBN:

8 Advances n Crcuts, Systems, Sgnal Prcessng and Telecmmuncatns MODULES frm ARCHITECTURE Fg. 10. a) nn verlapng splt; b) verlappng splt. SISO a SISO b Fg. 9. Tme dagram fr parallel turb decder (N=). wrte addresses are extracted frm ILM, whle the read nes are n nrmal rder. Frm tmng pnt f vew, Fg. 9 depcts the case when N= s used. Same cmments as the nes fr Fg. 5 apply. 5 Implementatn Results Frm Fg. 5 and 9 t can be bserved that the decdng latency s reduced n the case f parallel decdng wth almst a factr equal t N. There s a certan Delay, whch n ths mplementatn case s 11 clck perds that adds at each frward trells run, when the LLRs are cmputed, s such values are ntrduced at each teratn. The natve latency fr seral decdng s cmputed as fllws: K clck perds needed fr the backward trells run at the frst sem-teratns, anther K clck perds plus Delay fr the frward trells run and LLR cmputatn, and multpled by fr the secnd sem-teratn. Cnsderng L the number f executed teratns, t results a ttal latency n clck perds fr each blck seral decdng f: Testng the parallel decdng perfrmances, a certan level f degradatn was bserved, snce the frward and backward metrcs are altered at the data blck extremtes. In rder t btan smlar results as n the seral decdng case, a small verhead s accepted. If at each parallel blck barder an verlap s added, the metrcs cmputatn wll have a tranng phase. The mnmum verlap wndw may be as lng as the mnmum standard defned data blck, n ths case K mn =40 bts. Fg. 10 descrbes ths stuatn, fr N= case. The crrespndng latency s n ths case, cnsderng N>, whch leads t blcks wth K mn at bth left and rght sdes: ( ) Latency _ p = 4( K / N + K mn ) + Delay L. (15) In rder t evaluate the perfrmances, the used hardware prgrammng language s Very Hgh Speed Hardware Descrptn Language (VHDL). Fr the generatn f RAM/ ROM memry blcks Xlnx Cre Generatr 11.1 was used. The smulatns were perfrmed wth MdelSIM 6.5. The synthess prcess was dne usng Xlnx XST frm Xlnx ISE Usng these tls, the btaned system frequency when mplementng the decdng structure n a Xlnx XC5VFX70T- FFG1136 chp s arund 10 MHz. The values ncluded n Table 1 are cmputed based n (13), (14), and (15) fr the N=8 case. It can be ntced that the verhead ntrduced by the verlapped splt s less sgnfcant nce the value f K ncreases, whch represents the scenar when parallel decdng s usually used. ( ) Latency _ s = 4K + Delay L, (13) whle fr the parallel decdng the needed number f clck perds s: ( ) Latency _ p = 4 K / N + Delay L. (14) Table 1. Latency Values fr N=8, L= 3 r 4 and K=1536, 4096 r 6144 Latency_s [us] Latency_p [us] Latency_p [us] K L ISBN:

9 Advances n Crcuts, Systems, Sgnal Prcessng and Telecmmuncatns Table prvdes the crrespndng thrughput rate when the values frm Table I are used. Table. Thrughput Values fr N=8, L= 3 r 4 and K=1536, 4096 r 6144 Tput_s [Mbps] Tput_p [Mbps] Tput_p [Mbps] K L As ne can bserve frm Table, the seral decdng perfrmance s clse t the theretcal ne. Let us cnsder fr example the case K=6144 and L=3. The natve theretcal latency s 4KL clck perds, whch leads t a theretcal thrughput f 17.5 Mbps, whle the btaned results fr the prpsed seral mplementatn s Mbps. The fllwng perfrmance curves were btaned usng a fnte precsn Matlab smulatr. Ths apprach was selected because the Matlab smulatr prduces exactly the same utputs as the MdelSIM smulatr, whle the smulatn tme s smaller. All the smulatn results are usng the Max Lg MAP algrthm. All pctures descrbe the Bt Errr Rate (BER) versus Sgnal-t-Nse Rat (SNR) expressed as the rat between the energy per bt and the nse pwer spectral densty. Fg. 11 depcts the btaned results when a blck f length K = 51 was decded n a seral manner, n a parallel wthut verlappng manner and n a parallel wth verlappng manner. Fr ths scenar N =, QPSK mdulatn was used and L = 3. Fg. 1 presents the same type f results, fr the case f K = 104 and N = 4. As ne can bserve frm Fg. 11 and 1, the parallel decdng wth verlap s prducng same results as the seral decdng. BER 10 0 QPSK, 3 ter, 51 bts, N = seral parallel wth verlap parallel wthut verlap BER 10 0 QPSK, 104, 3 ter, N = parallel wth verlap parallel wthut verlap seral SNR[dB] Fg. 1. Cmparatve decdng results fr QPSK, L = 3, K = 104, N = 4. On the ther hand, the parallel decdng wthut verlap ntrduces a certan level f degradatn cmpared wth the seral decdng, the lss n terms f perfrmances beng dependent n the value f N. 6 Cnclusns The mst mprtant aspects regardng the FPGA mplementatn f a turb decder fr LTE-A systems were presented n ths paper. The seral turb decder archtecture was develped and mplemented n an effcent manner, especally frm the nterleaver/ denterleaver prcesses pnt f vew. The nterleaver memry ILM was ntrduced s that the nterleaver prcess t wrk effectvely nly utsde the decdng prcess tself. The ILM was wrtten tgether wth the nput data, whle the prevus blck was stll under decdng. Ths apprach allwed the transfer t the parallel archtecture n a smplfed way, usng nly cncatenated values at same memry lcatns. The parallel archtecture used the same number f blck memres and nly ne nterleaver, wth the cst f sme multplexng/ demultplexng structures. The parallel decdng perfrmances were cmpared wth the seral nes and certan degradatn was bserved. T elmnate ths degradatn, a small verhead was accepted by the verlappng splt that was appled t the parallel data blcks SNR[dB] Fg. 11. Cmparatve decdng results fr QPSK, L = 3, K = 51, N =. ISBN:

10 Advances n Crcuts, Systems, Sgnal Prcessng and Telecmmuncatns Acknwledgment The wrk has been funded by the Sectral Operatnal Prgramme Human Resurces Develpment f the Mnstry f Eurpean Funds thrugh the Fnancal Agreement POSDRU/159/1.5/S/ References: [1] C. Berru, A. Glaveux, and P. Thtmajshma, Near Shannn lmt errr-crrectng cdng and decdng: Turb Cdes, IEEE Prceedngs f the Int. Cnf. n Cmmuncatns, Geneva, Swtzerland, May 1993, pp [] C. Berru and A. Glaveux, Near ptmum errr crrectng cdng and decdng: Turb- Cdes, IEEE Trans. Cmmuncatns, vl. 44, n. 10, pp , Oct [3] C. Berru and M. Jézéquel, Nn bnary cnvlutnal cdes fr turb cdng, Electrncs Letters, vl. 35, n. 1, pp. 9-40, Jan [4] Thrd Generatn Partnershp Prject. 3GPP hme page. [5] 3GPP TS 36.1 V8.7.0 (009-05) Techncal Specfcatn, 3rd Generatn Partnershp Prject; Techncal Specfcatn Grup Rad Access Netwrk; Evlved Unversal Terrestral Rad Access (E-UTRA); Multplexng and channel cdng (Release 8). [6] F. Khan, LTE fr 4G Mble Bradband, Cambrdge Unversty Press, New Yrk, 009. [7] M. C. Valent and J. Sun, The UMTS turb cde and an effcent decder mplementatn sutable fr sftware-defned rads, Internatnal Jurnal f Wreless Infrmatn Netwrks, vl. 8, n. 4, Oct [8] M. Sanad and N. Hassan, Nvel wdeband MIMO antennas that can cver the whle LTE spectrum n handsets and prtable cmputers, The Scentfc Wrld Jurnal, vl. 014, art. ID , 9 pages, 014. [9] Suchang Chae, A lw cmplexty parallel archtecture f turb decder based n QPP nterleaver fr 3GPP-LTE/LTE-A, [10] Y. Sun and J. R. Cavallar, Effcent hardware mplementatn f a hghly-parallel 3GPP LTE/ LTE-advance turb decder, Integratn, the VLSI Jurnal, vl. 44, ssue 4, pp , Sept [11] D Wu, R. Asghar, Yuln Huang, and D. Lu, Implementatn f a hgh-speed parallel turb decder fr 3GPP LTE termnals, ASICON 09, IEEE 8th Internatnal Cnference n ASIC, pp , 009. [1] C. Studer, C. Benkeser, S. Belfant, and Qutng Huang, Desgn and mplementatn f a parallel turb-decder ASIC fr 3GPP-LTE, IEEE Jurnal f Sld-State Crcuts, vl. 46, ssue 1, pp 8-17, Jan [13] Xlnx Vrtex 5 famly user gude, [14] Xlnx ML507 evaluatn platfrm user gude, [15] P. Rbertsn, E. Vllebrun, and P. Heher, A Cmparsn f Optmal and Sub-Optmal MAP Decdng Algrthms Operatng n the Lg Dman, Prc. IEEE Internatnal Cnference n Cmmuncatns (ICC 95), Seattle, pp , June [16] S. Papaharalabs, P. Sweeney, and B. G. Evans, Cnstant lg-map decdng algrthm fr du-bnary turb cdes, Electrncs Letters vl. 4, ssue 1, pp , June 006. [17] Jung-Fu Cheng and T. Ottssn, Lnearly apprxmated lg-map algrthms fr turb decdng, Vehcular Technlgy Cnference Prceedngs, 000. VTC 000-Sprng Tky. 000 IEEE 51st vl. 3, pp. 5 56, 000. [18] C. Anghel, A. A. Enescu, C. Palelgu, and S. Cchna, CTC Turb Decdng Archtecture fr H-ARQ Capable WMAX Systems Implemented n FPGA, Nnth Internatnal Cnference n Netwrks ICN 010, Menures, France, Aprl 010. [19] C. Anghel, V. Stancu, C. Stancu, and C. Palelgu, CTC Turb Decdng Archtecture fr LTE Systems Implemented n FPGA, IARIA ICN 01, Reunn, France, 01. [0] Vrtex 5 Famly Overvew, Feb. 009, ISBN: