Fast Acquisition Digital Tanlock Loop with Adaptive Time Delay

Transcription

1 Fast Acqustn Dgtal Tanlck Lp wth Adaptve Tme Delay NAWAF AL-MOOSA, SALEH Al-ARAJI AND MAHMOUD AL-QUTAYRI Cllege f Engneerng and Infrmatn Scences Etsalat Unversty Sharjah UNITED ARAB EMIRATES Abstract: - In ths paper, a nvel apprach that enhances the lckng and acqustn characterstcs f the Tme Delay Dgtal Tanlck Lp s develped. The dea revlves arund replacng the sngle tme delay unt wth a dual tme delay structure. Ths apprach extends the trackng range f the lp and explts the desred characterstcs nduced by each tme delay n ts wn. Smulatn results f the new structure shw that the newly develped lp can ffer rapd acqustn and gd trackng perfrmance ver a wde lckng range. Applcatn f the lp t the demdulatn f FSK sgnal s demnstrated. Key-Wrds: - Dgtal Phase-Lcked Lps, Tanlck Lps, Adaptve Tme Delay. Intrductn Phase-Lcked Lps are used n a varety f cmmuncatn, cntrl and sgnal prcessng applcatns []. Dgtal Phase-Lcked Lps (DPLLS) have been ntrduced t vercme the prblems asscated wth ther analgue cunterparts partcularly n the applcatns f subcarrer trackng and bt synchrnzatn f dgtal data stream. The use f DPLLs allevates ther prblems nherent wth the analg PLL such as agng, cmpnent tlerances and dc drft [2]. One f the mst prmsng DPLLs s the Dgtal Tanlck Lp, whch ffered many advantages ver ther archtectures such as the lnearty f ts phase characterstcs and nsenstvty t fluctuatns f the sgnal pwer [3]. Recently, a mdfed archtecture f the rgnal Dgtal Tanlck Lp, called the Tme Delay Dgtal Tanlck Lp (TDTL), has been ntrduced. The mdfed archtecture vercmes the cmplextes f desgnng the Hlbert transfrmer, whch s an essental part f the Cnventnal Dgtal Tanlck Lp [4]. Hwever, the lnearty f the phase errr and the lckng range characterstcs are n lnger preserved n sme parts f the lckng regn. The tme delay s a dctatng parameter n defnng the lckng range and the frequency acqustn characterstcs f the TDTL [4,5]. Ths paper prpses a nvel structure f the TDTL that utlzes the best behavr f the lp n terms f carrer acqustn characterstcs ver a wde lckng range. Ths s acheved by utlzng tw tme delay blcks, exhbtng dfferent phase shfts, nstead f a sngle ne. The fllwng sectn descrbes the structure f the prpsed lp and presents an analyss f the man mathematcal prncples underlyng the peratn f the lp. Sectn 3 shws the results f the system smulatn under dfferent peratng cndtns. 2 Lp Structure and Analyss 2. Lp Structure The prpsed lp archtecture s depcted n Fg.. It s cmpsed manly f tw sample and hld blcks, Sampler s preceded by tw tme delay unts, whereas Sampler 2 has the same nput sgnal as that f the lp. y(t) Delay Delay 2 x (t) x 2 (t) d( Sampler DCO Sampler 2 x( Dgtal Flter y( Fnte State Machne (FSM) Fg. Adaptve Tme Delay DTL Phase Detectr arctan (XY) The generated samples frm bth arms f the lp are fed t a phase detectr, whch has a characterstc functn f tan ( y x), generatng an errr sgnal. Ths errr sgnal wll be appled t a

2 dgtal flter, n rder t prduce a drvng sgnal fr the Dgtally-Cntrlled Oscllatr (DCO), whch s merely a varable-perd clck trggerng the sample and hld blcks. The Fnte State Machne (FSM) wll decde, accrdng t the phase errr, whch f the delayed sgnals wll pass t Sampler. 2.2 Lp Analyss The nput t the lp s assumed t be a cntnuustme snusdal sgnal wth AWGN (Addtve Whte Gaussan Nse) fllws [ t + ( t) ] n( ) y( t) = Asn θ + t ω () Where A s the ampltude f the sgnal, ω s the free runnng frequency f the DCO, θ (t) s the nfrmatn bearng phase and n (t) s the AWGN. Assumng a frequency step at the nput then the phase prcess wll be θ ( t) = ( ω ω ) t + θ (2) Where ω s the radan frequency f the nput sgnal and θ s a cnstant. A phase lag = ωτ, where { },2 wll be nduced n the nput sgnal after t passes thrugh tw tme delay unts τ and τ 2. Therefre, the fllwng sgnals wll be generated [ t + θ ( t) ] n ( ) [ t + θ ( t) ] n ( ) x ( t) = Asn ω + t (3) x ( t) = Asn ω + (4) t Where n ( t) s the tme delayed AWGN due t τ. The cntrl sgnal d ( wll decde whch f the sgnals specfed by (3) and (4) wll be passed t Sampler, smlarly, y(t) wll be passed t Sampler 2 prducng the fllwng dscrete tme sgnals [ t( + ( ] n( ) [ t( + θ ( ] n ( y( = Asn ω θ + k (5) x( = Asn ω (6) + Where t ( dentes the ttal tme elapsed up t the k-th samplng nstant. The samplng nterval f the DCO between the samplng nstants t( k +) and t( s gven by T ( = T c( k ) (7) Where T = 2π ω s the free-runnng perd f the DCO, and c( k ) s the utput f the dgtal flter at the prevus samplng nstant. The ttal tme up t the k-th samplng nstant can be defned as k = k t ( = T ( ) = kt c( ) (8) = 0 And cnsequently the phase errr between the nput sgnal and the DCO s gven by k φ k = θ k ω ( ) ( ) c( ) (9) = 0 Nw, (5) and (6) can be redefned as [ ( + ] n ( [ ( ] n( ) y( = Asn φ + (0) x ( = Asn φ + k () These sgnals wll be appled t the phase detectr prducng the errr sgnal e( gven by sn e( = f tan sn [ φ( ] [ φ( + ] + ζ ( Where ( γ ) = π + [( γ + π ) md 2π ] (2) f, ζ ( s a randm phase dsturbance due t AWGN. The errr sgnal e ( wll serve as an nput t the dgtal flter whse transfer functn s D(z) and ts utput s the sgnal c ( that wll drve the DCO. Therefre, the system dfference equatn can be derved frm (7) and (9) as φ ( k + ) = φ( ωc( + Λ (3) Where Λ = 2π ( ω ω ) ω. Unlke the sngle delay TDTL, the dual delay varant allws fr the expltatn f the nfluences f changng the value f the tme delay, whch affects the perfrmance f the lp n terms f the lckng range and the acqustn speed [4,5]. In the frst rder lp, the dgtal flter cmprses nly a gan blck G, causng the system equatn t be redefned as [ φ( k ] Λ φ ( k + ) = φ( K h ) + (4)

3 Where K = ωg and all AWGN terms are neglected snce nse free analyss s t be perfrmed. Defnng K as ω G wll result n K = K W, where W = ω ω. The nmnal phase lag nduced by the tme delay unts n the nput can be ntally arranged by manpulatng the parameters ω and τ n the manner gven by = ωτ. Fllwng the analyss n [4], the lck range f the frst rder lp can be fund by numercally slvng the nequaltes gven by K 2 2 sn ( α ) + sn ( α + W ) < 2W (5) sn( W ) K > 2 W (6) Where φss = σ + jπ, j {,0, } φ ss s the steady state phase errr. Fg. 2 shws the lckng range fr = π 2 and 2 = π 3. It can be clearly seen frm Fg. 2 that the lckng bundary curves defnng each lck range are n parts nnlnear, and the areas cvered by each curve dffer n terms f the lp gan and the frequency range. In the prpsed system, the tme delay unts have been arranged s that = π 2 and 2 = π 3, ths wll ensure a symmetrc trackng range frm W = 0.5 up t W =.5. Hence, the system wll explt the gd range and acqustn characterstcs f n the area where W >, and f 2 n the area where W<. The lp gan K =.3 has been selected t ensure gd perfrmance and wde lckng range fr bth values f the tme delay. The states f the FSM are defned by the phase errr and the cntrl sgnal d (, f the system s subjected t a frequency step whch causes the nput sgnal frequency t g hgher than ω,.e. W < and the phase errr s greater than a predefned threshld ε > 0, the cntrl sgnal d ( wll allw the sgnal x 2 ( t ) t pass t Sampler, whereas f the system s subjected t a frequency step whch causes the nput frequency t g lwer than ω,.e. W>, the FSM wll mntr the phase errr untl t s belw anther threshld ε 2 < 0, then the cntrl sgnal d( wll allw the sgnal x ( t ) t pass t the sampler. The parameters ε and ε 2 allw fnetunng f the FSM behavr fr any ntended regn f peratn f the lp n rder t ensure fast acqustn behavr. 3 System Smulatn Results Fg. 3 (a) shws the transent respnse f the sngle delay lp wth = π 2 and K =.3 t a frequency step wth W = 0.5. Snce ths mde f peratn s utsde the lckng range f the lp, the phase errr wll dverge resultng n an unstable state, thus thrwng the lp n the unlcked mde. Ths s als llustrated n Fg. 3 (b), whch shws the phase plane plt fr the same frequency step, where t s clear that the phase wll nt cnverge t a steady state value. Fg. 2 Lckng Range f Frst Order TDTL wth dfferent values f, the Trackng Range s the Bld Lne (). Snce the value f the tme delay s f great nfluence n the cnvergence behavur f the lp [5]. The cnflctng requrements f fast acqustn and wde lckng range necesstate adptng mre than ne tme delay. The result f applyng the same frequency step t same TDTL but wth 2 = π 3 s shwn n Fg. 4 (a). It can be clearly seen that the phase errr wll settle t a steady state value wthn a few samples. Ths prperty s f great mprtance fr a wde range f cmmuncatn and sgnal prcessng applcatns. The same behavr s als llustrated by the phase plane plt shwn n Fg. 4 (b), where

4 the phase errr cnverges rapdly t a steady state value. (a) (a) (b) Fg.3 (a): Transent Respnse f the Sngle Delay TDTL wth = π 2 and K =.3 t a frequency step wth W = 0.5 (b) Phase Plane Behavr The sld perfrmance f the lp can als be demnstrated fr frequency steps less than ω,.e. W>, as shwn n Fg. 5, whch shws the transent respnse f the sngle delay TDTL wth 2 = π 3 and K =.3 t a frequency step wth W =.25. The respnse f the lp under the afrementned parameters s pr, and t s clear that the phase errr s nt cnvergng t a steady state value wthn an acceptable tme. Whereas the transent respnse f the same TDTL wth = π 2 fr the same frequency step, demnstrated n Fg. 6, shws that the phase errr cnverges t a steady state value n tw samples. (b) Fg.4 (a): Transent Respnse f the Sngle Delay TDTL wth 2 = π 3 and K =.3 t a frequency step wth W = 0.5 (b) Phase Plane Behavr A Ptental applcatn f the adaptve delay TDTL, wth wde lckng range and fast acqustn characterstcs descrbed abve, s FSK demdulatn. The sngle delay TDTL mght nt respnd wthn an adequate tme t sme frequency changes as demnstrated by the FSK demdulated sgnal f Fg. 7, where the settlng n the respnse t the hgher frequency W s lastng fr mre than fve samples. In addtn t settlng, the sngle delay TDTL mpses restrctns n the Symbl Rate R s, n ths example β, whch s the rat between the free runnng frequency f the lp f and the symbl Rate R s, s equal t 20 n rder t allw enugh tme fr the lp t settle fr each symbl. The adaptve delay TDTL vercmes ths lmtatn wng t ts fast acqustn characterstcs. As

5 llustrated n Fg. 8, the lp can respnd rapdly t the mdulatng frequences and settle wthn tw samples. In addtn t that, the symbl rate can be ncreased allwng fr hgh data transmssn rate, n ths example β has been decreased t 7.5. demnstrate the superr perfrmance f the lp by ts ablty t rapdly track all nputs wthn the lckng range. The applcatn f the adaptve delay lp n the demdulatn f FSK sgnals was demnstrated wth satsfactry perfrmance. Fg. 5: Transent Respnse f the Sngle Delay TDTL wth 2 = π 3 and K =.3 t a frequency step wth W =.25 Fg. 7: FSK Demdulatn Usng the Sngle Delay TDTL wth = π 2, W = 0.83, W 2 =.25, K =.3 and β =20. Fg. 6: Transent Respnse f the Sngle Delay TDTL wth = π 2 and K =.3 t a frequency step wth W =.25 Fg. 8: FSK Demdulatn Usng the Adaptve Delay DTL wth W = 0.83 and W 2 =.25 and β =7.5 4 Cnclusn A new Dgtal Tanlck Lp wth adaptve tme delay has been prpsed and the mathematcal analyss gvernng ts perfrmance has been utlned. The lp exchanges the sngle tme delay wth a dual structure n rder t take advantage f the best characterstcs f the ndvdual lps. The lp utlzes the best perfrmance fr >W>. The lp has been smulated usng MATLABSIMULINK. The results reprted abve References: [] G.C Hseh and J. C. Huang, Phase-Lcked Lp Technques A Survey, IEEE Transactns n Industral Electrncs, Vl.43, N.6, December 996, pp [2] W.C Lndsey and C. M. Che, A Survey f Dgtal Phase-Lcked Lps, Prceedngs f the IEEE, Vl.69, Aprl 98, pp

6 [3] J. C. Lee and C. K. Un, Perfrmance Analyss f Dgtal Tanlck Lp, IEEE Transactns n Cmmuncatns, Vl.COMM-30, N.0, Octber 982, pp [4] Z. M. Hussan, B. Bashash, M. Hassan-Al, and S. R. Al-Araj, A Tme-Delay Dgtal Tanlck Lp, IEEE Transactns n Sgnal Prcessng, Vl.49, N.8, August 200, pp [5] Z. M. Hussan, Cnvergence Behavr f the Frst-Order Tme-Delay Dgtal Tanlck Lp, IEEE Cmmuncatns Letters, Vl.6, N.7, July 2002, pp