Voltage Sag and Swell Mitigation Using Matrix Converter with Reduced Number of Switches

Transcription

1 Vlume: 5, Issue: 4, Pages: (14) ISSN : Vltage Sag and Swell Mtgatn Usng Matrx Cnverter wth Reduced Number f Swtches Dr. Samuel Rajesh Babu Department f EIE,Sathyabama unversty, Chenna-119. Emal: dr.samuelrajeshbabu@gmal.cm Dr.S.Deepa Department f EEE,Panmalar Insttute f Technlgy,Chenna-13. Emal: dee_sms13@yah.c.n ABSTRACT Dynamc Vltage Restrer (DVR) s used n pwer dstrbutn system t prtect senstve lads n vltage dsturbances. The perfrmance f DVR s related t the adpted cnfguratn and cntrl strategy used fr nverters. In ths paper, matrx cnverter wth reduced number f swtches (RMC) s used t mprve peratn f DVR t cmpensate vltage sag/swell. Smulatn results usng MATLAB/ Smulnk are presented t demnstrate the feasblty and the practcalty f the prpsed nvel Dynamc Vltage Restrer tplgy. Ttal Harmnc Dstrtn (THD) s calculated. The smulatn results f new DVR presented n ths paper, are fund qute satsfactry t elmnate vltage sag/swell. Keywrds: DVR, Matrx cnverter, swell, THD and vltage sag Date f Submssn: February 3, 14 Date f Acceptance: March 14, I Intrductn Pwer qualty prblems n ndustral applcatns cncern a wde range f dsturbances such as vltage sags and swells, flcker, nterruptns, harmnc dstrtn. Preventng such phenmena s partcularly mprtant because f the ncreasng heavy autmatn n almst all the ndustral prcesses. Electrncs devces hld substantal prmse fr makng dstrbuted energy applcatns mre effcent and t effectve. There s a need t develp advanced pwer electrncs nterfaces fr the dstrbuted applcatns wth ncreased functnalty (such as mprved pwer qualty,vltage/vlt-amperes reactve (VAR) supprt), cmpatblty (such as reduced dstrbuted energy fault cntrbutns), and flexblty (such as peratn wth varus dstrbuted energy surces) whle reducng verall ntercnnectn ts. The use f vltage surce nverters s ncreasng [1]. They are used bth fr feedng pwer frm dstrbuted generatrs t the transmssn grd and pwer t varus types f electrnc lads. In recent years, the number f dfferent pwer resurces cnnected t pwer systems (vltage grds) has ncreased and there has been a mve tward cnnectng small pwer resurces t the medum and lw vltage netwrk []. Pwer qualty standards fr cnnectn f an nverter t the grd are stll under develpment, snce prevusly there have been a few smlar hgh pwer applcatns. In [3] t s that the pwer qualty s determned by the vltage qualty, when the vltage s a cntrlled varable. In rder t delver a gd ac pwer the cntrlled pulse wdth mdulatn (PWM) nverter and L-C utput flter have t cnvert a dc vltage surce (e.g. batteres) t a snusdal ac vltage wth lw vltage THD and fast transent respnse under lad dsturbances. Anther mprtant aspect f pwer qualty s harmnc dstrtn. General requrements fr harmnc dstrtn can be fund n standard [4] and partcularly fr cnnectn f dstrbuted resurces t grd. PWM cntrl s the mst pwerful technque that ffers a smple methd fr cntrl f analg systems wth the prcessr s dgtal utput. Wth the avalablty f lw t hgh perfrmance DSP chps characterzed by the executn f mst nstructns n ne nstructn cycle, cmplcated cntrl algrthms can be executed wth fast speed, makng very hgh samplng rate pssble fr dgtally-cntrlled nverters.

2 Vlume: 5, Issue: 4, Pages: (14) ISSN : A DVR cnssts f a vltage-surce nverter, a seres-cnnected njectn transfrmer, an nverter utput flter, and an energy strage devce that s cnnected t the dc lnk [5]. The vltage-surce cnverter s a pwer electrnc devce, whch can generate a snusdal vltage wth any requred magntude, frequency and phase angle. Ths devce emplys nsulated gate bplar transstrs (IGBT) as swtches [6]. Ths cnverter njects a dynamcally cntrlled vltage n seres wth the supply vltage thrugh the three sngle-phase transfrmers t crrect the lad vltage. The man functns f the njectn transfrmer nclude vltage bst and electrcal slatn. The DC sde f the cnverter s cnnected t a DC energy-strage devce. Energy-strage devces, such as batteres r super-cnductng magnetc energy-strage systems (SMES) are requred t prvde actve pwer t the lad when vltage sags ccur [7]. In ths paper, battery s used as a surce f the DC vltage fr the reduced matrx cnverter. The utput f the nverter (befre the transfrmer) s fltered by Passve flters n rder t reject the swtchng harmnc cmpnents frm the njected vltage [8].Dfferent cntrl strateges were prpsed fr DVR. Vltage-Space Vectr PWM was mplemented n Estmatn f symmetrcal cmpnents f vltage t cntrl DVR s used n [9]. Synchrnus reference frame cntrl can be adpted t mprve vltage qualty f senstve lads[1].in ths paper, a DVR wth a new nverter tplgy s presented t suppress the lad harmncs and t cmpensate the vltage dsturbances. Ths nverter has less vltage harmncs generated n the ac termnal f the nverter cmpared wth cnventnal technque. II DVR Tplgy The man functn f a DVR s vltage njectn t cmpensate the vltage drp due t the vltage sag ccurrence. In the ther wrd DVR restres the lad vltage t ts rated value. T d ths, DVR needs t exchange actve and reactve pwer wth the system. There are tw types f DVR n general: 1) DVR wth n energy strage system ) DVR wth energy strage system. Each type has tw tplges: 1) supply-sdecnnected cnverter and ) lad-sde-cnnected cnverter. All f the mentned tplges are cmpared n [4] and the n energy strage DVR tplgy wth ladsde-cnnected cnverter has been evaluated as the best ne whch s shwn n Fg..1 Fg.1 General Type f DVR wth n energy strage and lad-sde-cnnected cnverter. As there s n energy strage devce n ths tplgy, DVR needs a mnmum system vltage t wrk prperly and t may nt be able t cmpensate very deep sags but the lack f energy strage devce s a great ecnmcal advantage. Furthermre, mst usual sags are wthn the range f DVR lmts. The matrx cnverter based DVR n ths paper s establshed n ths tplgy whch means a DVR wth n energy strage and lad-sde cnnected cnverter. Accrdng t Fg..1 tw cnverters are replaced by a matrx cnverter and the DC-lnk capactr s remved. Fgure. shws the resultant DVR system. Fgure. Matrx cnverter based DVR. The nput vltage f matrx cnverter cmes frm the lad and the utput f matrx cnverter s cnnected t an the tme nt erval when the crcut k k s n md e j, durng the kth cycle j m j Ts Ts njectn transfrmer. Matrx cnverter cntrls the requred cmpensatn vltage and njects that vltage thrugh the transfrmer. T reduce harmncs, bth nput and utput f matrx cnverter are suppled wth flters. There s n energy strage devce and the energy s taken frm the grd. III Reduced matrx cnverter Reduced matrx cnverter (RMC) s a cnvenent tplgy due t ts ptental t reduce the sze and weght f the cnverter and t ncrease the effcency nherent t less stages f cnversn. The reduced matrx cnverter (RMC) prvdes drect AC-AC cnversn wthut the need f a bulky DC lnk capactr, t s thus a cmpact slutn. Its man advantages are adjustable (ncludng unty) pwer factr, b-drectnal pwer flw, hgh qualty wavefrm, and the pssblty f a cmpact desgn due t the lack f large energy strage cmpnents. It prvdes snusdal nput and utput wavefrms, wth mnmal hgher rder harmncs and n sub-harmncs; the nput pwer factr can be fully cntrlled. Hwever, the cmplexty f ts cnventnal PWM strategy s prne t cmmutatn falure, whch s a factr that keeps t frm beng utlzed n ndustry. The prpsed matrx cnverter has fllwng advantages

3 Vlume: 5, Issue: 4, Pages: (14) ISSN : The prpsed methd matrx cnverter cnssts f nly the 4 b-drectnal swtches. Lne t lne shrt crcuts at the nput s vercme by varyng the swtchng pattern and by means f cmmutatn cntrl. Open crcuts at the utput (assumng nductve lad) s vercme by varyng the swtchng pattern and by means f cmmutatn cntrl IV Prncple f peratn The Sngle-Phase Matrx Cnverter (SPMC) cnssts f a matrx f nput and utput lnes wth fur b-drectnal swtches cnnectng the sngle-phase nput t the snglephase utput at the ntersectn. The SPMC s presented schematcally n Fg 4.1 Its nstantaneus nput vltage v(t) and ts utput vltage v(t). It cmprses f fur deal swtches S1, S, S3, and S4 capable f blckng frward and reverses vltages (symmetrcal devces) and swtchng between states wthut any delays. The matrx cnverter wll be desgned and cntrlled n such a manner that the fundamental f the utput vltage s.() V () t V () t ω t The nstantaneus value f the utput vltage, v(t), has the fllwng characterstcs: 1. Its maxmum value s dentcal t the maxmum value f the nput vltage.. It cntans fundamental and addtnal hgh rder harmncs lcated at well defned sampled frequences. 3. Its man harmnc has a stepped-up frequency and a stepped dwn ampltude. The fur pwer swtchng devces are swtched at hgh frequency, fs (fs >>f and f where f ω / Π and f ω /Π). The nrmalzed swtchng tme (r duty cycles f every swtch) durng any swtchng cycle (Ts 1/fs), s defned by Where j 1, s the peratn mde, k 1, n s the cycle number. It s bvus that j 1 j T s. (3) Fg 4.1 Sngle-phase matrx cnverter crcut cnfguratn at n lad SPMC peratng at n-lad: Wth the SB pen the SPMC s unladed as shwn n Fg4.1. Ths tplgy cnverts the nput vltage v(t), wth cnstant ampltude and frequency, thrugh the fur deal swtches t the utput termnals n accrdance wth pre-calculated swtchng angles. k k m + m 1..(4) 1 As a result f hgh frequency f the cnverter, the average utput vltage durng any kth swtchng cycle Ts s gven by k k k k V, ( m1 m ) V ( t) av..(5) Where v(t) s the nput vltage durng the Kth cycle and s practcally cnstant. Keepng wth equatn 6 ne can wrte that the fundamental f utput vltage s gven by V ( ω t) ( m1 m ) V ( ω t) (6) Fg 4. Sngle-phase matrx cnverter crcut cnfguratns at lad () () V t V t ω t.(1) Fgure 4.3 shws the nput vltage, the nstantaneus utput vltage, the desred fundamental f the utput vltage and the averaged utput vltage durng ne nput swtchng cycle fs 1KHz). Frm the fgure4.3, t can be seen that the nput vltage s almst cnstant wthn ne swtchng cycle (f << fs)

4 Vlume: 5, Issue: 4, Pages: (14) ISSN : ( ωt ) ( t) V 1+ V ω m1 V 1 V m ( ωt ) (11) Keepng wth equatn (11) we btan Fg 4.3 Input, Output, requred utput and averaged utput wave frms ω V ω V.(1) Frm equatns (5) and (6), we btan It s bvus that Frm equatns 4.7 and 4.8 s evdent that (7).. (8) (9) Equatn (9) must exst fr any tme, t, and ths mply that when (ω(t)) vanshes (ths functn > ) als (ω(t)) must vansh (> ). Therefre, nput and the utput wavefrms must be synchrnzed and the fundamental f utput vltage must crss zer mre frequently than the nput vltage. Hence, the sngle-phase matrx cnverter s a frequency step-up crcut capable f cnvertng an nput wavefrm wth an angular frequency gven by ω r ω...(1) ( ωt) ( t) V 1+ V ω m1 V 1 V m V V mj 1 1 ( ωt) The abve equatn means that sngle-phase matrx cnverter s steppng dwn the utput vltage fundamental. Based n the equatns (7) - (1), we can cnclude that the swtchng pattern, the Ms mght be calculated. The fur swtchng pwer devces S1, S, S3, and S4 wll be cntrlled accrdng t the swtchng pattern. The abve dscussed matrx cnverter tpcs can be summarzes as: 1. The matrx cnverter wll be cntrlled accrdng t a swtchng pattern and t the purpse s t btan an utput man harmncs as per equatn ().. Its nput, v(t) s a snusdal wavefrm and ts utput, v(t) cmprses a number f hgh rder harmncs. 3. Bth wavefrms have dentcal maxmum values and ttal RMS values. 4. The matrx cnverter s a frequency step-up and fundamental vltage step-dwn cnverter. Up t ths pnt the SPMC s unladed. V Mdes f peratn The crcut dagram fr the prpsed cnverter and mdes f peratn s shwn n fgure5.1, 5.1 (a),(b),(c)&(d). The cnventnal matrx cnverter has 8 swtches. But prpsed matrx cnverter cnssts f 4 swtchng devces. There are fur mdes f peratn. Where r 1,, 3 When ( w(t)), the m1 and m are calculated n accrdance wth equatn 3.8 and L Hsptal rule. The result s

5 Vlume: 5, Issue: 4, Pages: (14) ISSN : Fg 5.1(c) Fg 5.1 Crcut dagram fr the prpsed cnverter Mde 1: In mde3 swtch S and S 3 s ON. The Dde D 5, D 8,D 9 & D 13 the dde wll cnduct. The utput vltage s pstve. Mde4: Fg 5.1(a) In mde 1 swtch S 1 and S 4 s ON. The Dde D 1,D 4,D 14 & D 18 wll cnduct. The utput vltage s pstve Mde: Fg 5.1(d) In mde 4 swtch S1 and S4 s ON the dde D15, D9,D & D3 wll be cnduct. The utput vltage s negatve. VI Smulatn Results A typcal clsed lp cntrlled DVR wth the RMC n a smple pwer system t prtect a senstve lad n a dstrbutn system s presented n Fgure 6.1 Fg 5.1(b) In mde swtch S and S 3 s ON. The dde D 1,D 1,D 6 &D 7 wll cnduct. The utput vltage s negatve. Mde3: Fg 6.1 Clsed lp cntrlled DVR wth a matrx cnverter

6 Vlume: 5, Issue: 4, Pages: (14) ISSN : Subsystem1 cntans the rectfer and the nverter as shwn n Fgure 6.. The pulse wdth mdulatn technque was used t cntrl the RMC. Subsystem cnssts f PWM pulse generatn blcks as shwn n Fgure 6.3 The smulatn s dne usng MATLAB and the results are presented. b. Injected vltage (v) c. Cmpensated vltage (v) Fgure 6.5 shws the respnse f the clsed lp DVR system t the vltage sag. Intally, the system was subjected t sag f 3% magntude and.4sec duratn. Smulatn s dne and the transent perfrmance at the sag frnt and recvery was bserved. Fgure 6.5(a) shws the sag n vltage. Fgure 6.5(b) ndcates the njected vltage and the Fgure 6.5(c) shws the cmpensated lad vltage after vltage njectn Fgure 6. Subsystem 1 f the clsed lp DVR wth a matrx cnverter Fgure 6.3 Subsystem f the Clsed lp DVR wth a matrx cnverter Fgure 6.5 Respnse f RMC based DVR t a vltage swell a. Uncmpensated vltage (v) b. Injected vltage (v) c. Cmpensated vltage (v) Fgure 6.5 shws the respnse f the clsed lp DVR system t the vltage swell. The system was subjected t a swell f 13% magntude and.4sec duratn. Smulatn s dne and the transent perfrmance at the swell frnt and recvery was bserved. Fgure 6.5(a) shws the swell n vltage. Fgure 6.5(b) ndcates the njected vltage and the Fgure 6.5(c) shws the cmpensated lad vltage after vltage njectn. It s seen that the DVR has successfully cmpensated the swell. Fgure 6.6 shws the FFT analyss f the clsed lp DVR system wth a matrx cnverter. The ttal harmnc dstrtn (THD) value s.81%. The THD f the lad vltage s wthn the lmts (IEEE std.519). The THD s very lw n the case f the RMC when cmpared wth cnventnal matrx cnverter Fgure 6.4 Respnse f RMC based DVR t vltage sag a. Uncmpensated vltage (v)

7 Vlume: 5, Issue: 4, Pages: (14) ISSN : VII Cnclusn Fg 6.6 FFT Analyss f RMC Ths paper has presented a nvel DVR system tplgy emplyng a RMC wthut energy strage. In ths tplgy, the matrx cnverter nput termnals are cnnected n the lad-sde, characterstc that makes t able t generate the vltages fr deep vltage sags cmpensatn. The verall system encmpassng the vltage njectn cntrller and the plant have been smulated va detaled Matlab/smulnk. The prpsed cnverter s mre relable, cmpact and effcent than the exstng cnverter state f the art fr research wth ndrect-drve, back t back cnverter and lw frequency transfrmer. The cnversn frm AC t AC s perfrmed drect by the reduced matrx cnverter, thus the bulky capactr whch has the hghest falure rate f the pwer electrncs equpment can be mtted. References: [1]. Mahdanpr F.M., Hshmand R.A. and Atae M. (11), A New Apprach t Multfunctnal Dynamc Vltage Restrer Implementatn fr Emergency Cntrl n Dstrbutn Systems, IEEE Transactns n Pwer Delvery, Vl.6, N., pp []. Mradlu M. and Karshenas H.R. (11), Desgn Strategy fr Optmum Ratng Selectn f Interlne DVR, IEEE Transactns n Pwer Delvery, Vl.6, N.1, pp [3]. Ramrez D., Martnez S., Plater C.A., Blazquez F. and de Castr R.M. (11), Lw-vltage rdethrugh capablty frwnd generatrs based n Dynamc Vltage Restrers,IEEE Transactns n Energy Cnversn, Vl.6, N.1, pp [4]. Senturk O.S. and Hava A.M. (1), A Smple Sag Generatr Usng SSRs, IEEE Transactns n Industry Applcatns, Vl.48, N.1, pp [5]. Vlathgamuwa D.M., Wjekn H.M. and Ch S.S. (1), A Nvel Technque t Cmpensate Vltage Sags n Multlne Dstrbutn System&The Interlne Dynamc Vltage Restrer, IEEE Transactns n Industral Electrncs,Vl.53, N.5, pp [6]. Sastharan S. and Mahesh K Mshra (9), Adaptve Band Cntrller fr Dynamc Vltage restrer, Prceedngs f the IEEE Appled Pwer Electrncs Cnference, pp [7]. Nadu S.R. and Fernandes D.A. (9), Dynamc Vltage Restrer based n a fur-leg Vltage Surce Cnverter, IET prceedngs n Generatn Transmssn Dstrbutn, Vl.3, N.5, pp [8]. Pedr Rncer, Jse Enrque and Aurel Garca (9), A Versatle Cntrl Scheme fr a Dynamc Vltage Restrer fr pwer Qualty Imprvement, IEEE Transactns n pwer Delvery, Vl.4, N.1, pp Authrs Bgraphy Dr. R. Samuel Rajesh Babu has btaned has btaned hs B.E Degree frm Madras Unversty n 3.He btaned hs M.E degree frm Anna Unversty n 5. He btaned hs Ph.D degree frm Sathyabama Unversty n 13. Presently he s a asscate prfessr n Sathyabama Unversty. Hs areas f nterest are Pwer Electrncs and Dgtal Prtectn. Dr. S.Deepa has btaned her B.E Degree frm Peryar Unversty n 3.She btaned her M.E degree frm Annamala Unversty n 5. She btaned her Ph.D degree frm Sathyabama Unversty n 13. Presently she s a asscate prfessr n Panmalar Engneerng cllege. Her area f nterest s Pwer Qualty.