Wp/Lmin. Wn/Lmin 2.5V
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1 UNIVERITY OF CALIFORNIA Cllege f Engneerng Department f Electrcal Engneerng and Cmputer cences Andre Vladmrescu Hmewrk #7 EEC Due Frday, Aprl 8 th, 0 Cry Prblem #.5V Wp/Lmn 0.0V Wp/Lmn n ut Wn/Lmn.5V Wn/Lmn C L Fgure Calculate the lgcal effrt f the crcut shwn n Fgure gven that WpWnWmn. If R and R are the PMO and NMO equvalent resstances respectvely, the equvalent eqp eqn resstance f the crcut durng pull-up and pull-dwn s respectvely R R + R // R eqlh eqp ( eqp eqn eqhl Reqn ( Reqp // Reqn Reqp Reqn R eq ReqLH ReqHL R + nce R the abve equatns gve R / Fr the equvalent resstance t be equal t that f the mnmum szed nverter (R, the nput transstrs shuld be made / tmes larger, ncreasng thus the nput capactance by / (cmpared t the mnmum szed nverter. Hence, the lgcal effrt f the crcut s g / Prblem # uppse we want t mplement tw lgc functns gven by FA+B+C and A+B+C+D. Assume bth true and cmplementary sgnals are avalable. a Implement these functns n dynamc CMO as cascaded stages s as t mnmze the ttal transstr cunt.
2 V DD V DD F A B C D F D A + B + C + D. b Dscuss any cndtns under whch ths mplementatn wuld fal t perate prperly. When A+B+C, F wll make a transtn ->0, whch cannt be appled drectly t the secnd stage. If D0 fr example, wll be dscharged at the begnnng f the evaluatn phase. Therefre wll have an ncrrect value (0 fr ths cmbnatn f nput sgnals. c Desgn an np-cmo mplementatn f the same lgc functns. Des ths desgn dsplay any f the dffcultes f part b? V DD V DD A B C F D The stages n np-cmo can be cascaded drectly snce every stage prduces the crrect sgnal transtn fr the ppste type f lgc cnnected t ts utput.
3 Prblem # a hw that the expressn fr n Eq..6 s equvalent t the ne n Eq.. ABC + ABC + ABC ABC + ABC + ABC ABC + ABC ( AB + BC + AC ( A + B + C ( A + B( A + B + C ABC + ( A + B( C + A B( A + B + C ( A C + A B + B C + A B( A + B + C b Cnvnce yurself that the crcut n Fg.. mplements Eq..6. ze the transstrs such that each stage (carry and sum has the same pull-up/pull-dwn strength as a mnmum-szed / nverter. Fnd the lgcal effrt fr each nput (cnsder the carry and sum stages separately Lgcal effrt: Carry A.67 A 6. B.67 B 6. C.77 C 6. um c Nw cnsder the mrrr adder n Fg..6. Make sure that yu understand what t des. ze the transstrs such that each stage (carry and sum has the same pull-up/pull-dwn strength as a mnmum-szed / nverter. Fnd the lgcal effrt fr each nput (cnsder the carry and sum stages separately. Hw des t cmpare t the archtecture n Fg..?
4 6 6 6 Lgcal effrt: Carry A / A 5/ B / B 5/ C 6/ C 5/ um We can see that the mrrr adder has lwer lgcal effrt fr all nputs except C. Hwever we shuld nt frget the extra ladng and delay f the addtnal nverters n the cmplementary archtecture. When thse are ncluded the mrrr adder wns verall. Prblem # a Assumng that all nputs f the crcut shwn n Fgure belw are ntally 0 durng the precharge phase and that all nternal ndes are at 0V, calculate the vltage drp n V, f A changes t (V DD.5V durng the evaluate phase. It s gven that V tn0 0.5V, F 0.6V and γ0.v 0.5. Hnt: Dn t frget the bdy effect.
5 .5V CLK A M V CL0fF B M C5fF 0 M0 C5fF CLK Fgure Assumng that V <, the capactr C s charged t a vltage V, whch s the maxmum Δ ut V tn V vltage fr whch M cnducts. cnductn and cut-ff: V V tn V V ( F + VB F tn0 + γ s calculated usng the equatn that s vald at the edge f nce the bulk f the NMO transstrs s cnnected t grund, the prevus equatn can be rewrtten as: V V V Vtn0 + γ( F + V F V V Vtn0 + γ F γ( F + V ( V V Vtn0 + γ F γ ( F + V.78V V.8V V. 7V (We accept nly the lwer slutn f the quadratc equatn, snce after reachng ths vltage the transstr desn t cnduct and can t thus reach the hgher value. Hence, charge cnservatn yelds: V C V + C V CL DD L CLΔ V CV ΔV C V / CL 0. V 5
6 nce V V V, V tn 0. 8V. Hence, ur assumptn abut tn Δ V < V 0. V was crrect. tn 8 b Nw calculate the vltage drp n V f bth A and B change t (under the abve cndtns. mlarly t (a, capactrs C and C wll be charged t a fnal vltage f.7v. Hence, charge cnservatn gves: C ΔV C V + C V ΔV 0. 85V > V L Hence, ur assumptn that C s Δ V VDD, where C s C + C Cs + CL Hence, 0 Δ V.5V 0. 8V tn Δ V ut < Vtn desn t hld anymre and ΔV s calculated as fllws:. c What s the maxmum number f transstrs that can be cnnected n seres t M and M (ncludng M and M, excludng M0 f the utput shuld nt fall belw 0.9V durng the evaluate phase? Assume that each ne f the new transstrs has the same ntrnsc capactance (t grund as M and M (C5fF. The fnal value f V 0. 9V crrespnds t Δ V. 6V > Vtn. Hence, the fllwng equatn s vald: Cs Δ V VDD ( C + C s L where C s the ttal ntrnsc capactance t be charged. The wrst case s when all f the cnnected transstrs cnduct and thus C s NC (where N the number f the transstrs. In ths case ( gves: Δ V ( NC + C V NC L DD DD NC( V Δ V ΔV C.6V 0 ff N 7., hence N V 5 ff L 6
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