SIMULATION AND MODELING OF VECTOR CONTROLLED 3-PHASE MATRIX CONVERTER INDUCTION MOTOR DRIVE

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1 IMULATION AND MODELING OF ECTOR CONTROLLED 3-PHAE MATRIX CONERTER INDUCTION MOTOR DRIE Hüseyn Altun edat ünter e-mal: e-mal: Frat Unversty, Faculty f Engneerng, Department f Electrcal & Electrncs Engneerng, 39, Elazığ, Turkey ey wrds: Matr cnverter, vectr cntrl, nductn mtr, ulnk ABTRACT In ths paper, a vectr cntrlled matr cnverter-fed nductn mtr drve has been sulated usng the MATLAB/IMULIN package prgram. The feedfrward ndrect feld rentatn technue has been plemented n the drve system. A mdulatn algrthm gvng a unty pwer factr at the nput s used t generate swtchng sgnals f the devces n the matr cnverter pwer crcut. ulatn results btaned fr varus lad cndtns at khz swtchng freuency are presented. The results llustrate the feasblty f the hgh perfrmance matr cnverter drve system. I. INTRODUCTION The matr cnverter s the mst general cnverter-type n the famly f AC-AC drect cnverters. On the ne hand, the matr cnverter fulfls the reurements t prvde a snusdal vltage at the lad sde, n the ther hand t s pssble t adjust unty pwer factr n the mans sde under certan cndtns []. nce there s n dc-lnk lke n cmmn cnverters, the matr cnverter can be bult as a full-slcn structure. Hwever, a mans flter s necessary t smth the pulsed currents n the nput sde f the matr cnverter. Usng a suffcently hgh pulse freuency, the utput vltage and nput current bth are shaped snusdally. The matr cnverter s an alternatve t an nverter drve fr 3-phase freuency cntrl. The cnverter cnssts f nne b-drectnal swtches arranged as three sets f three s that any f the three nput phases can be cnnected t any f the three utput lnes as shwn n Fgure. The swtches are then cntrlled n such a way that the average utput vltages are a three phase set f snusds f the reured freuency and magntude []. The matr cnverter can cmply wth fur uadrants f mtr peratns, whle generatng n hgher harmncs n the three-phase AC pwer supply. Cmpared t cnventnal drves there s ptental fr reduced cst f manufacture and mantenance, and ncreased pwer/weght and pwer/vlume rats. The crcut s nherently capable f b-drectnal pwer flw and als ffers vrtually snusdal nput current, wthut the harmncs usually asscated wth present cmmercal nverters. The physcal realsatn f the matr cnverter s nt straghtfrward due t the fact that there are n freewheelng paths. In addtn, the number f the devces n the pwer crcut s hgh cmparng t that f the nverter (fr nstance 8-swtch and 8-dde). Cnseuently, the tng f the swtch actuatn sgnals s partcularly crtcal and prtectn f the crcut under fault cndtns reures very careful cnsderatn [3]. N ndustral use has als been made f ths cnverter type up t nw. A B C Fgure. Matr cnverter schematc blck dagram representatn. Only a few techncal papers have dealt wth the dynamc behavur analyss f the vectr cntrlled matr cnverter mtr drve. The prncple f vectr cntrl was devsed by Blaschke [4] and was develped by Lenhard [5]. Ths paper cncerns dynamc sulatn f the vectr cntrlled matr cnverter drve that has serv perfrmance and true fur uadrant capablty a b c

2 II. MODULATION ALGORITHM Many f the publshed papers n the plementatn f mdulatn algrthms fr the matr cnverter have emplyed fed swtchng patterns. In ths case, fr certan utput cndtns (ampltude, freuency etc.) duty cycles fr the swtchng patterns are pre-calculated and placed nt the memry. The fed swtchng patterns, fr nstance usng the enturn algrthm [], can be nly created fr certan utput freuences where nput and utput freuences are synchrnsed such as; 5 Hz, 50 Hz, 00 Hz etc. The prblem wth the mdulatn algrthms fr the matr cnverter s mre cmple than the usual PWM stuatn snce the swtch actuatn sgnals must be synchrnsed t the supply vltage whereas the synthessed utput freuency must be ttally asynchrnus wth respect t the supply freuency. Fr clsed lp peratn, t s reured t calculate the duty cycles every samplng perd n rder t acheve vltage cntrl n whch the utput freuency s cntnuusly varable. Fr unty nput dsplacement factr the duty cycle fr the swtch cnnected between the nput phase, β and utput phase, γ can be defned as; T γ β = T sn( ω t ψβ) sn(3ω () s m βγ t) where; ψ β : 0, π/3, 4π/3 crrespnds t the nput phases A,B and C, respectvely, m s the maum vltage rat (0.866), s the desred vltage rat, s the nput vltage vectr magntude and γ s gven by; γ = 4 cs( ω m t ψγ) - 6 cs(3ω t) cs(3ω where; ψ γ : 0, π/3, 4π/3 crrespnds t the utput phases, a,b and c, respectvely. Nte that the desred utput vltage has thrd harmnc cmpnents at the nput and utput freuences added t t t prduce γ. Ths s a reurement t get the maum pssble vltage rat []. Euatns () and () are used t calculate swtchng tes fr the matr cnverter. III. ECTOR CONTROL TRATEGY The vectr cntrl strategy has been sulated n the matr cnverter nductn mtr drve. The specfcatns f the mtr are gven n the append. The nductn machne s cntrlled n synchrnusly rtatng d- as frame wth the d-as rented alng the statr flu vectr pstn. In ths way a decupled cntrl between the electrcal true and the rtr ectatn current s btaned. The ndrect vectr cntrl technue usng pressed vltages and cntrl f feld and true current cmpnents has been plemented n the drve system. The cntrl reures the measurements f the statr currents and the rtr pstn. t) () Euatns (3-5) are the fundamental euatns fr vectr cntrl [5] and allws the nductn mtr t act lke a separately ected DC machne wth decupled cntrl f true and flu, makng t pssble t perate the nductn mtr as a hgh-perfrmance fur-uadrant serv drve. d mrd sd = τr mrd (3) dt ω sl = s r (4) τ mrd T e P L = 3 sds (5) L Fgure. shws a schematc blck dagram fr the vectrcntrlled matr cnverter nductn mtr drve where three utput currents and rtr pstn are reured t be measured. The vectr cntrl methd shwn n Fgure. pses a rtr flu vectr angle Θ e whch s algned t the d-as. The mtr speed, s measured and cmpared t the demanded speed,. The resultng speed errr s then prcessed by a prprtnal-ntegral (PI) cntrller t prduce an s demand, whch n the cnstant true regn s prprtnal t the true demand prvdng that the system s feld rented. The flu current demand s mantaned cnstant at just under saturatn level when the machne runs belw synchrnus-speed. Hwever, feld weakenng must be ntrduced abve synchrnusspeed peratng cndtns s that the flu current reference s reduced as the speed s ncreased abve ts synchrnus base. The transfrmatn f the nstantaneus statr currents nt feld rented d and as cmpnents s carred ut n tw stages. Frst, the three nstantaneus currents sa (t), sb (t) and sc (t) are transfrmed t the statnary tw as currents, sα (t) and sβ (t). These are then transfrmed nt the rtatng d- as currents, sd and s. The euvalent cmple peratr e -jθe s used n ths transfrmatn. Θ e dentes the nstantaneus flu vectr angle whch s determned by summng the rtr pstn sgnal and the cmmanded slp pstn btaned by ntegratng Euatn (4). The nverse transfrmatn f d and as values t the nstantaneus statr reference frame s represented by the cmple peratr e jθe. The tw current cntrllers whch emply PI cntrl prcess the sd and s errrs t gve sd and s. ltage cmpensatn terms are added t the utput f each current cntrller t get the resultng vltage reference sgnals sd and s. These vltages are then cnverted t the three-phase vltages usng the cmple peratr e jθe. The three-phase vltages a, b, c and nstantaneus flu vectr angle, Θ e are r

3 ECTOR CONTROLLER Isdα Φ PI (Current Cntrller) A B C - I s αte PI (peed Cntrller) sd PI s (Current Cntrller) d- Θ e s α s β A,B,C a (PWM) b (PWM) c (PWM) MATRIX CONERTER A B C Isd INTEGRATOR rtr Is ω sl ω e TG statr Inductn Mtr ω sl ωsl = R r Lr Is I sd Is Isd d- Θ e Isα Isβ A,B,C A B C Fgure. Blck dagram fr vectr cntrlled matr cnverter nductn mtr drve. Fgure 3. ulnk mdel f the vectr cntrlled matr cnverter nductn mtr drve. used as the nput sgnals fr the enturn algrthm (Euatns (-)) t generate the duty cycles fr each swtch n the matr cnverter. I. YTEM IMULATION The sulatn prgram s cnstructed n Matlab/ulnk package. The ulnk mdel fr verall system s shwn n Fgure 3. The mdel manly cnssts f the d- nductn mtr mdel, matr cnverter and vectr cntrller. On the tp f the fgure the d- ulnk mdel f the three-phase nductn mtr s gven tgether wth the transfrmatn blcks f a-b-c/α-β and α-β/d-. The ω sl -.. blck perfrms Euatn (4) and calculates the vltage cmpensatn terms t be added t the current cntrller utputs. In addtn, ths blck calculates the rtr flu vectr angle Θ e. The Is set.. blck s the speed PI cntrller n the vectr cntrl scheme. Output f ths blck prduces the true reference current, I s. The s - ds current PI blck plements the current PI s fr I s and I ds n the vectr cntrller n Fgure. The utput f these cntrllers are the s and ds d- demand vltages and nputs t the transfrmatn blck f ds t alpha-beta. Then, the blck f sa, sb, sc perfrms transfrmatn frm alpha-beta t a,b,c whch are the target utput vltages f the matr cnverter. The matr cnverter blck n Fgure 3. s gven n detal fr ne utput phase n Fgure 4.

4 0 n clck cs(u) cs(u-p/3) cs(u-4p/3) ut a vltages f the matr cnverter whch s recnstructed by the chpped three-phase nput vltage. Mtr steady-state current and the rtr flu cmpenents n n-lad cndtn are gven n Fgures 9. and 0., respectvely. OR rem(u,ts) < Fgure 5. Mtr speed and d- currents frm standstll t 000 rpm n n-lad. > AND > AND Fgure 6. Mtr speed and d- currents fr speed reversal frm 000 rpm t 000 rpm n n-lad. >= m Fgure 4. ulnk mdel f the matr cnverter fr ne utput phase.. IMULATION REULT ulatn results fr vectr cntrlled matr cnverterfed nductn mtr fr varus peratng cndtns are presented thrugh Fgures 5-3. Fgure 5. shws the mtr speed and d- currents frm standstll t 000 rpm. The mtr n ths nstance was nt laded and the ttal lad s the nerta and frctn f the mtr tself. The lnear acceleratn shws that the true reference current s held at ts ltng value thrughut the entre transent. In Fgure 6. the mtr speed and d- currents are gven fr speed reversal frm 000 rpm t 000 rpm fr the same lad cndtn. Fgure 7. llustrates the mtr speed and true fr varus speed reference cndtns n n-lad. In ths case, the mtr s accelerated frm standstll t 000 rpm and stays n steady-state fr a whle. Then, the reference s changed t 000 rpm. Therefre, the mtr speed decelerates fllwng ths reference sgnal. After the mtr speed reaches -000 rpm and remans at that speed fr a certan te the reference cmmand sgnal s agan changed t 000 rpm. As can be seen frm ths fgure the mtr perates at fur regns. Ths s man advantage f the matr cnverter cmparng t dc lnk nverter drves. Fgure 8 shws ne f the utput phase Fgure 7. Mtr speed and true fr varus speed reference cndtns n n-lad. Fgure 8. One utput phase vltage f the matr cnverter. Fgures -4 shw the sulatn results fr a cnstant lad f 7 Nm. In Fgure. mtr speed and d- currents are presented fr a speed refrence f 500 rpm t 000 rpm. As can be seen the mtr takes lnger te t accelerate because f the lad. Fgure llustrates the mtr speed and d- currents fr speed reversal frm 000 rpm t -000 rpm where the mtr perates as a generatr (I. regn) n steady-state when the mtr

5 speed reaches t target speed f 000 rpm. The mtr speed and true fr varus speed reference cndtns are shwn n Fgure 3. Fgure 4. demnstrates the threephase steady-state mtr currents under lad. Fgure 4. Three-phase steady-state mtr currents n lad. Fgure 9. Mtr steady-state current n n-lad. Fgure 0. Rtr flu cmpenents n n-lad. Fgure. Mtr speed and d- currents frm 500 rpm t 000 rpm n lad. Fgure. Mtr speed and d- currents fr speed reversal frm 000 rpm t -000 rpm n lad. I. CONCLUION In ths paper, a sulatn study f the vectr cntrlled matr cnverter-fed nductn mtr drve has been dne. A hgh perfrmance vectr cntrlled drve emplyng the matr cnverter has been presented. Instead f the nverter wth dc lnk n the vectr cntrlled drve system, the use f the matr cnverter has made the drve system capable f peratng n all fur uadrant regns. The sulatn results agree wth the nature f hgh perfrmance mtr drve system. REFERENCE. M. enturn, A New ne Wave In ne Wave Out Cnversn Technue Whch Elnates Reactve Elements, Prc. Pwercn 7, an Deg (CA), pp.e3-,e3-5, A. Alesna and M. enturn, ld-tate Pwer Cnversn: A Furer Analyss Apprach t Generalzed Transfrmer ynthess, IEEE Trans. n Crcut and ystems, vl. CA-8, n.4, pp , Aprl unter and J.C. Clare, Develpment f A Matr Cnverter Inductn Mtr Drve, MELECON, Antalya, pp , Aprl F. Blaschke, The Prncple f Feld Orentatn as Appled t The Transvectr Clsed-Lp Cntrl ystem fr Rtatng-Feld Machnes, emens Rev., 39,5, May 97, pp W. Lenhard, Cntrl f Electrcal Drves, prnger- erlag, Berln, 985. APPENDIX The ratngs f the three phase 50 Hz, 45, 4 kw, delta cnnected, 40 rpm surrel cage nductn mtr are: R s =5.3 Ω, R r =4.4 Ω, T=7 Nm., L s =0.6 H, L r =0.59 H, J=0.4 kgm, L =0.565 H, B=0.707 Nm.s/rad, csϕ=0.83, I s =8. A, P=4 ples Fgure 3. Mtr speed and true fr varus speed reference cndtns n lad.