2.45Ghz Wireless Radio Transceiver Design
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1 .Ghz Wireless Radio Transceiver Design Design and layout by Mohamed K. Design and layout by Mohamed K.
2 ON/OFF ADJ ON/OFF ADJ + + RX_.VDC U L IN OUT 0mH + C 0uF J R BP PS_main 9VDC K /SHDN R9 K MAX_EZK-T C 0nF RX_-.VDC L9 0mH C.uF F 0-RXE0 RX_VDC 0 U LM99S VIN TAP_IN VO R9 00K uf C Lf 0mH L 0mH R9 0 R9 00K J U LM0C IN OUT KILL RX + C 0uF RX_.VDC R + C 0uF U ADPAKC-.-RL Vin OUT OUT L 0mH + C 0uF D LED_LS0 DC Power regulation U ADPAKC-.-RL Vin OUT OUT L 0mH TX_.VDC + C 0uF TX_VDC L 0mH TX_-.VDC J U LM0C IN OUT U LM99S VIN VO L KILL TX C.uF 0 TAP_IN R9 00K uf 0mH C C uf + R9 0 R9 00K C.uF ** ALL 0mH Inductors are Chilisin Elect PN SDS00BL- 0M-S. ** All capacitors are AVX 00 > 0 Volts. ** All inductors are Pulse Tech PE-00CD. ** All Trim Resistors are Murata PVZA. ** All resistors are TT Elect. PFC.%, 00, %PPM ** ALL OF THE DC INVERTER 0UF Caps are: Taiyo Yuden PN/ JMKBJ0KL/ 0 PCB Design and layout by Mohamed K. WLAN PROJECT, Dr. M.K. Nezami, Dr. Zul, Eng. Kamal, Eng. Faisal Title WLAN PROJECT: Power Supply Size Document Number Rev C <Doc> A Date: Monday, February, 00 Sheet of
3 J LTCH_TX_AGC LTCH_TX_AGC CLCK_TX_AGC CLCK_TX_AGC DATA_TX_AGC DATA_TX_AGC LTCH_RX_AGC LTCH_RX_AGC CLCK_RX_AGC CLCK_RX_AGC DATA_RX_AGC DATA_RX_AGC TX_I/Q_AGC RX_I/Q_AGC R.K R³.K R.K R.K R.K PLL_EN PLL_CLK PLL_DATA PLL_PWDN TBD DAC_PA_PC TBD DIG_ PLL_AUX_OUT RX_.VDC TX/RX R L L³ 0 00nH 00nH I/O interface This is where the logical common point connection between the digital ground and the RF ground DIG_ Design and layout by Mohamed K.
4 Rf VGA V+ V- VGA Vcc IOUT+ Vcm Qout- IOUT- EN Qout+ Vcc V+ V- R9 9.9 U J Q- R 9.9 RX_-.VDC L9 nh C.uf DATA_RX_AGC CLCK_RX_AGC LTCH_RX_AGC INLO ICOM DATA CLCK LTCH VCCO 0 OCOM 9 OPLO INHI ICOM VCC PWUP VOCM VCCO OCOM OPHI 9.9 R0 C.uf L0³ RX_-.VDC ** ALL 0mH Inductors are Chilisin Elect PN SDS00BL- 0M-S. ** All capacitors are AVX 00 > 0 Volts. ** All inductors are Pulse Tech PE-00CD. ** All Trim Resistors are Murata PVZA. ** All resistors are TT Elect. PFC.%, 00, %PPM J Q- R 9.9 AD0 L nh Cf pf C³.uf nh RX_.VDC R 9.9 RX_VDC RX_VDC J I- R 9.9 RX_-.VDC L nh.uf C9 DATA_RX_AGC CLCK_RX_AGC LTCH_RX_AGC INLO ICOM DATA CLCK LTCH VCCO 0 OCOM 9 OPLO U9 INHI ICOM VCC PWUP VOCM VCCO OCOM OPHI R 9.9 C0.uf U RX_.VDC L nh LT00-0 IN- 00 R RX_VDC R K R 99 I-DC_of f MMBT U0f R³ K R9 0K R0 0K R K R K U R MMBT 00 R 99 Q-DC_of f RX_.VDC L nh LT00-0 U IN- C.uf J I+ 9.9 C.uf AD0 Cf.uf RX_-.VDC L.uf C L nh RX_.VDC RX_-.VDC nh L OUT+ BB-FIL OUT- VMID VOCM IN+ R9³ 00 R K R 99 U MMBT R0 K R³ 0K R 0K Rf K RX_VDC R K U MMBT R 99 R 00 VMID OUT+ BB-FIL VOCM OUT- IN+ Lf C nh RX_-.VDC J RECEIVER nh Gain=dB R.K BIAS RFIN U LNA RFOUT VCC C9.uf C0 pf L9.nH R.K BIAS RFIN U C.uf LNA MAX RFOUT VCC I+DC_of f C 0pF LDBG0C-0 T L0.nH U RF+ QUAD DMOD Vcc RF- LO- LO+ Vcc LT 0 9 T L.nH LDBG0C-0 Q+DC_of f.uf pf C L.nH MAX L L nh RX_VDC R9 0 R0 00k R 00k L nh RX_VDC nh RX_VDC C pf C.uF J RX_LO C C pf C³.uF + Cf 0uF C 00pF pf RX_VDC RX_VDC R.0K R R.0K R k R 0k R.K C pf J9f TX_DC_OFF_ADJ I+DC_of f R9 0k R.k k J0 C TX_DC_OFF_ADJ Q+DC_of f 000pF R0 0k R 0k Receiver RX_VDC R.0K R.K R k J RX_VDC R.0K R³.K R k J R 0k C9 TX_DC_OFF_ADJ I-DC_of f pf R9 0k C0 TX_DC_OFF_ADJ pf Q-DC_of f R0 0k R 0k Design and layout by Mohamed K. WLAN PROJECT, Dr. M.K. Nezami, Dr. Zul, Eng. Kamal, Eng. Faisal Title WLAN PROJECT: Receiver Size Document Number Rev D <Doc> A Date: Monday, February, 00 Sheet of
5 PLL_CLK IF & RF PLL RF Center Freq 00MHz RX_.VDC PLL_EN PLL_DATA L nh U0 R -dbm Nominal J LO_TX -dbm Nominal J LO_RX k R R 0 R0 R k R Value = 00 RF_OUT U9 db SP RF_OUT SCN-- RF_IN C 0pF R SCLK SDATA NC NC RFOUT VDDR /SEN VDDI IFOUT 0 IFLB 9 IFLA VDDD XIN /PWDN AUXOUT L9 nh L C.uf 0nH RX_.VDC C.uf L³ nh C³ 0pF R 9.9 R9 k 0 R k RX_.VDC L0 nh Si C.uF PLL_PWDN RX_.VDC PLL_AUX_OUT RX_VDC L 00nH R LOCK INDICATOR D LED_LS0 R 9.9 U C.uf R. R C.uf R.K.K C³ pf R 00k /INH TCXO Vcc FOUT MFO-0F R K C9 J TCXO_out Q³ MMBTA.K R9.K pf TP T POINT R ** ALL 0mH Inductors are Chilisin Elect PN SDS00BL- 0M-S. ** All capacitors are AVX 00 > 0 Volts. ** All inductors are Pulse Tech PE-00CD. ** All Trim Resistors are Murata PVZA. ** All resistors are TT Elect. PFC.%, 00, %PPM PLL Synthesizer R90.K Design and layout by Mohamed K. WLAN PROJECT, Dr. M.K. Nezami, Dr. Zul, Eng. Kamal, Eng. Faisal Title WLAN PROJECT: Synthesizer Size Document Number Rev C <Doc> A Date: Monday, February, 00 Sheet of
6 QUAD MOD VGA V- V+ VGA V- V+ CTRL/VDD RFC 0 RF RF Vcc VDAC=0mv+>I_dac(.)= GYa.in=0Rsh/(Rsh+Rser) Rser=0, Rsh=inf, Gain= Pout=-dBm Gain=0/R Fc=/*pi*R*C TX_.VDC L 00nH C0.uf Gain to db Rout 00 Ohm Diff Rin 00 Ohm Diff PdB +dbm NF db Output Comm DC.V SET GAIN to db Q J³ I+ J9f I- U R99 R R0 IN- 00 VMID OUT+ R0 C BB-FIL 00 R0 0pF.9 VOCM OUT- IN+ R0.9 LT00-0 Cf.uf C L.uf TX_-.VDC nh nh L U INHI INLO ICOM ICOM VCC DATA PWUP CLCK VOCM LTCH VCCO VCCO OCOM OCOM 0 OPHI OPLO 9 AD0 DATA_TX_AGC CLCK_TX_AGC LTCH_TX_AGC R k.uf C L nh TX_-.VDC.VDC VPP for RF=-0dbM ** ALL 0mH Inductors are Chilisin Elect PN SDS00BL- 0M-S. ** All capacitors are AVX 00 > 0 Volts. ** All inductors are Pulse Tech PE-00CD. ** All Trim Resistors are Murata PVZA. ** All resistors are TT Elect. PFC.%, 00, %PPM TX_.VDC L nh + C0f 0uF TX_-.VDC Cf pf C.uf k Rf Pout=-dBm R0.k R0 k.k R9 Vcc=V, Pout=9dBm G=dB TX_VDC C 0.0uf C I J Q+ J Q- TX_-.VDC L R.9 R0.9 nh.uf C 0pF C R.9 R.9 VMID L0 nh BB-FIL VOCM IN+ LT00-0 TX_.VDC C90³ pf U9 OUT+ IN- OUT- C0.uf nh L R 00 R9 00 TX_VDC J TX_DC_OFF_ADJ C 0.uF Gain to db Rout 00 Ohm Diff Rin 00 Ohm Diff PdB +dbm NF db Output Comm DC.V U0 INHI ICOM VCC PWUP VOCM VCCO OCOM OPHI AD0 INLO ICOM DATA CLCK LTCH VCCO OCOM 0 OPLO 9 k.k R R.k R.k Rf R0 R k.k R0 k.k R9 TX_-.VDC L nh.uf C DATA_TX_AGC CLCK_TX_AGC LTCH_TX_AGC R³ k.vdc R R0.k k LDBG0C-0 LDBG0C-0 00pF C T C9 00pF L9 TX_VDC nh Cf pf C 00pF U IBBP IBBN COM COM LOIN LOIP VPS ENBL AD QBBP QBBN COM COM VPS VOUT COM COM 0 9 C0.pF C³ pf Pout=-9dBm R³ 9 Cf.uF L 00nH R0 9 R 0 TX_VDC ADJUST FOR BEST LINEARITY, now=-.db I/Q imbal deg,.db SSB suppr -db Outp Power -0dBm OPdB=-dBm LO out -0dBm Input imp (I/Q) = K Ohm LO in = -dbm R 9 U LFBHGSGA RF FIL RFIN IL -.db Pout=-dBm RFOUT L.nH pf C0 R.K BIAS RFIN U³ LNA MAX Gain=dB IIP=-dBm NF=dB IPdB=-dBm RFOUT VCC C0 pf Pout=+dBm Cf.uf TX_VDC L nh J³ TX_PWR_ADJ R.k 0.V PA=off V PA=MAX R.9K C0.pF R 0k C0³.pF TX_VDC RF IN RF IN PC C 0.0uf U0 RF OUT RF OUT RF OUT RF OUT PRE-PA RF TX_VDC 0UF L nh C90.pF PE IL -0.9dB Pout=ddBm+Pin RX_.VDC L nh 0pF C0 C pf IL -.db L=RX H=TX CTRLTX/RX Rf.k C pf U C pf C 0.0uf TX_.VDC L 00nH TX_-.VDC + C9 0uF C9.uf k R TX_ON D 9-SSL-LX0ID Jf TX_mannual_On R9 C9 00 J TX_LO Qf MMBTA R³.uf R0.K DAC_PA_PC.K J ANTENNA U LFBHGSGA RF FIL RFIN RFOUT TX/RX J9 RECEIVER Transmitter WLAN PROJECT, Dr. M.K. Nezami, Dr. Zul, Eng. Kamal, Eng. Faisal Title WLAN PROJECT: TRANSMITTER Size Document Number Rev D <Doc> A Date: Saturday, February, 00 Sheet of Design and layout by Mohamed K.
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