HD74HC160/HD74HC161/ HD74HC162/HD74HC163

Transcription

1 HD74H160/HD74H161/ HD74H162/HD74H163 Synchronous Decade ounter (Direct lear) Synchronous 4-bit Binary ounter (Direct lear) Synchronous Decade ounter (Synchronous lear) Synchronous 4-bit Binary ounter (Synchronous lear) Description he HD74H160 and the HD74H162 are 4 bit decade counters, and the HD74H161 and the HD74H163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to transition (positive edge) of the clock input waveform. hese counters may be preset using the load input. Presetting of all four flip-flops is synchronous to thte rising edge of clock. When load is held low counting is disabled and the data on the A, B,, and D inputs is loaded into the counter on the rising edge of clock. If the load input is taken high before the positive edge of clock the count operation will be unaffected. All of these counters may be cleared by utilizing the clear input. he clear function on the HD74H162 and HD74H163 counters are synchronous to the clock. hat is, the counters are cleared on the positive edge of clock while the clear input is held low. he HD74H160 and HD74H161 counters are cleared asynchronously. When the clear is taken low the counter is cleared immediately regardless of the clock. wo active high enable inputs Enable P and Enable and a ripple carry output are provided to enable easy cascading of counters. Both enable inputs must be high to count. he Enable input also enables the Ripple arry output. When enabled, the Ripple arry outputs a positive pulse when the counter overflows. his pulse is approximately equal in duration to the high level portion of the A outputs. he Ripple arry output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters. Features High Speed Operation: t pd (lock to ) = 18 ns typ ( L = 50 pf) High Output urrent: Fanout of 10 LSL s Wide Operating Voltage: V = 2 to 6 V Low Input urrent: 1 µa max

2 HD74H160/HD74H161/HD74H162/HD74H163 Low uiescent Supply urrent: I (static) = 4 µa max (a = 25 ) Function able Inputs Outputs lock lear* 1 Enable P Enable n L X X X Reset-clear H L X X input data H H H H ount H H L X No count H H X L No count Note: and 163 Only-160 and 161 are Asynchronous lear Devices Decade ounter Binary ounter Asynchronous clear HD74H160P HD74H161P Synchronous clear HD74H162P HD74H163P Pin Arrangement lear 1 16 V lock A 2 3 K Ripple arry A A Ripple arry Output A Data Inputs B 4 5 B B B Outputs D 6 D D 11 D Enable P 7 P 10 Enable GND 8 9 (op view) 2

3 HD74H160/HD74H161/HD74H162/HD74H163 D haracteristics a = 40 to a = Item Symbol V (V) Min yp Max Min Max Unit est onditions Input voltage V IH V V IL V Output voltage V OH V Vin = V IH or V IL I OH = 20 µa I OH = 4 ma I OH = 5.2 ma V OL V Vin = V IH or V IL I OL = 20 µa I OL = 4 ma I OL = 5.2 ma Input current Iin 6.0 ±0.1 ±1.0 µa Vin = V or GND uiescent supply current I µa Vin = V or GND, Iout = 0 µa 3

4 HD74H160/HD74H161/HD74H162/HD74H163 A haracteristics ( L = 50 pf, Input t r = t f = 6 ns) a = 40 to a = Item Symbol V (V) Min yp Max Min Max Unit est onditions Maximum clock f max MHz frequency Propagation delay t PLH ns lock to time t PHL ns lear to (H160, H161 only) ns Enable to Ripple arry output ns lock to Ripple carry output Setup time t su ns Data to lock to lock lear to lock (H162, H163 only) Hold time t h ns Removal time t rem ns

5 HD74H160/HD74H161/HD74H162/HD74H163 A haracteristics ( L = 50 pf, Input t r = t f = 6 ns) (cont) a = 40 to a = Item Symbol V (V) Min yp Max Min Max Unit est onditions Pulse width t w ns Output rise/fall t LH ns time t HL Input capacitance in pf Function able ount Enable/Disable ontrol Inputs Result at Outputs Enable P Enable A to D Ripple arry Output H H H ount High when A to D are maximum L H H No count X L H No count High when A to D are maximum X H L No count L X L L No count L 5

6 HD74H160/HD74H161/HD74H162/HD74H163 iming Diagram HD74H160/HD74H162 Sequence illustrated in waveforms. 1. lear outputs to zero. 2. Preset to BD seven. 3. ount to eight, nine, zero, one, two and three. 4. Inhibit lear(h160) lear(h162) (Asynchronous) (Synchronous) A Data Inputs B D lock(h160) lock(h162) ount Enables Enable P Enable A Outputs B D Ripple arry Output lear ount Inhibit 6

7 HD74H160/HD74H161/HD74H162/HD74H163 HD74H161/HD74H163 Sequence illustrated in waveforms. 1. lear outputs to zero. 2. Preset to binary twelve. 3. ount to thirteen, fourteen, fifteen, zero, one and two. 4. Inhibit lear(h161) lear(h163) (Asynchronous) (Synchronous) A Data Inputs B D lock(h161) lock(h163) ount Enables Enable P Enable A Outputs B D Ripple arry Output lear ount Inhibit 7

8 HD74H160/HD74H161/HD74H162/HD74H163 Logic Diagram HD74H160 Decade ounter with Asynchronous lear A 1 P1 A A A B 2 P2 B B B 3 P3 D 4 P4 D D D Enable P Enable lear V Ripple arry Output lock 8

9 HD74H160/HD74H161/HD74H162/HD74H163 HD74H161 4-bit Binary ounter with Asynchronous lear A 1 P1 A A A B 2 P2 B B B 3 P3 D 4 P4 D D D Enable P Enable lear Ripple arry Output lock 9

10 HD74H160/HD74H161/HD74H162/HD74H HD74H162 Decade ounter with Synchronous lear K A B D RO K A B D P V K K K IN K K IN K K IN K K IN

11 HD74H160/HD74H161/HD74H162/HD74H HD74H163 4-bit Binary ounter with Synchronous lear K A B D RO K A B D P K K K IN K K IN K K IN R R IN

12 Max 16 9 Unit: mm Max Max 2.54 ± ± Min 2.54 Min 5.06 Max Hitachi ode JEDE EIAJ Weight (reference value) DP-16 onforms onforms 1.07 g

13 Unit: mm Max Max 1.27 *0.42 ± ± ± Max 0.15 *0.22 ± ± ± M *Dimension including the plating thickness Base material dimension Hitachi ode JEDE EIAJ Weight (reference value) FP-16DA onforms 0.24 g

14 Unit: mm Max Max Max *0.22 ± ± *0.42 ± ± M *Dimension including the plating thickness Base material dimension Hitachi ode JEDE EIAJ Weight (reference value) FP-16DN onforms onforms 0.15 g

15 Unit: mm * ± Max M 0.65 Max 6.40 ± Max 0.10 *0.17 ± ± ± 0.10 *Dimension including the plating thickness Base material dimension Hitachi ode JEDE EIAJ Weight (reference value) P-16DA 0.05 g

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