Penryn / Cantiga / ICH9-M

Transcription

1 PU THERML SENSOR.V PG RII-SOIMM RII-SOIMM 0.V_R_VTT.V_SUS.V V_R_MH_REF PG, Web am on L US V luetooth US V_SUS US PORT X US0~, V_SUS Fingerprint US O(fixed) V Internal H V.V PG PG PG PG PG PG HP SPI FLSH PG SWITH OR.V_LW RII MHz PG SPI US.0 ST ST FN PG.V.0V_VP V_ORE FS /00 MHz Touchpad V PU Penryn ( Micro-FPG) NORTH RIGE.0V_VP.V_SUS.V.V V_R_MH_REF X'TL.KHz.V.0V_VP.V.V.V_LW.V_S.V_SUS V_VLN V V_LW V_S VRT_(~) antiga ufg IH-M G LP X'TL.KHz.V_LW.V V RT_V IT0E MI LINK X PI-E LQFP PIN Keyboard PG, PG ~ PG ~ PG SPI FLSH FOR restline (L/RT/S-VIEO) FOR restline (L/RT) SVO PI-E zalia MOEM ONN. (M).V_SUS PG.V_LW PG.V_LWPG Parade WIRE PS0 PG PI PG RJ/US X oard to board ONN. PG PU LK_ 00MHz GMH LK_ 00MHz REFLK_MHz PIE MH LK_00MHz HMI L Panel RT port zalia odec X0 PG V MP TP0 PG V_SPK_MP VIN_LIGHT LV.V V.V HMI port.v.v JK HEPHONE/SPIF INT. MI INT. SPEKERS PG S LOK IGRM LOK GEN ISLPRS/RTMT-0 pins.v PG PG 0 PG X'TL.MHz PIE IH LK_00MHz LN(0/00) Marvell E00 LN_. LN_. LN_. LN_E. LNV RJ JK PG 0 ST IH LK_00MHz PG 0, X'TL MHz Penryn / antiga / IH-M PIE LN LK_00MHz PG PIE MINIR LK_00MHz PIE NEW R LK_00MHz MINI-PI-E ard X US~.V_SUS.V.V PI OZT LK_MHz PG EXPRESS R (NEW R) US V_NEWR VUX.V_NEWR ocument Number ustom LOK IGRM V_S/V_S PG 0 PU ORE POWER ISL0ISL0.V &.0VP (RT0) R.V_SUS & 0.V / POWER _LW &.V_LW HRGER ISL RUN POWER SW & ISHRGE PG PROJET : S PG PG PG RREER ONTROLLER OZT.V.V IN SM/x-Picture S/MM MS/MSPRO (F) PG PG PG PG PG Quanta omputer Inc. ate: Friday, pril, 00 Sheet of

2 .V L LMPG00SN L LMPG00SN ST_LKREQ# MINILK_REQ# PLK_LP_EUG OZTLK 0 PI_LK_ LK_PI_IH LK_IH_M, PU_MH_SEL0, PU_MH_SEL, PU_MH_SEL LK_IH_M E -0 dd in tage For EMI use U/.V/XR_ U/.V/XR_ L LQGHSNS0 P/0V ST_LKREQ# MINILK_REQ# PLK_LP_EUG OZTLK PI_LK_ LK_PI_IH LK_IH_M LK_IH_M 0 0.U/0V/XR_ 0.U/0V/XR_ 0 0.U/0V/XR_ 0.U/0V/XR_ E -0 change P to 0P for RT issue. 0P/0V/NPO_ 0P/0V/NPO_ 0 0.U/0V/XR_ 0.U/0V/XR_ R R R _ R _ R0 _ R.K_ R0 0K_ R0 _ K_V_MIN K_V_MIN 0.U/0V/XR_ /F_ R _ R0 *M/F_ 0.U/0V/XR_ /F_ R _ 0.U/0V/XR_ 0 0.U/0V/XR_ STLKREQ#_R MINILK_REQ#_R PI/TME PI FTSEL PI_F/ITP_EN FSL FSL XIN XOUT Y.MHZ 0 0.U/0V/XR_ 0 0.U/0V/XR_ U VPI V VPLL VREF VSR VPU V_IO 0 VPLL_IO VSR_IO VSR_IO VPU_IO VSR_IO 0 0 PI0/R#_ PI/R#_ PI/TME PI PI/_Select PI_F/ITP_EN US_MHz/FSL FSL/TEST_MOE REF0/FSL/TEST_SEL X X GNPI GN GN GN GNPU GNSR GNSR GNSR GNREF K0 N SLK ST PI_STOP# PU_STOP# PUT0 PU0 PUT_F PU_F 0 PUT_ITP/SRT PU_ITP/SR SR0 SRT0 SRT/R#_H SR/R#_G SRT 0 SR SRT/R#_F SR/R#_E SRT SR 0 SRT SR R#_/SR- SR/R#_ SRT/STT SR/ST MHz_NonSS/SRT/SE MHz_SS/SR/SE SRT0/OTT_ SR0/OT_ K_PWRG/P# ISLPRSGLFT / RTMT-0 GLK_SM_M GT_SM_M PU_LK PU_LK# MH_LK MH_LK# LK_PIE_NEW LK_PIE_NEW# MH_GPLL# MH_GPLL LK_GPLLREQ#_R MINILK_REQ#_R PIE_MINI PIE_MINI# NEW-R_LK_REQ#_R R0 SR T PIE_IH PIE_IH# PIE_MINI PIE_MINI# LK_LN LK_LN# PIE_ST PIE_ST# REFSSLK_R REFSSLK#_R REFLK_R REFLK#_R T R R RP 0X RP 0X 0X RP RP 0X /F_ /F_ /F_ RP 0X RP 0X 0X RP RP 0X RP 0X RP 0X RP0 0X LK_GPLLREQ# MINILK_REQ# NEW-R_LK_REQ# GLK_SM_M,, GT_SM_M,, H_STP_PI# H_STP_PU# LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PIE_NEW_ LK_PIE_NEW_# LK_MH_GPLL# LK_MH_GPLL LK_GPLLREQ# MINILK_REQ# LK_PIE_MINI LK_PIE_MINI# NEW-R_LK_REQ# LK_PIE_IH LK_PIE_IH# LK_PIE_MINI LK_PIE_MINI# LK_PIE_LN LK_PIE_LN# LK_PIE_ST LK_PIE_ST# REF_SSLK REF_SSLK# MH_REFLK MH_REFLK# LK_PWRG 0.V R 0K_ PI/TME R *0K_.V R *.K_ PI_F/ITP_EN R.K_ PI_F/ITP_EN PI/TME PULL HIGH ITP/ITP# Overclocking of PU and SR not allowed PULL LOW SR/SR# Overclocking of PU and SR allowed GLK_SEL = FTSEL FTSEL (PIN) PIN 0=UM OT PIN PIN PIN OT# = External VG SR-0 SR-0# Mout-NSS Mout-SS.V SR-/LT_00 SR-#/LT_00 GT_SM_M R 0K_.V Q N00E/H0SPT.V IH_SMT, PU lock select FS FS FS PU SR PI MINILK_REQ# LK_GPLLREQ# ST_LKREQ# MINILK_REQ# NEW-R_LK_REQ# R R R R R0 EMI P *P/0V P/0V P/0V 0P/0V/0G_ P/0V P/0V E -0/0 hange to 0P and R to ohm for meet lock test. 0K_ 0K_ 0K_ 0K_ 0K_.V OZTLK LK_IH_M LK_IH_M PI_LK_ PLK_LP_EUG LK_PI_IH PI R *0K_ PI R *0K_ FTSEL R 0K_ PULL HIGH PIN/ is PU_STOP/PI_STOP PIN/ IS SR. PULL LOW **SR_EN/PI- (Internal Pull Low) R 0K_ Q GLK_SM_M IH_SMLK, N00E/H0SPT PROJET : S Quanta omputer Inc. ocument Number ustom LOK GENERTOR ate: Friday, pril, 00 Sheet of

3 H_#[..] H_ST#0 H_REQ#[0..] H_#[..] H_ST# H_0M# H_FERR# H_IGNNE# H_STPLK# H_INTR H_NMI H_SMI# H_#[..] H_REQ#[0..] H_#[..] H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# U J []# S# L []# NR# L []# PRI# K []# M []# EFER# N []# RY# J []# SY# N [0]# P []# R0# P []# L []# IERR# P []# INIT# P []# R []# LOK# M ST[0]# RESET# K REQ[0]# RS[0]# H REQ[]# RS[]# K REQ[]# RS[]# J REQ[]# TRY# L REQ[]# HIT# Y []# HITM# U []# R []# PM[0]# W [0]# PM[]# U []# PM[]# Y []# PM[]# U []# PRY# R []# PREQ# T []# TK T []# TI W []# TO W []# TMS Y []# TRST# U [0]# R# V []# W []# []# THERML []# []# PROHOT# V ST[]# THERM THERM 0M# FERR# THERMTRIP# IGNNE# R GROUP 0 R GROUP IH STPLK# LINT0 LINT SMI# M RSV[0] N RSV[0] T RSV[0] V RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] F RSV[0] RESERVE XP/ITP SIGNLS ONTROL H LK Penryn all-out a LK[0] LK[] H E G H F E F 0 G E 0 R H_IERR# ITP_PM#0 ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_TK ITP_TI ITP_TO ITP_TMS ITP_TRST# ITP_RESET# H_PROHOT# H_THERM H_THERM H_THERMTRIP_R# H_THERM R H_S# H_NR# H_PRI# H_EFER# H_RY# H_SY# H_R0#.0V_VP H_INIT# H R 0 H_LOK# H_RESET_R# H_RESET# F H_RS#0 F H_RS# G H_RS# G H_TRY# R _ 0 *00P/0V H_HIT# H_HITM# P T P T P T P T P T P T ITP_RESET#.0V_VP P T H_THERM H_THERM R 0_ *./F_ LK_PU_LK LK_PU_LK# H_THERM.0V_VP Layout Note: Place R R close to */F PU. H_THERMTRIP#,.0V_VP H_PROHOT# H_RESET#.0V_VP.0V_VP.V_LW Q Layout Note: Place voltage divider within 0." of GTLREF pin R0 K/F R0 K/F R *.K H_#[0..] H_STN#0 H_STP#0 H_INV#0 H_#[0..], PU_MH_SEL0, PU_MH_SEL, PU_MH_SEL Voltage Level shift H_STN# H_STP# H_INV# IMVP_PROHOT# H_#[0..] H_#[0..] H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_GTLREF PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST R *K/F R0 *K/F PU_TEST PU_TEST *0.U/0V R *0 PU_TEST PU_TEST R *0 PU_TEST U E [0]# F []# E []# G []# F []# G []# E []# E []# K []# G []# J [0]# J []# H []# F []# K []# H []# J STN[0]# H STP[0]# H INV[0]# N []# K []# P []# R []# L [0]# M []# L []# M []# P []# P []# P []# T []# R []# L []# T [0]# N []# L STN[]# M STP[]# N INV[]# GTLREF TEST TEST TEST F TEST F TEST TEST TEST SEL[0] SEL[] SEL[] T GRP 0 T GRP []# Y []# []# V []# V []# V []# T []# U []# U [0]# Y []# W []# Y []# W []# W []# []# []# STN[]# Y STP[]# INV[]# U T GRP []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# STN[]# STP[]# INV[]# T GRP Penryn all-out a OMP[0] R MIS OMP[] U OMP[] OMP[] Y PRSTP# E PSLP# PWR# PWRGOO SLP# PSI# E P T P T H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# E H_# H_# H_#0 H_# H_# H_# 0 H_# E H_# F H_# H_# E H_# H_# H_#0 H_# F H_# H_# E F 0 OMP0 OMP OMP OMP PU_TEST PU_TEST H_#[0..] H_#[0..] H_#[0..] 0 H_STN# H_STP# H_INV# H_#[0..] H_STN# H_STP# H_INV# Note: H_PRTSTP need to daisy chain from IH to IMVP to PU. H_PRSTP#,, H_PSLP# H_PWR# H_PWRGOO H_PUSLP# H_PSI# For the purpose of testability, route these signals through a ground referenced Z0 = ohm trace that ends in a via that is near a GN via and is accessible through an oscilloscope connection. Populate ITP00Flex for bringup.0v_vp *N00W--F R 0 Place close to the PU_TEST pin. Make sure PU_TEST routing is reference to GN and away from other noisy signal. FS LK SEL SEL SEL H_RESET# R0 */F_ ITP_TMS ITP_TI ITP_TO ITP_TK ITP_TRST# *0.U/0V/XR_ R./F_ R./F_ R *./F_ R./F_ R./F_ *0.U/0V/XR_.V_S ITP_RESET# R 0K/F_ E -0 chamge from 0 to 0K for meet Intel spec. *0.U/0V/XR_ ITP00 layout guidelines Signal Resistor Value onnect To Resistor Placement TI. ohm ± % VP Place the pull-up near PU TMS. ohm ± % VP Within 00ps of ITP connector. TRST# ohm ± % GN Place the pull-down near PU onnect to TK pin of PU and then TK. ohm ± % GN connect it to FO pin of ITP connector in daisy chain. Place the pull-down near TK0 pin of ITP connector TO RESET#. ohm ± % VP Place the pull-up near ITP. ohm ± % series resistor and pullup ohm ± %. VP onnect to PURST# pin of GMH through the series resistor placed within 00ps of ITP connector. Place the pull-up after the series resistor from ITP connector. OMP0 OMP OMP OMP R./F omp0, connect with Zo=.ohm,omp, connect with Zo=ohm, make those traces length shorter than 0.".Trace should be at least mils away from any other toggling signal. R./F R./F PROJET : S R./F Quanta omputer Inc. ocument Number ustom Penryn Processor (HOST US) ate: Friday, pril, 00 Sheet of

4 V_ORE V_ORE V_ORE V_ORE V_ORE inside cavity, north side, primary layer. V_ORE 0U/V.0V_VP ll use U 0V(-0%,XR,0)Pb-Free. inside cavity, north side, secondary layer. 0U/V inside cavity, south side, secondary layer. 0 0U/V 0U/V inside cavity, south side, primary layer. 0U/V 0U/V 0U/V 0.U/0V 0U/V 0U/V 0U/V 0U/V 0U/V 0.U/0V 0U/V 0U/V 0U/V 0U/V 0U/V 0U/V 0 0.U/0V Layout out: Place these inside socket cavity on North side secondary. 0 0U/V 0U/V 0U/V 0U/V 0U/V 0U/V 0.U/0V 0U/V 0U/V 0.U/0V 0U/V 0U/V 0U/V 0U/V 0U/V 0U/V 0.U/0V V_ORE PWR_SR *00U/V U V[00] V[0] 0 V[00] V[0] 0 V[00] V[00] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] 0 V[00] V[0] V[00] V[0] V[0] V[0] 0 V[0] V[0] 0 V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[0] E V[0] V[0] E0 0 V[00] V[0] E V[0] V[0] E V[0] V[0] E V[0] V[00] E V[0] V[0] E V[0] V[0] E0 V[0] V[0] F 0 V[0] V[0] F0 V[0] V[0] F V[0] V[0] F V[00] V[0] F V[0] V[0] F V[0] V[0] F E V[0] V[00] F0 E V[0] E0 V[0] VP[0] G E V[0] VP[0] V E V[0] VP[0] J E V[0] VP[0] K E V[0] VP[0] M E V[00] VP[0] J E0 V[0] VP[0] K F V[0] VP[0] M F V[0] VP[0] N F0 V[0] VP[0] N F V[0] VP[] R F V[0] VP[] R F V[0] VP[] T F V[0] VP[] T F V[0] VP[] V F0 V[00] VP[] W V[0] V[0] V[0] 0 V[0] V[0] V[0] V[0] VI[0] V[0] VI[] F V[0] VI[] E V[0] VI[] F 0 V[0] VI[] E V[00] VI[] F 0 V[0] VI[] E 0 V[0] V[0] V[0] VSENSE F V[0] V[0] V[0] VSSSENSE E Penryn all-out a V_ORE VSENSE VSSSENSE and remove in stage P remove in FI stage Layout Note: Need to add 00uF cap on PWR_SR for cap singing. Place on PWR_SR near V_ORE...0V_VP 0U/.V_ VI0 VI VI VI VI VI VI VSENSE VSSSENSE 0.0U/V VSENSE VSSSENSE.V Layout Note: Place 0 near PIN. V_ORE 0U/V R 00/F R 00/F Route VSENSE and VSSSENSE traces at.ohms and length matched to within mil. Place PU and P within inch of PU. U VSS[00] VSS[0] P VSS[00] VSS[0] P VSS[00] VSS[0] P VSS[00] VSS[0] R VSS[00] VSS[0] R VSS[00] VSS[0] R VSS[00] VSS[0] R F VSS[00] VSS[0] T VSS[00] VSS[00] T VSS[00] VSS[0] T VSS[0] VSS[0] T VSS[0] VSS[0] U VSS[0] VSS[0] U VSS[0] VSS[0] U VSS[0] VSS[0] U VSS[0] VSS[0] V VSS[0] VSS[0] V VSS[0] VSS[0] V VSS[0] VSS[00] V VSS[00] VSS[0] W VSS[0] VSS[0] W VSS[0] VSS[0] W VSS[0] VSS[0] W VSS[0] VSS[0] Y VSS[0] VSS[0] Y VSS[0] VSS[0] Y VSS[0] VSS[0] Y VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[] VSS[0] VSS[] VSS[0] VSS[] VSS[0] VSS[] VSS[0] VSS[] E VSS[0] VSS[] E VSS[0] VSS[] E VSS[0] VSS[] E VSS[0] VSS[] E VSS[0] VSS[0] E VSS[00] VSS[] E VSS[0] VSS[] E VSS[0] VSS[] E VSS[0] VSS[] F VSS[0] VSS[] F VSS[0] VSS[] F VSS[0] VSS[] F VSS[0] VSS[] F VSS[0] VSS[] F VSS[0] VSS[0] F VSS[00] VSS[] F VSS[0] VSS[] F VSS[0] VSS[] G VSS[0] VSS[] G VSS[0] VSS[] G VSS[0] VSS[] G VSS[0] VSS[] H VSS[0] VSS[] H VSS[0] VSS[] H VSS[0] VSS[0] H VSS[00] VSS[] J VSS[0] VSS[] J VSS[0] VSS[] J VSS[0] VSS[] J VSS[0] VSS[] E K VSS[0] VSS[] E K VSS[0] VSS[] E K VSS[0] VSS[] E K VSS[0] VSS[] E L VSS[0] VSS[0] E L VSS[00] VSS[] E L VSS[0] VSS[] E L VSS[0] VSS[] E M VSS[0] VSS[] M VSS[0] VSS[] F M VSS[0] VSS[] F M VSS[0] VSS[] F N VSS[0] VSS[] F N VSS[0] VSS[] F N VSS[0] VSS[0] F N VSS[00] VSS[] F P VSS[0] VSS[] VSS[] F Penryn all-out a. 0 PROJET : S Quanta omputer Inc. ocument Number ustom Penryn Processor (POWER) ate: Friday, pril, 00 Sheet of

5 0 PU Thermal monitor Q N00W--F.V.V R 0_ E -0 chamge from 0 to 0 ohm for meet I spec. V 0 LK 0 T THERM_LERT# SYS_SHN# LK.V Q N00W--F T.V Q N00W--F THLK_SM THT_SM R OVERT# R 0K_ *0_ R 0K_ R 0K_ R *0K_ OVERT# T RESS: H Layout Note: Layout Note:Routing 0:0 mils and away from noise source with ground gard U SLK S LERT# V XP XN GN 0.U/0V/XR_ H_THERM 00P/0V_ H_THERM need choice for penryn thermal chip H_THERM H_THERM PU FN 0 PWM_FN R0 0 mil V_FN FNSET V U 0 mil VEN VIN VO SET GN GN GN GN 0 U/0V/XR_ 0 mil 0.U/0V/XR_ V_FN 0U/0V/XR_ N FN 000P/V/XR_ 00K GPU 0.U/0V/XR_.V FNSIG 0 FNSIG Q PTEU R0 00K PROJET : S Quanta omputer Inc. ocument Number ustom Thermal monitor ate: Friday, pril, 00 Sheet of

6 0.0V_VP H_SWING H_ROMP H_#[0..] Layout Note: H_ROMP trace should be 0-mil wide with 0-mil spacing..0v_vp R K/F H_#[0..] 0 <--close pin 0.U/0V R K/F H_RESET# H_PUSLP# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_SWING H_ROMP H_REF U0 F H_#_0 G H_#_ F H_#_ E H_#_ G H_#_ H H_#_ H H_#_ F H_#_ H_#_ H H_#_ M H_#_0 M H_#_ J H_#_ J H_#_ N H_#_ J H_#_ P H_#_ L H_#_ R H_#_ N H_#_ L H_#_0 M H_#_ J H_#_ N H_#_ R H_#_ N H_#_ N H_#_ P H_#_ N H_#_ L H_#_ N0 H_#_0 M H_#_ Y H_#_ H_#_ Y H_#_ Y0 H_#_ Y H_#_ Y H_#_ Y H_#_ W H_#_ H_#_0 Y H_#_ H_#_ H_#_ H_#_ H_#_ 0 H_#_ H_#_ E H_#_ E H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ E H_#_ F H_#_ H_#_ E H_#_ H_#_ E H_#_0 E H_#_ G H_#_ H_#_ H_SWING E H_ROMP H_PURST# E H_PUSLP# H_VREF H_VREF NTIG_p0 HOST H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_S# H_ST#_0 H_ST#_ H_NR# H_PRI# H_REQ# H_EFER# H_SY# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_STN#_0 H_STN#_ H_STN#_ H_STN#_ H_STP#_0 H_STP#_ H_STP#_ H_STP#_ H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_RS#_0 H_RS#_ H_RS#_ F H M J P R N M E P F G0 J E0 H J0 L L J H0 K 0 F K L0 H G F G E 0 H H J F H E H J L Y Y L0 M E L M E K F F H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_#[..] H_#[..] H_S# H_ST#0 H_ST# H_NR# H_PRI# H_R0# H_EFER# H_SY# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#0 H_INV# H_INV# H_INV# H_STN#0 H_STN# H_STN# H_STN# H_STP#0 H_STP# H_STP# H_STP# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_RS#0 H_RS# H_RS# <--LK 0.U/0V R./F R /F R 00/F Layout Note: Place the 0. uf decoupling capacitor within 00 mils from GMH pins. PROJET : S Quanta omputer Inc. ocument Number ustom antiga (HOST) ate: Friday, pril, 00 Sheet of

7 pull up/down impedance compensation For Memory SM_ROMP_VOH 0.0U/V SM_ROMP_VOL 0.0U/V, PU_MH_SEL0, PU_MH_SEL, PU_MH_SEL MH_FG[..0] PM_SYN#,, H_PRSTP#, PM_EXTTS#0 PM_EXTTS#, ELY_VR_PG PLTRST#_N, H_THERMTRIP#, PM_PRSLPVR.U/0V.U/0V.V_SUS R K/F R.0K/F R K/F Layout Note: Location of all MH_FG strap resistors needs to be close to minmize stub. MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG0 MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG0 M RSV N RSV R RSV T RSV H RSV H0 RSV H RSV H RSV K RSV L RSV0 K RSV N RSV M RSV T RSV RSV G RSV F RSV H RSV F RSV T FG_0 R FG_ P FG_ P0 FG_ P FG_ FG_ N FG_ M FG_ E FG_ FG_ FG_0 N FG_ P FG_ T FG_ R0 FG_ M0 FG_ L FG_ H FG_ P FG_ R FG_ T FG_0 R PM_SYN# PM_EXTTS#0 PM_PRSTP# N PM_EXTTS# PM_EXT_TS#_0 P PM_EXT_TS#_ T0 R 00/F_ PLTRST#_R PWROK T H_THERMTRIP# RSTIN# T0 THERMTRIP# R PRSLPVR R 0 Y U0 RSV J RSV M RSV RSV0 T TP_N G TP_N N_ T0 F TP_N N_ T00 TP_N N_ T0 TP_N N_ T0 H T0 TP_N N_ G T TP_N N_ E TP_N N_ T H TP_N N_ T F TP_N0 N_ T G T TP_N N_0 H T TP_N N_ H T0 TP_N N_ H T TP_N N_ H TP_N N_ T G T TP_N N_ H N_ F N_ H.V N_ G N_ E R 0K PM_EXTTS#0 N_0 G R 0K PM_EXTTS# N_ F N_ N_ N_ F N_ NTIG_p0 RSV N PM R ONTROL/OMPENSTION LK MI FG GRPHIS VI ME MIS H S_K_0 S_K_ S_K_0 S_K_ S_K#_0 S_K#_ S_K#_0 S_K#_ S_KE_0 S_KE_ S_KE_0 S_KE_ S_S#_0 S_S#_ S_S#_0 S_S#_ S_OT_0 S_OT_ S_OT_0 S_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF SM_PWROK SM_REXT SM_RMRST# PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# PEG_LK PEG_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_0 GFX_VI_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF P_TRLLK P_TRLT SVO_TRLLK SVO_TRLT LKREQ# IH_SYN# TSTN H_LK H_RST# H_SI H_SO H_SYN P T V U0 R R U V0 Y Y Y V R Y F Y G H SMROMPP SMROMPN F H SM_ROMP_VOH SM_ROMP_VOL V_R_MH_REF V R SM_PWROK R 0_ F R /F SM_RMRST# TP E F F E E E E H E0 E E H0 E E E H E F H G F E H H N J H MH_LVREF M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# R_KE0_IMM, R_KE_IMM, R_KE_IMM, R_KE_IMM, R_S0_IMM#, R_S_IMM#, R_S_IMM#, R_S_IMM#, M_OT0, M_OT, M_OT, M_OT, MH_REFLK MH_REFLK# REF_SSLK REF_SSLK# LK_MH_GPLL LK_MH_GPLL# MI_MRX_ITX_N0 MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_N MI_MRX_ITX_P0 MI_MRX_ITX_P MI_MRX_ITX_P Layout Note: MI_MRX_ITX_P Place 0 ohm termination resistors MI_MTX_IRX_N0 MI_MTX_IRX_N close to GMH. MI_MTX_IRX_N MI_MTX_IRX_N MI_MTX_IRX_P0 MI_MTX_IRX_P MI_MTX_IRX_P MI_MTX_IRX_P T T T T T0 T P P P P P P L_LK0 L_T0 PWROK,0 IH_L_RST0# N P_TRLLK TP M PP_TRLT TP G SVO_TRLLK SVO_TRLLK E SVO_TRLT SVO_TRLT K LK_GPLLREQ# H MH_IH_SYN#.V R0./F_ R0 *0K MH_TSTN E -.0V_VP Z_ITLK_MH Z_ITLK_MH 0 Z_RST#_MH Z_RST#_MH Z_SIN_MH R0 0_ Z_SIN Z_SOUT_MH Z_SOUT_MH Z_SYN_MH Z_SYN_MH INT KLT_TRL INT_LVS_LON.V 0 0 INT_LVS_EILK INT_LVS_EIT INT_LVS_IGON INT_HSYN INT_VSYN Layout Note: HSYN/VSYN serial R place close to N R TXLLKOUT- TXLLKOUT TXULKOUT- TXULKOUT TXLOUT0- TXLOUT- TXLOUT- TXLOUT0 TXLOUT TXLOUT TXUOUT0- TXUOUT- TXUOUT- TXUOUT0 TXUOUT TXUOUT R R R 0 INT_RT_LU 0 INT_RT_GRN 0 INT_RT_RE 0 INT_RT_LK 0 INT_RT_T R R R R PLTRST#_R 0K_ R./F_ K/F_./F_ Non-iMT MH_LVREF L_TRL_LK L_TRL_T INT_LVS_EILK INT_LVS_EIT R 0_ 0/F_ 0/F_ 0/F_ TV_ONSEL_0 TV_ONSEL_ E- change R from.0k to K meet Intel check list. 0K_ 0.U/0V R.0V_VP R K/F For ME Management Engine R *00 M.K/F_ LVS_IG E E 0 /F_ L L_KLT_TRL G L_KLT_EN M L_TRL_LK M L_TRL_T K L LK J L T SMROMPP SMROMPN For Memory L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK H LVS_T#_0 E LVS_T#_ G0 LVS_T#_ 0 LVS_T#_ H LVS_T_0 LVS_T_ F0 LVS_T_ 0 LVS_T_ LVS_T#_0 H LVS_T#_ G LVS_T#_ J LVS_T#_ LVS_T_0 G LVS_T_ F LVS_T_ K LVS_T_ F TV_ H TV_ K TV_ H E G J G INT_RT_LK H INT_RT_T J INT_HSYN J RTIREF E INT_VSYN L R /F R *0 U0 TV_RTN TV_ONSEL_0 E TV_ONSEL_ RT_LUE RT_GREEN RT_RE RT_IRTN RT LK RT T RT_HSYN RT_TVO_IREF RT_VSYN NTIG_p0.V_SUS R 0./F R 0./F install 0. for antiga. install 0 for Teenah. PLTRST#,,, LVS TV PI-EXPRESS GRPHIS VG HMI_HP_ON PEG_OMPI T PEG_OMPO T PEG_RX#_0 H PEG_RX#_ J PEG_RX#_ L PEG_RX#_ L0 PEG_RX#_ N PEG_RX#_ P PEG_RX#_ N PEG_RX#_ T PEG_RX#_ U PEG_RX#_ Y PEG_RX#_0 Y PEG_RX#_ Y PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX_0 H PEG_RX_ J PEG_RX_ L PEG_RX_ L PEG_RX_ N0 PEG_RX_ P PEG_RX_ N PEG_RX_ T PEG_RX_ U PEG_RX_ Y PEG_RX_0 W PEG_RX_ Y PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ 0 PEG_TX#_0 J PEG_TX#_ M PEG_TX#_ M PEG_TX#_ M0 PEG_TX#_ M PEG_TX#_ R PEG_TX#_ N PEG_TX#_ T0 PEG_TX#_ U PEG_TX#_ U0 PEG_TX#_0 Y0 PEG_TX#_ PEG_TX#_ PEG_TX#_ 0 PEG_TX#_ PEG_TX#_ PEG_TX_0 J PEG_TX_ L PEG_TX_ M PEG_TX_ M PEG_TX_ M PEG_TX_ R PEG_TX_ N PEG_TX_ T PEG_TX_ U PEG_TX_ U PEG_TX_0 Y PEG_TX_ Y PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_. ohm for cantiga EXP OMPX PEG_PX_ VO_RE#_ VO_GREEN#_ VO_LUE#_ VO_LK#_ VO_RE_ VO_GREEN_ VO_LUE_ VO_LK_ FOR HME HP (NEE HEK) R *0 R 00K/F_.V R./F V_PEG For UM HMI Function R 0K/F_ PEG_PX_ PROJET : S 0 SVO_RE- SVO_GREEN- SVO_LUE- SVO_LK- SVO_RE SVO_GREEN SVO_LUE SVO_LK Quanta omputer Inc. ocument Number ustom antiga (VG,MI) ate: Friday, pril, 00 Sheet of 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ Q N00W--F R.K/F_

8 R R [0..] U0 R 0 J R S_Q_0 J R S_Q_ N R S_Q_ M R S_Q_ J R S_Q_ J0 R S_Q_ M R S_Q_ M R S_Q_ N R S_Q_ N R 0 S_Q_ U0 R S_Q_0 T R S_Q_ N R S_Q_ N R S_Q_ U R S_Q_ U R S_Q_ V R S_Q_ Y R S_Q_ 0 R S_Q_ R 0 S_Q_ V R S_Q_0 Y R S_Q_ R S_Q_ 0 R S_Q_ Y R S_Q_ R S_Q_ V R S_Q_ T R S_Q_ Y R S_Q_ R 0 S_Q_ V R S_Q_0 W R S_Q_ R S_Q_ U R S_Q_ R S_Q_ R S_Q_ U R S_Q_ V R S_Q_ R S_Q_ R 0 S_Q_ R S_Q_0 R S_Q_ U0 R S_Q_ V R S_Q_ R S_Q_ R S_Q_ Y R S_Q_ R S_Q_ V R S_Q_ V R 0 S_Q_ T R S_Q_0 N R S_Q_ U R S_Q_ U R S_Q_ T R S_Q_ N0 R S_Q_ M R S_Q_ M R S_Q_ J R S_Q_ J R 0 S_Q_ N R S_Q_0 M R S_Q_ J R S_Q_ J S_Q_ NTIG_p0 R SYSTEM MEMORY S_S_0 S_S_ S_S_ S_RS# S_S# S_WE# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_0 S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_0 S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_0 S_M_ S_M_ S_M_ S_M_ R S0 G R S T R S 0 0 Y0 R RS# R S# R WE# M R M0 T R M Y R M U R M R M Y R M T R M J R M J T W U M J T Y U M R QS0 R QS R QS R QS R QS R QS R QS R QS R QS#0 R QS# R QS# R QS# R QS# R QS# R QS# R QS# R M0 R M G R M H R M G R M R M R M G R M F R M W R M R M0 G R M H R M H R M Y R M R S0, R S, R S, R RS#, R S#, R WE#, R M[0..] R QS[0..] R QS#[0..] R M[0..], R [0..] U0E R 0 K R S_Q_0 H R S_Q_ P R S_Q_ P R S_Q_ J R S_Q_ J R S_Q_ M R S_Q_ P R S_Q_ U R S_Q_ U R 0 S_Q_ R S_Q_0 Y R S_Q_ T R S_Q_ R R S_Q_ R S_Q_ R S_Q_ R S_Q_ R S_Q_ G R S_Q_ F R 0 S_Q_ E R S_Q_0 R S_Q_ F0 R S_Q_ F R S_Q_ G R S_Q_ F R S_Q_ H R S_Q_ G R S_Q_ H0 R S_Q_ G R 0 S_Q_ G R S_Q_0 H R S_Q_ H R S_Q_ G R S_Q_ H R S_Q_ G R S_Q_ H R S_Q_ F R S_Q_ F R S_Q_ G R 0 S_Q_ R S_Q_0 R S_Q_ Y R S_Q_ Y R S_Q_ F R S_Q_ F R S_Q_ R S_Q_ R S_Q_ V R S_Q_ U R 0 S_Q_ R R S_Q_0 N R S_Q_ Y R S_Q_ V R S_Q_ P R S_Q_ R R S_Q_ L R S_Q_ L R S_Q_ J R S_Q_ H R 0 S_Q_ M R S_Q_0 M R S_Q_ H R S_Q_ J S_Q_ NTIG_p0 R SYSTEM MEMORY S_S_0 S_S_ S_S_ S_RS# S_S# S_WE# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_0 S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_0 S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_0 S_M_ S_M_ S_M_ S_M_ R S0 R S R S U R RS# G R S# F R WE# M R M0 Y R M 0 R M F R M G R M R M P R M K R M L R QS0 V R QS G R QS G R QS H R QS R QS U R QS N R QS L R QS#0 V R QS# H R QS# H R QS# G R QS# R QS# T R QS# N R QS# V R M0 R M R M U R M W R M R M U R M W R M T R M R M R M0 W R M Y R M H R M U R M 0 R S0, R S, R S, R RS#, R S#, R WE#, R M[0..] R QS[0..] R QS#[0..] R M[0..], STRPPING FG FG FG FG FG0 FG FG FG0 MI X Select itpm Host Interface Intel Management Engine rypto Strap PI Express Graphic Lane PIe Loopback Enable FS ynamic OT MI Lane ersal igital isplay Port(SVO/P/iHMI) and PIe oncurrent Operation. FG FG XOR / LLZ / lock Un-gating Low=MIx High=MIx(efault) Low= Enable High=isable(efault) Low= Intel Management Engine rypto TLS cipher suite with no onfidentiality High=Intel Management Engine rypto TLS cipher suite with onfidentiality(efault) Low= eise Lane High=Normal operation Low= Enable High=isable(efault) Low=ynamic OT isable High=ynamic OT Enable(default). Low=Normal(default). High=Lane ersed Low=Only P or inly PIe is operational (defaults) High=P and PIe x are operating simultaneously. 00=Reserved. 0=XOR Mode Enabled. 0=ll-Z Mode Enabled. =Normal Operation (efault)..v R0 R R R R R0 R R R R P T P T *.K/F *.K/F *.K/F P T *.K/F *.K/F P T *.K/F *.K/F P T P T *.K/F P T P T *.0K/F.K/F MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG0 MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG MH_FG0 ocument Number ustom antiga (R,STRPPING) MH_FG[..0] PROJET : S Quanta omputer Inc. ate: Friday, pril, 00 Sheet of

9 .V_SUS.0V_VP U0G P V_SM_ N V_SM_ H V_SM_ G V_SM_ F V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ Y V_SM_0 W V_SM_ V V_SM_ U V_SM_ T V_SM_ R V_SM_ P V_SM_ N V_SM_ H V_SM_ G V_SM_ F V_SM_0 G0 V_SM_ H V_SM_ G V_SM_ F V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ Y V_SM_ W V_SM_0 V V_SM_ U V_SM_ T V_SM_ R V_SM_ P V_SM_ V_SM_/N V_SM_/N V_SM_/N V_SM_/N W V_SM_0/N W V_SM_/N T V_SM_/N Y V_XG_ E V_XG_ V_XG_ V_XG_ E V_XG_ V_XG_ V_XG_ Y V_XG_ E V_XG_ V_XG_0 V_XG_ V_XG_ J V_XG_ G V_XG_ E V_XG_ V_XG_ V_XG_ Y V_XG_ H0 V_XG_ F0 V_XG_0 E0 V_XG_ 0 V_XG_ 0 V_XG_ 0 V_XG_ T V_XG_ T V_XG_ M V_XG_ L V_XG_ E V_XG_ J V_XG_0 H V_XG_ G V_XG_ F V_XG_ V_XG_ V_XG_ Y V_XG_ V V_XG_ U V_XG_ N V_XG_ M V_XG_0 U V_XG_ T V_XG_ J V_XG_SENSE H VSS_XG_SENSE POWER V SM V GFX V GFX NTF V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V SM LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF W V W V W V W V W V M L K W V U M0 K0 W0 U0 M L K J H G F E Y W V U M K H G F E Y W V M L K J H G F E Y W V U V M0 V Y M0.0V_VP VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF.V_SUS.0V_VP E -0 N 0U Layout Note: Place close to GMH. Place close to the MH Layout Note: Place where LVS and R taps. Layout Note: Inside GMH cavity. N Power Status and max current table(/) POWER PLNE S0 S S/S Voltage I(max) 0 0.U/0V V(EXT_VG) O X X.0V V(INT_VG) O X X.0V m V_XG O X X.0V 00m Graphics ore V_SM(00) O O X.VSUS (RII-). V_SM(Standby) O (See N ES :.0 Section 0. for max current) (See N ES :.0 Section. for voltage) 00 0.U/0V E -0 N 0U 0U/.V_ 0.U/0V R 0.00/F 0.U/0V *0U/.V_ O 0.U/0V X 0.U/0V.VSUS 0 *0U/.V_ 0.U/0V 0U/.V U/V.0V_VP m m 0 U/0V avity apactors V_SM Layout Note: Place on the edge. U/0V U/V 0.U/0V U/0V Note Self Refresh during S 0U/.V U/V 0.U/0V U/V 0.U/0V 0 0.U/0V U0F G V_ V_ V_ V_ Y V_ V V_ U V_ M V_ K V_ J V_0 G V_ F V_ E V_ V_ V_ Y V_ W V_ V V_ U V_ H V_0 F V_ V_ V_ J V_ G V_ E V_ V_ H V_ G V_ F V_0 G V_ J V_ H V_ F R 0 V_ T V_ 0.U/0V NTIG_p0 V ORE POWER V NTF V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ M L K J H G E Y W U M0 L0 K0 H0 G0 F0 E Y0 W0 V0 U0 L K J H G E Y W V L K L K K K K 0.0V_VP NTIG_p0 PROJET : S Quanta omputer Inc. ocument Number ustom antiga (V,NTF) ate: Friday, pril, 00 Sheet of

10 .0V_VP 0mil L L.0V_VP 0mil L L V.0M_MH_PLL R 0mil.0V For Teenah 0uH/00M_ 0U/V_ESR_ 0U/V_ESR_ 0U/.V_ 0uH/00M_ LMS_.U/.V_ LMS_.U/0V_.U/0V_.U/0V_ 0./F_ V_PLL V_PLL V_HPLL V_MPLL.U/0V_.V.V.V.V.0V For Teenah 0mil.0V_VP.0V_VP L LMPGSN_ R 0.0/F_0 R For Teenah R 0_ For antiga R 0_ *0U/.V_ E -0 N 0U *0_ 0.U/0V_ int m V_RT 0.0U/V_ int u m.m R *0_ des 000P/0V_ V_PEG_G.U/0V_ 0m V_RT V_RT V_TVG V G 0 0 R VSS G.U/0V_.0U/V_ *0_ int int des V_PLL F total.m V_PLL V_PLL L V_PLL m V_HPLL V_HPLL.m V_MPLL E V_MPLL.m V_TX_LVS J V_LVS VSS_LVS V_PEG_G.U/0V_ V_PEG_PLL V_PEG_PLL 0m V.0M SM R0 V_SM_ P0 V_SM_ N0 0U/.V_ 0U/.V_ 0U/.V_ V_SM_ R V_SM_ P V_SM_ N V_SM_ T V_SM_ R 0U/.V_.U/.V_ U/.V_ V_SM_ P V_SM_ J U0H RT PLL LVS PEG SM POWER VTT VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ U T U T U T U0 T0 U T U T U T U T U T V U V U T V U.U/.V_ V_XF V_SM_K V_TX_LVS m.u/.v_ 0 U/.V_ 0U/.V_ des R00 *0_ R 0_ 0U/.V_.U/0V_.U/.V_ V_SM_K_L.0V_VP VP_GMH.0V For Teenah.V_SUS L uh/00m_ 0mil uh-0%_00m R /F_ 0U/.V_.U/.V_ 000P/0V_ 0U/.V_ 0 uh-0%_00m.0v_vp R 0_ 0mil *0U/.V_ L0 int 0U/.V_ E -0 N 0U.V_SUS uh/00m_ 0mil.V 0mil 0mil 0mil R 0_ L.U/0V_.0V_VP V_TV_R VQ_Q_R LMPGSN.U/0V_ int.u/0v_ int.0u/v_ int L *nf/v_ LMPGSN 0 U/.V_ int.0v For Teenah V_PEG_PLL V.0S_PEGPLL_F 0mil R /F_ R 0_ ~0mil.U/.V_ L.V 0mil LMPGSN int V_SM_K V_TV_R.V R 0_ V_H 0mil int V_H 0 R0.U/0V_ *0_.m int des.m V_TV_R M V_TV 0mil.m VQ_Q_R L V_Q 0m V.0M_MH_PLL F V_HPLL.U/0V_ V_PEG_PLL 0 0.m V_PEG_PLL 0mil.U/0V_ M V_LVS_ L V_LVS_.V_SUS R0 0_ 0mil int 0U/.V_ 0U/.V_.U/0V_.m 00 0U/.V_.U/0V_ int int R *0_ des 0m V_LVS R 0 *0_ U/.V_ int 0U/.V_ des int P V_SM_K_ N V_SM_K_ P V_SM_K_ N V_SM_K_ N V_SM_K_ M V_SM_K_NTF_ M V_SM_K_NTF_ M V_SM_K_NTF_ L V_SM_K_NTF_ M V_SM_K_NTF_ L V_SM_K_NTF_ M V_SM_K_NTF_ L V_SM_K_NTF_ V_TV V_TV NTIG_p0 VTTLF VTTLF VTTLF TV H LVS K TV/RT XF SM K MI V_XF_ V_XF_ V_XF_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ HV PEG V_TX_LVS VTTLF V_HV_ V_HV_ V_HV_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_MI_ V_MI_ V_MI_ V_MI_ VTTLF VTTLF VTTLF F H0 G0 F0 K V U V U U H F H G L.m.m V_V_HV VTTLF VTTLF VTTLF 0.m.U/0V_ V_RXR_MI m V_V_HV.U/0V_.U/.V_ V_PEG m E -0 N 0U.U/0V_ R 0_ int.0v_vp *0U/V_ H0H-0PT R.V 0_ 0mil R0 0_ 0U/.V_ R 0_ 0mil 0mil E - /0 el L,L dd R0,R 0 0 ohm..0v_vp.0v_vp 0U/.V_ 0.U/.V_.U/.V_.U/.V_ PROJET : S Quanta omputer Inc. ocument Number ustom antiga (POWER) ate: Friday, pril, 00 Sheet 0 of

11 PROJET : S Quanta omputer Inc. ate: Sheet of ocument Number ustom antiga (VSS) Friday, pril, 00 PROJET : S Quanta omputer Inc. ate: Sheet of ocument Number ustom antiga (VSS) Friday, pril, 00 PROJET : S Quanta omputer Inc. ate: Sheet of ocument Number ustom antiga (VSS) Friday, pril, 00 VSS_ G VSS_0 W VSS_0 U VSS_0 P VSS_0 N VSS_0 H VSS_0 F VSS_0 VSS_0 R VSS_0 M VSS_0 J VSS_ G VSS_ 0 VSS_ 0 VSS_ W0 VSS_ T0 VSS_ J0 VSS_ G0 VSS_ Y0 VSS_ N0 VSS_0 K0 VSS_ F0 VSS_ 0 VSS_ 0 VSS_ G VSS_ VSS_ G VSS_ VSS_ W VSS_ T VSS_0 R VSS_ M VSS_ H VSS_ VSS_ VSS_ U VSS_ N VSS_ N VSS_0 K VSS_ G VSS_ E VSS_ G VSS_ W VSS_ VSS_ G VSS_ VSS_ VSS_0 G VSS_ VSS_ VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_0 G VSS_ E VSS_ F VSS_ V VSS_ T VSS_ M VSS_ VSS_ J VSS_ VSS_ VSS_0 VSS_ Y VSS_ N VSS_ H VSS_ Y VSS_ N VSS_ G VSS_ VSS_ G0 VSS_0 V0 VSS_ T0 VSS_ J0 VSS_ E0 VSS_ 0 VSS_ H VSS_ VSS_ G VSS_0 VSS_ M VSS_ N VSS_ VSS_ M0 VSS_ F VSS_ H VSS_ Y VSS_ L VSS_00 E VSS_0 VSS_0 Y VSS_0 U VSS_0 N VSS_0 J VSS_0 E VSS_0 VSS_0 N VSS_0 J VSS_0 G VSS_ VSS_ V VSS_ T VSS_ VSS_ M VSS_ M VSS_ VSS_ VSS_ H VSS_ VSS_0 Y VSS_ L VSS_ J VSS_ H VSS_ F VSS_ E VSS_ VSS_ V VSS_ L VSS_NTF_ F VSS_NTF_ VSS_NTF_ V VSS_NTF_ J0 VSS_NTF_ M VSS_NTF_ F VSS_NTF_ VSS_NTF_ U VSS_NTF_ U VSS_NTF_0 L0 VSS_NTF_ V0 VSS_NTF_ VSS_NTF_ L VSS_NTF_ J VSS_NTF_ VSS_NTF_ U VSS_S_ H VSS_S_ H VSS_S_ VSS_S_ VSS_S_ VSS_S_ N_ E N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ N_ N_ N_ F N_0 E N_ N_ VSS_0 R VSS_ P VSS_ VSS_ R VSS_ U VSS_ P VSS_ F VSS_ W VSS_ E VSS_0 F VSS_ H VSS_ J VSS_ VSS_ VSS_ Y VSS_ M VSS_ K VSS_ M VSS_ VSS_ P VSS_0 H VSS_ VSS_ V VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_00 L VSS VSS NTF VSS S N U0J NTIG_p0 VSS VSS NTF VSS S N U0J NTIG_p0 VSS_ U VSS_ VSS_ R VSS_ L VSS_ VSS_ W VSS_ N VSS_ J VSS_ F VSS_ VSS_0 VSS_ Y VSS_ T VSS_ N VSS_ L VSS_ G VSS_ VSS_ VSS_ V VSS_0 R VSS_ M VSS_ V VSS_ R VSS_ P VSS_ H VSS_ F VSS_ F VSS_ H VSS_ VSS_0 VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ F VSS_ VSS_ V VSS_ U VSS_ M VSS_0 J VSS_ VSS_ G VSS_ Y VSS_ T VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_0 VSS_ U VSS_ M VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_0 G VSS_ VSS_ G0 VSS_ 0 VSS_ V0 VSS_ N0 VSS_ H0 VSS_ E0 VSS_ T VSS_ M VSS_0 J VSS_ E VSS_ N VSS_ L VSS_ VSS_ H VSS_ VSS_ VSS_ U VSS_ H VSS_0 VSS_ VSS_ Y VSS_ U VSS_ T VSS_ J VSS_ F VSS_ VSS_ VSS_00 M VSS_0 E VSS_0 P VSS_0 L VSS_0 J VSS_0 F VSS_0 VSS_0 H VSS_0 VSS_0 Y VSS_0 U VSS_ T VSS_ F VSS_ M VSS_ J VSS_ F VSS_ E VSS_ W VSS_ VSS_ VSS_0 G VSS_ VSS_ VSS_ V VSS_ R VSS_ L VSS_ H VSS_ VSS_ P VSS_ L VSS_0 H VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ N VSS_ T VSS_ N VSS_ K VSS_0 H VSS_ F VSS_ VSS_ G VSS_ VSS_ VSS_ V VSS_ T VSS_ R VSS_ J VSS_0 G VSS_ E VSS_ VSS_ Y VSS_ P VSS_ K VSS_ H VSS_ F VSS_ VSS_ F VSS_0 H VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ H VSS_ VSS_ VSS_ V VSS_0 R VSS_ J VSS_ VSS_ Y VSS_ N VSS_ L VSS_ J VSS_ G VSS_ E VSS_ F VSS_ F VSS_ VSS_0 W VSS_ T VSS_ N VSS_ J VSS_ H VSS_ VSS_ G VSS_ U VSS_ T VSS_ H VSS_ VSS_ L VSS_ Y VSS_ G VSS_ E VSS_ G VSS_ VSS_ Y VSS_ J VSS_ F VSS_ R VSS_ K VSS_0 J VSS_ F VSS_ H VSS_ Y VSS_ K VSS_0 VSS U0I NTIG_p0 VSS U0I NTIG_p0

12 R ual channel / PU 0.V_R_VTT RII HNNEL Layout note: Place cap close to every R-pack terminated to SMR_VTERM U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.V_R_VTT RII HNNEL U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.V_R_VTT 0.V_R_VTT,, R M[0..] R M[0..], R M R M RP X RP0 X R M R M R M R M RP X RP X R M R M, R RS#, R S RP X RP0 X R S, R RS#,, M_OT0 R M RP X RP X R M M_OT,, R S R M RP X RP X R M R M Please these resistor closely IMM,all trace length<0 mil. R M R M RP X RP X R M R M Please these resistor closely IMM,all trace length<0 mil. R M R M RP X RP X R M R M, R S0 R M0 R S0 RP X RP X R M0 R S0,, R S#, R WE# RP X RP X R WE#, R S#, R M0 R M RP X RP X R M R M0, M_OT, R_S0_IMM#, R_S_IMM#, R_KE0_IMM, R_KE_IMM, R M R M R _ R _ R _ R _ R _ R _ R0 _ R _ R _ R _ R0 _ R _ R _ R _ M_OT, R S, R_S_IMM#, R_S_IMM#, R_KE_IMM, R_KE_IMM, R M, R Thermal Sensor SO-IMM 0 &.V Uninstall.V,,,,0,,,,,,,,0,,,,,,,0,,,,0,, GLK_SM_M,, GT_SM_M, PM_EXTTS#0 PM_EXTTS# R *0_ U SLK V S XP LERT# XN OVERT# GN *LMIMM R *0_ LM_V 0 *0.U/0V/XR_ R_THERM R_THERM *MMT0_NL Q PROJET : S Quanta omputer Inc. ocument Number ustom R RES. RRY ate: Friday, pril, 00 Sheet of

13 GT_SM_M GLK_SM_M R M R QS R QS# R R R M R M R M0 R M R 0 R R M R R M R R R M R R R R R QS0 R QS R 0 R R R R R R 0 R R QS#0 R QS R R R R QS# R QS# R QS R QS# R R R R R R R R R 0 R M R R M R M R M R M R M0 R R R QS R R M R QS R QS# R M R M0 R QS# R R M R R R R QS# R M R R R 0 R R R R R R R R R R 0 R R R R R R R M R QS R M R R R 0 R R R R M GLK_SM_M GT_SM_M R M R QS R QS# R R R M R M R M R M0 R R R M R R M R R R R R QS0 R QS R 0 R R R R R 0 R R QS#0 R QS R R R R QS# R QS# R QS R QS# R R R R R R 0 R 0 R R M R M R M R R QS R QS# R R R R M R M R M R M R M R M R M0 R M R R R M R R R R QS# R QS R R R R R M R R R R 0 R QS# R QS R R R R R R R M R R R R R M0 R R R R R 0 R R 0 R R R R [0..] R M[0..] R [0..] R M[0..] R M, R M, R M[0..], R M[0..], R_S_IMM#, M_OT, R S, R S#, R WE#, R S0, R_KE0_IMM, R_S0_IMM#, R QS#[0..] R S, M_LK_R0 R RS#, R QS[0..] R_KE_IMM, M_LK_R# M_LK_R M_OT0, M_LK_R#0 R_S_IMM#, R S, M_OT, R S#, R WE#, R S0, R_KE_IMM, R QS#[0..] R QS[0..] R_S_IMM#, R S, R RS#, R_KE_IMM, M_OT, M_LK_R M_LK_R# M_LK_R# M_LK_R PM_EXTTS#0, PM_EXTTS#0, GT_SM_M,, GLK_SM_M,, V_R_MH_REF,.V,,,,0,,,,,,,,0,,,,,,,0,,,,0 V_R_MH_REF.V.V_SUS.V V_R_MH_REF.V_SUS.V_SUS.V_SUS.V V_R_MH_REF.V_SUS.V_SUS V_R_MH_REF.V.V_SUS.V.V_SUS PROJET : S Quanta omputer Inc. ate: Sheet of ocument Number ustom R SO-IMM(00P) Friday, pril, 00 PROJET : S Quanta omputer Inc. ate: Sheet of ocument Number ustom R SO-IMM(00P) Friday, pril, 00 PROJET : S Quanta omputer Inc. ate: Sheet of ocument Number ustom R SO-IMM(00P) Friday, pril, 00 LOK 0, LOK, KE, KE 0, R ual channel / ONN SMbus address 0 is required to route to Top SoIMM for MT to function.this will need to change for M0 Place these aps near So-imm. Place these aps near So-imm. SMbus address.u/.v/xr_.u/.v/xr_ 0.U/.V/XR_ 0.U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ VREF VSS Q0 Q VSS QS#0 QS0 VSS Q Q VSS Q Q VSS QS# QS VSS Q0 Q VSS0 VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE0 V N _ V V 0 V0 0 0/P WE# 0 V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q0 Q VSS Q Q VSS M0 0 VSS Q Q VSS Q 0 Q VSS M VSS K0 0 K0# VSS Q Q VSS 0 VSS0 Q0 Q VSS N 0 M VSS Q Q VSS 0 Q Q VSS QS# QS 0 VSS0 Q0 Q VSS KE 0 V V 0 V V 0 0 RS# 0 S0# 0 V OT0 V N 0 VSS Q Q VSS M 0 VSS Q Q VSS Q 0 Q VSS VSS M VSS Q Q VSS0 Q Q VSS NTEST VSS0 QS# QS VSS Q0 Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS 0 Q Q VSS Q Q 0 VSS K K# VSS M 0 VSS Q Q VSS Q0 0 Q VSS QS# QS VSS 0 Q Q VSS S0 S 00 VSS P00 R SRM SO-IMM (00P) N IMM_. P00 R SRM SO-IMM (00P) N IMM_. 0.U/0V/XR_ 0.U/0V/XR_ 0 0.U/0V/XR_ 0 0.U/0V/XR_.U/.V/XR_.U/.V/XR_ 0 0.U/0V/XR_ 0 0.U/0V/XR_ R0 0K_ R0 0K_ R 0K_ R 0K_ 0 0.U/0V/XR_ 0 0.U/0V/XR_ 0.U/.V/XR_ 0.U/.V/XR_.U/.V/XR_.U/.V/XR_ VREF VSS Q0 Q VSS QS#0 QS0 VSS Q Q VSS Q Q VSS QS# QS VSS Q0 Q VSS0 VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE0 V N _ V V 0 V0 0 0/P WE# 0 V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q0 Q VSS Q Q VSS M0 0 VSS Q Q VSS Q 0 Q VSS M VSS K0 0 K0# VSS Q Q VSS 0 VSS0 Q0 Q VSS N 0 M VSS Q Q VSS 0 Q Q VSS QS# QS 0 VSS0 Q0 Q VSS KE 0 V V 0 V V 0 0 RS# 0 S0# 0 V OT0 V N 0 VSS Q Q VSS M 0 VSS Q Q VSS Q 0 Q VSS VSS M VSS Q Q VSS0 Q Q VSS NTEST VSS0 QS# QS VSS Q0 Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS 0 Q Q VSS Q Q 0 VSS K K# VSS M 0 VSS Q Q VSS Q0 0 Q VSS QS# QS VSS 0 Q Q VSS S0 S 00 VSS GN 0 P00 R SRM SO-IMM (00P) N IMM_. P00 R SRM SO-IMM (00P) N IMM_..U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ R 0K_ R 0K_.U/.V/XR_.U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ R 0K_ R 0K_.U/.V/XR_.U/.V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0 0.U/0V/XR_ 0 0.U/0V/XR_.U/.V/XR_.U/.V/XR_ *0U/.V_ *0U/.V_

14 V_LW H0H-0PT VRT_ T R0 VRT_ *.K_0 R0 *.K/0.V_LW R0 *K/0 ST_LE# R0 K/F_ N RT_ON. VRT_ IH_Z_M_ITLK IH_Z_OE_ITLK Z_ITLK_MH IH_Z_M_SYN IH_Z_OE_SYN Z_SYN_MH IH_Z_M_RST# IH_Z_OE_RST# Z_RST#_MH 0MIL H0H-0PT RT_ELL 0MIL Q RT_ELL.V U/.V_ R U/.V_ P/0V_.KHZ IH_ST_LE# Z Interface( M, OE, HMI) R R *MMT0 R 0_ 0 *P/0V U Z_IT_LK Z_SYN Z_RST# RTRST# IH_SRTRST# SM_INTRUER# RT IH_RTX IH_RTX R Z_SOUT IH_Z_M_SOUT R IH_Z_OE_SOUT R0 _ Z_SOUT_MH Place all series terms close to IH except for SIN input lines,which should be close to source.placement of R0, R00, R0 & R should equal distance to the T split trace point as R0, R, R0 & R0 respective. asically,keep the same distance from T for all series termination resistors..u/0v_ Y R R R0 _ *P/0V 0K/F_ M/F_ *TSH0FU P/0V_ R0 0K/F_ R R R _ R R0 R _ 0K/F_ R 0M_ U/.V_ Reserved for Intel Nineveh T P design. T P T P T P T0 P T P.V_S.V_PIE_IH Z_IT_LK Z_SYN Z_RST# IH_Z_OE_SIN0 IH_Z_M_SIN T P Z_SIN H O Z_SOUT T0 change Name in stage T0 P from LN_ISLE_# to GPIO.V T P R 0K IH_RTX IH_RTX RTRST# IH_SRTRST# SM_INTRUER# IH_INTVRMEN LN00_SLP GLN_LK LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX ENERGY_ET Z_IT_LK Z_SYN Z_RST# Z_SOUT GPIO R *0K IH_ST_LE# ST_TX0-_ ST_TX0_ ST_TX-_ ST_TX_ LN00_SLP RT_ELL LN00_SLP IH-M LN00_SLP Strap (Internal VR for VccLN_0 and VccL.0) RTX RTX RTRST# F0 SRTRST# INTRUER# INTVRMEN LN00_SLP E GLN_LK Low = Internal VR disable High = Internal VR enable(efault) LN_RSTSYN F LN_RX0 G LN_RX LN_RX LN_TX0 LN_TX E LN_TX 0 R./F GLN_OMP_S F H_IT_LK H H_SYN E H_RST# F H_SIN0 G H_SIN H H_SIN E H_SIN G G U GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_SOUT G H_OK_EN#/GPIO E H_OK_RST#/GPIO STLE# J ST0RXN H ST0RXP F ST0TXN G ST0TXP H STRXN J STRXP G STTXN F STTXP IHM REV.0 R K/F_ R *0_ RT LP LN / GLN PU IH ST LRQ#0 RIN# GTE0 RT_ELL R 0K_ R0 0K_ ST_TX-_ ST_TX_ R 0K_ R 0K_ ST_TX-_ ST_TX_ IH_INTVRMEN IHM Internal VR Enable Strap (Internal VR for VccSus.0, VccSus., VccL.) IH_INTVRMEN S Strap FWH0/L0 K FWH/L K FWH/L L FWH/L K FWH/LFRME# K LRQ0# J LRQ#/GPIO J 0GTE N 0M# J H_PRSTP# PRSTP# J H_PSLP# PSLP# E R H_FERR# FERR# J PUPWRG IGNNE# F INIT# E INTR G RIN# L NMI F SMI# F STPLK# H H_THERMTRIP_R THRMTRIP# G TP G STRXN H STRXP J STTXN G STTXP F STRXN H STRXP J STTXN E0 STTXP F0 ST_LKN H ST_LKP J STRIS# J STRIS H R K/F R *0 Low = Internal VR isabled High = Internal VR Enabled(efault) R./F ST_IS LP_L0,0 LP_L,0 LP_L,0 LP_L,0 LP_LFRME#,0 GTE0 0 H_0M# H_PRSTP#,, H_PSLP# H_FERR# H_IGNNE# H_INIT# H_INTR RIN# 0 H_NMI H_SMI# H_STPLK# R./F H_THERMTRIP# P P P P P T T T T T Place within 00mils of IH ball P T P T0 LK_PIE_ST# LK_PIE_ST IH TP 0 0 H_PWRGOO 0 H_PRSTP# H_FERR# GTE0 RIN# H_THERMTRIP#, H_THERMTRIP# H_PWRGOO.V Z_SOUT XOR hain Entrance Strap H SOUT escription 0 *000P/V/XR_ R *K R *K RSV Enter XOR hain Normal Operation (efault) Set PIE port config bit R0 * R0.K_.0V_VP.V.0V_VP IH_TP R R 0K R -TX for ST E -0,,, hange to 0nF in Stage. ST_TX0- ST_TX0 ST_RX0- ST_RX0 ST_RX- ST_RX ST_TX- ST_TX 0.0U/V/XR_ 0.0U/V/XR_ 0.0U/V/XR_ 0.0U/V/XR_ ST_TX0-_ ST_TX0_ ST_TX-_ ST_TX_ istance between the IH- M and cap on the "P" signal should be identical distance between the IH- M and cap on the "N" signal for same pair. PROJET : S Quanta omputer Inc. ocument Number ustom IH-M (PU,IE,ST,LP,,LN) ate: Friday, pril, 00 Sheet of

15 .V_SUS.V_SUS.V_S O# pull up US_O# US_O# O# US_O0# PI Pullups PI_PIRQ# GPIO PI_IRY# PI_PIRQ#.V PI_PERR# PI_PIRQ# PI_PIRQ# PI_SERR#.V [0..] PI_PIRQ# T0 T T.V 0 RP0 0PR-0K R0 R R R0 R PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ#.V_SUS US_O# O# WLN_RF_OFF# US_O# 0K O0# 0K O# 0K O# 0K US_O# 0K PI_PME# E -0 / dd R PI_PME# onnect to.v_s 0 0 R0 RP 0PR-.K RP 0PR-.K.K_.V PI_FRME# PI_TRY# PI_PLOK# PI_EVSEL# PI_STOP#.V IH_GPIO_PIRQG# PI_REQ0# IH_GPIO_PIRQH# GPIO U 0 E E E0 G 0 F F E F0 0 F 0 F F G H G H G 0 H J PIRQ# E PIRQ# J PIRQ# PIRQ# PI REQ0# GNT0# REQ#/GPIO0 GNT#/GPIO REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO /E0# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# Interrupt I/F IHM REV.0 PIRQE#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO Place TX blocking caps close IH. PIE_RX-/GLN_RX- PIE_RX/GLN_RX PIE_TX-/GLN_TX- PIE_TX/GLN_TX PIE_RX- PIE_RX Miniard- (WLN) PIE_TX- PIE_TX PI_REQ0# PI_GNT0# OR_I PI_GNT# OR_I PI_GNT# OR_I PI_GNT# E0# /E# /E# /E# PI_IRY# PI_PR PI_EVSEL# PI_PERR# PI_PLOK# PI_SERR# PI_STOP# PI_TRY# PI_FRME# PLTRST#_N LK_PI_IH R PI_PME# PIE_RX- PIE_RX Miniard- PIE_TX- PIE_TX PIE_RXN PIE_RXP Express ard (NEWR) PIE_TXN PIE_TXP F G F F E F E R E J F H GPIO K GPIO F IH_GPIO_PIRQG# G IH_GPIO_PIRQH# PI_REQ0# PI_GNT0# OR_I T OR_I T OR_I LK_PI_IH PI_PME# 0.U/0V/XR_ 0.U/0V/XR_ US_O0# US_O# US_O#, WLN_RF_OFF#.V_SUS T T T T PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ T0 T T T GLN_TXN_ GLN_TXP_ SPI_LK_R SPI_S#0_R SPI_S#_R SPI_MOSI_R SPI_MISO_R US_O0# US_O# US_O# US_O# US_O# US_O# WLN_RF_OFF# O# O# O# O0# O#./F US_RIS_PN placed within 00-mils of the IHM /E0# LK_PI_IH /E# /E# /E# R PI_IRY# Reserved for EMI. _ PI_PR Place resister and cap PIRST# 0, close to IH. PI_EVSEL# PI_PERR# P/0V/NPO_ PI_PLOK# PI_SERR# PI_STOP# PI_TRY# PI_FRME# E - / mount R and for EMI request. T T T T 0 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ 0.U/0V/XR_ R U0 TSH0FU(F) PLTRST#_N E -0 change to.v_sus for test 0.U/0V/XR_ R 00K_ PLTRST#,,, U N PERN N PERP P PETN P PETP L PERN L PERP M PETN M PETP J PERN J PERP K PETN K PETP G PERN G PERP H PETN H PETP SPI_HOL# MI0RXN V MI0RXP V MI0TXN U MI0TXP U MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP E PERN MI_LKN T E PERP MI_LKP T F PETN F PETP MI_ZOMP F MI_IROMP F PERN/GLN_RXN PERP/GLN_RXP USP0N PETN/GLN_TXN USP0P PETP/GLN_TXP USPN USPP SPI_LK USPN SPI_S0# USPP F SPI_S#/GPIO/LGPIO USPN USPP SPI_MOSI USPN E SPI_MISO USPP USPN N O0#/GPIO USPP N O#/GPIO0 USPN W N O#/GPIO US USPP W P O#/GPIO USPN Y M O#/GPIO USPP Y N O#/GPIO USPN W M O#/GPIO0 USPP W M O#/GPIO USPN V N O#/GPIO USPP V N O#/GPIIO USP0N U P O0#/GPIO USP0P U P O#/GPIO USPN U USPP U G USRIS G USRIS# IHM REV.0 R0 0K/F_ PI-Express SPI irect Media Interface SPI_S#_R PI_GNT0#.V VSS R MI_IROMP_R USP- USP IH_USP0- IH_USP0 IH_USP- IH_USP R *K 0.U/0V/XR_ R *K SPI_WP# WP# K byte SPI ROM For HP only MI_MTX_IRX_N0 MI_MTX_IRX_P0 MI_MRX_ITX_N0 MI_MRX_ITX_P0 MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P MI_MTX_IRX_N MI_MTX_IRX_P MI_MRX_ITX_N MI_MRX_ITX_P LK_PIE_IH# LK_PIE_IH USP0- USP0 USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP T T USP- USP USP- USP T T T T LP PI SPI ocument Number ustom IH-M (US,MI,PIE,PI)./F SPI_LK_R.V_PIE_IH System System PI_GNT# PROJET : S Place within 00mils of IH NEWR Miniard- (WLN) Miniard-(reserved) FINGERPRINT ONNETOR WE M LUETOOTH oot IOS Strap 0 0 System GNT0# No stuff No stuff Stuff away override strap. Low = swap override enabled. High = efault. FI Remove SPI_S# No stuff Stuff MXLM-G E - / dd U for HP support. No stuff.v Quanta omputer Inc. X *0.U/0V/XR_ U SPI_S#0 SPI_S#0_R E# R0 _ V SPI_LK SPI_LK_R SK R0 _ SPI_MOSI SPI_MOSI_R SI R0 _ SPI_MISO R0 _ SPI_MISO_R HOL# SO R0 *K R0 0K/F_ ate: Friday, pril, 00 Sheet of

16 .V L_I0 L_I.V.V.V_S RP.V_S R.K PI_LKRUN# IH_SMT IH_SMLK Option to " isable " clkrun. Pulling it down will keep the clks running. L_I R PR-.K R *0.V.V *.K R 0K R *0K R 0K R00 0K R 0K R 0K R0 00K R 00K R00 0K R 0K R *0K R 0K R 0K_ R 0K_ R K_ R K_ VR_PWRGO_LKEN THERM_LERT# MH_IH_SYN#_R IRQ_SERIRQ RSV_GPIO WPN_RIO_IS_MINI# RSV_GPIO PIE_MR_ET# PIE_MR_ET# PIE_MR_ET# US_MR_ET# KSMI# NSWON# US_MR_ET# LN_WOL_EN E -0 dd R Pull high to.v_s IH_SMLINK0 IH_SMLINK IH_SMLK R *0 IH_SMLINK0 IH_SMT R *0 IH_SMLINK, IH_SMLK, IH_SMT IH_SMLK IH_SMT.V_S R0 0K IH_L_RST# T P IH_SMLINK0 T P IH_SMLINK T P ITP_RESET# PM_SYN# H_STP_PI# H_STP_PU#,0 PI_LKRUN#,, IH_PIE_WKE# 0 IRQ_SERIRQ THERM_LERT# 0 0 Z_SPKR MH_IH_SYN# NVII Non-iMT SF.0.V_S RP 0 T P FPK# KSMI# SWI SI# T_ON# T P ST_LKREQ# oard I IH_RI# LP_P# PI_LKRUN# E -0/ dd for TMP in FI. R 00K SI# IH_PIE_WKE# IRQ_SERIRQ THERM_LERT# VR_PWRGO_LKEN RSV_GPIO RSV_GPIO KSMI# SWI PIE_MR_ET# OR_I0 PIE_MR_ET# GPIO0 US_MR_ET# IH_GPIO WPN_RIO_IS_MINI# RSV_GPIO GPIO Z_SPKR R 0 MH_IH_SYN#_R IH_TP T0 P T P T P M I IH_TP IH_TP0 IH_TP INTEL SENTROS INTEL MENTVIR T P.V.V.V.V R 0K_ R *0K_ 0K-PR R *0K_ R 0K_ E - T P T P R 0K_ R *0K_ I I R *0K_ OR_I OR_I R K_ I0.V_S U G SMLK SMT E LINKLERT#/GPIO0/LGPIO SMLINK0 SMLINK F R SUS_STT#/LPP# G SYS_RESET# M PMSYN#/GPIO0 SMLERT#/GPIO STP_PI#/GPIO E STP_PU#/GPIO L LKRUN#/GPIO E0 WKE# M SERIRQ J THRM# 0 RI# VRMPWRG TP G TH/GPIO H TH/GPIO G TH/GPIO GPIO LNPHYP/GPIO ENGET/GPIO E TH0/GPIO K GPIO F GPIO0 J SLOK/GPIO QRT_STTE0/GPIO QRT_STTE/GPIO L STLKREQ#/GPIO E SLO/GPIO G STOUT0/GPIO F STOUT/GPIO H GPIO GPIO/LGPIO M SPKR J MH_SYN# TP H0 TP J0 TP0 J TP IHM REV.0 GPIO[0]--Integrated Pull-own 0K. OR_I OR_I0 R R R R R OR_I OR_I 0K 0K K 0K 0K SM ST GPIO locks SYS GPIO Power MGT MIS GPIO ontroller Link IH_RI# SWI IH_PIE_WKE# SI# RSV_GPIO VR_PWRG_LKEN#, ELY_VR_PG OR_I,0 ST0GP/GPIO STGP/GPIO STGP/GPIO STGP/GPIO PWROK LK LK SUSLK SLP_S# SLP_S# SLP_S# S_STTE#/GPIO PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# L_LK0 L_LK L_T0 L_T L_VREF0 L_VREF L_RST0# L_RST# MEM_LE/GPIO LERT#/GPIO0 NETETET/GPIO WOL_EN/GPIO H F E 0 H F P E G 0 LK_IH_M LK_IH_M IH_SUSLK SLP_S# SLP_S# SLP_S# PWROK L_LK.V L_T L_VREF0_S L_VREF_S L_RST# GPIO ME_E_LERT E_ME_LERT LN_WOL_EN LK_IH_M LK_IH_M S_STT# 0 G0 IH_PWROK E -0 change R0 pull-high to.v_s M PM_PRSLPVR_R 0 R PM_PRSLPVR, PM_TLOW#_R.K.V_S R0 LK_PWRG R NSWON# NSWON# 0 PM_PRSLPVR 0 RSV_IH_LN_RST# P T RSMRST# RSMRST# RSMRST# 0 RSV_IH_LN_RST# R LK_PWRG R F F F 0.V R0 K/F_.V_SUS R0.K R R U U T T NLSZFTG TSH0FU P T P PWROK,0 L_LK0 L_LK L_T0 L_T P P IH_L_RST0# L_RST#.V 00/F_ 00/F_ T0 T T ME_E_LERT 0 E_ME_LERT 0 LN_WOL_EN 0.U/0V_ VR_PWRGO_LKEN R0.U/0V_ SUS# 0 SUS# 0 00K/F_ IH_PWROK R0 0K/F_ ME_E_LERT E_ME_LERT Non-iMT For ME L_VREF0_S 0 0.U/0V.V ocument Number ustom IH-M (PM,GPIO,SM,L) LK_IH_M LK_IH_M.V Z_SPKR L_VREF_S Place these close to IH. Z_SPKR R *0K No Reboot strap. Low = efault. High = No Reboot..V_S PROJET : S R *0 *.P/0V R *0 R0 *0K R *00K R R *0K R /F R00 *K 0 *.P/0V 0K R0 0 R0.K/F 0.U/0V R.K/F R /F.V_S Quanta omputer Inc. ate: Friday, pril, 00 Sheet of

17 UE VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] E VSS[00] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E0 VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] H VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[00] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G0 VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[0] H VSS[00] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] J VSS[00] J VSS[0] J VSS[0] J VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] F VSS[0] F VSS[0] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[00] G VSS[0] G VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] IHM REV.0 VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[] VSS_NTF[] H J J J K K L L L L L L L M M M M M M M M M N N N N N N N N N N P P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U V V V V V V V V W W W Y Y Y Y Y G H F H H J J J J V_S.V V.V.V_S.V.V_PLL_RR L 0uH/00M 0uH-0%_00m.V.V_PLL.V_VGLNPLL RT_ELL HH-0HPT E -0 / chamge, to U, R,R0 to 00 ohm for US.0 can't work and meeti Intel Spec R 00_ L LMPGSN 0U/V R 0 U/0V 0U/.V L uh_00m HH-0HPT R0 00_.V.V_PIE_IH IH_VREF_RUN IH_VREF_SUS F_0ohm-%_00mHz_._0.0 ohm U/0V 0U/.V 0.U/0V U/.V_ U/.V_ 0.U/0V U/0V.V.V.V_PIE_IH.V.V TP TP 0.U/0V 0 0.U/0V 0.U/0V.V_PLL 0.U/0V.V TP_VSUSLN TP_VSUSLN 0.U/.V U/0V U/0V 0.U/0V.V UF VRT E VREF VREF_SUS V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] E V [0] E V [0] E V [] E V [] E V [] F V [] G V [] H V [] H V [] J V [] J V [] K V [0] K V [] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [0] P V [] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] U V [0] U V [] V V [] V V [] U V [] W V [] W V [] K V [] Y V [] Y V [] J VSTPLL V [0] V [0] V [0] E V [0] F V [0] G V [0] H V [0] J V [0] V [0] V [0] E V [] F V [] G0 V [] G V [] H0 V [] J0 V [] J V [0] G0 V [] G V [] V [] V [] V [] VUSPLL 0 VLN_0[] VLN_0[] VLN_[] VLN_[].V_VGLNPLL VGLNPLL VGLN_[] VGLN_[] E VGLN_[] E VGLN_[] V [] V [] V [] V [] V [] V [] V [] V [0] VGLN_ IHM REV.0 ORE VGP RX TX US ORE VP_ORE PI VPSUS VPUS GLN POWER V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] VMIPLL V_MI[] V_MI[] V_PU_IO[] V_PU_IO[] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[] V_[] V_[] V_[] VH VSUSH VSUS_0[] VSUS_0[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VL_0 VL_ VL_[] VL_[] E F L L L L L L M M P P T T U U V V V V V V R W Y G J 0 F0 G 0 F G G J J K J J F F E F T T T T T T U U V V W W Y Y T G G V_MI.V_MIPLL 0 0.0U/V 0.U/0V 0.U/0V VSUSH TP_VSUS.0_ TP_VSUS.0_ TP_VSUS._ TP_VSUS._ VSUS 0- uh-0%_00m.v L0 uh_00m R.V_MIPLL_R WWN Noise - IH improvements VSUS - R 0_ 0.U/0V 0.U/0V TP_VL.0 TP_VL..V 0U/.V.0V_VP 0.U/0V L LMPGSN.U/.V 0 0.U/0V 0.U/0V P T P T 0.U/0V 0.0U/V 0.U/0V.V.V_S R 0_ P T 0.U/0V 0.U/0V 0.0U/V 0.U/0V *U/0V.0V_VP E -0 0.U/0V.V 0.U/0V *0.U/0V 0.U/0V R 0_ 0 0.U/0V 0.U/0V.V_S 0.U/0V.V_S.0V_VP.U/0V ocument Number ustom IH-M (POWER,GN) E -0 hange to.v for H use. U/.V_ VIN Vout=.(R/R) 0.U/0V E -0 / mount 0.U U0 SHN SET PROJET : S 0.0U/V/XR_.V_S GN VOUT 0 I(P) G (SOT-)EP.U/.V_ Quanta omputer Inc. ate: Friday, pril, 00 Sheet of