DR1 (Roberts) Schematics Document ufcpga Mobile Penryn Intel Cantiga-GM + ICH9M REV : A00

Transcription

1 R () chematics ocument ufpg Mobile Penryn Intel antiga-gm + IHM REV : 00 : Nopop omponent <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. over Page ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

2 lock iagram PU / IL, INPUT OUTPUT +PWR_R +_ORE lock Generator LGPVTR RII /00 RII /00 lot 0 lot RII /00 hannel R II /00 hannel Intel Mobile PU Penryn ocket P Intel antiga-gml GTL+ PU I/F R Memory I/F External Graphics,, F 00/0MHz,,0,,, RG RT Project code :.Q0.00 P P/N :.Q0.0 Revision : 0- LV(ual hannel) RT (on I/O board) L PIE x & U.0 x Power W GRU New ard YTEM / TP INPUT +PWR_R YTEM / MX00 INPUT +PWR_R +V_LW +.V_RT_LO +V_LW +.V_LW YTEM / TP INPUT +PWR_R OUTPUT 0 +.0V_P OUTPUT OUTPUT +.V_U +0.V_R_VTT +V_R_MH_REF YTEM / PL /MM M/M Pro/x MER Module igital Mic rray MI IN Internal nalog MI ardreader Realtek RTE zalia OE IT H U.0 ZLI MIx Intel IH-M U.0/. ports () PI Express ports () High efinition udio T ports () LP I/F PI. PI/PI RIGE -LINK,,, PIE U.0 LP us PIE x 0/00 NI Marvell E00 PIE x 0 U.0 x U.0 x U.0 x U.0 x I/O oard onnector Mini-ard 0.a/b/g MER (Option) luetooth Right ide: U x RJ ONN Left ide: U x INPUT +.V_U P LYER L: Top OUTPUT +.V_RUN YTEM / LO INPUT +V_LW +.V_LW MXIM HRGER MX INPUT +_IN +PTT OUTPUT +V_RUN +.V_RUN OUTPUT +PWR_R L: HP OP MP MX T T PI K WINON WPEL L: ignal L: ignal L: GN L: ottom H PEKER 0 H O Flash ROM M Touch P Int. K Thermal & Fan EM0 <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock iagram ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

3 ignal H_OUT E IH E Rev.. Usage/When ampled omment XOR hain Entrance/ llows entrance to XOR hain testing when TP PIE Port onfig bit, pulled low. When TP not pulled low at rising edge Rising Edge of PWROK. of PWROK, sets bit of RP.P (ofig Registers: offset h). This signal has weak internal pull-down. L_RT0# PULL-UP 0K H_YN GNT#/ GPIO GPIO0 GNT#/ GPIO GNT#/ GPIO GNT0#: PI_#/ election 0:. (onfig Registers: Offset 0h:bit :0). FG MI Lane Reversal 0 = Normal operation (efault): Lane Numbered in GPIO PI_MOI GPIO TLE# PKR TP GPIO/ H_OK _EN# IHM Functional trap efinitions PIE config bit0, Rising Edge of PWROK. PIE config bit, Rising Edge of PWROK. Reserved. EI trap (erver Only) Rising Edge of PWROK. Top-lock wap override. Rising Edge of PWROK. oot IO estination Rising Edge of PWROK. PI Express Lane Reversal. Rising Edge of PWROK. No Reboot. Rising Edge of PWROK. XOR hain Entrance. Rising Edge of PWROK. Flash escriptor ecurity Override trap. Rising Edge of PWROK. This signal has a weak internal pull-down. ets bit0 of PR.P (onfig Registers: Offset h). This signal has a weak internal pull-up. ets bit of PR.P (onfig Registers: Offset h). This signal should not be pulled high. EI compatible mode is for server platforms only. This signal should not be pulled low for desktop and mobile. ampled low: Top-lock wap mode (inverts for all cycles targeting FWH IO space). Note: oftware will not be able to clear the Top-wap bit until the system is rebooted without GNT# being pulled down. ontrollable via oot IO estination bit GNT0# is M, 0-PI, 0-PI, -LP Integrated TPM Enable, ample low: the Integrated TPM will be disable. Rising Edge of LPWROK. ample high: the MH TPM enable strap is sampled low and the TPM isable bit is clear, the Integrated TPM will be enable. MI Termination Voltage. Rising Edge of LPWROK. The signal is required to be low for desktop applications and required to be high for mobile applications. ignal has weak internal pull-up. ets bit of MP.LR (evice : Function 0:Offset ). If sampled high, the system is strapped to the "No Reboot" mode (IH will disable the TO Timer system reboot feature). The status is readable via the NO REOOT bit. This signal should not be pull low unless using XOR hain testing. ampled low: the Flash escriptor ecurity will be overridden. If high, the security measures will be The pull-up or pull-down active when configured for native GLN_OK# functionality and determined by LN controller. FG[:] Reserved FG FG[:] FG[:] FG MI x elect 0 = MI x = MI x (efault) FG itpm Host Interface 0 = The itpm Host Interface is enabled (Note ) = The itpm Host Interface is disabled (default) FG Intel Management engine crypto strap 0 = Transport Layer ecurity (TL) cipher Order = Reverse Lanes MI x mode [MH->IH]: (->0, ->, -> and 0->) MI x mode [MH->IH]: (->0, ->) in effect. This should only be enabled in manufacturing environments using an external pull-up resister. IH Integrated pull-up and pull-down Resistors IGNL L_LK[:0] L_T[:0] PRLPVR/GPIO ENERGY_ETET H_IT_LK H_OK_EN#/GPIO H_RT# H_IN[:0] H_OUT H_YN GLN_OK# GNT[:0]#/GPIO[,,] GPIO0 GPIO L[:0]#/FHW[:0]# LN_RX[:0] LRQ[0] LRQ[]/GPIO PME# PWRTN# TLE# PI_#/GPIO/LGPIO PI_MOI PI_MIO PKR TH_[:0] TP[] U[:0][P,N] IH E Rev.. Resistor Type/Value PULL-UP 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-OWN K antiga chipset and IHM I/O controller Hub strapping configuration Pin Name FG[:0] FG0 Montevina Platform esign guide Rev.0. trap escription onfiguration igital isplay Port 0 = Only igital isplay Port or PIE is (VO/P/iHMI) operational (efault) oncurrent with PIe = igital display Port and PIe are operating simulataneously via the PEG port VO VO Present _TRLT L T Local Flat Panel (LFP) Present suite with no confidentiality = TL cipher suite with confidentiality(efault) FG PIE Graphics Lane 0 = Reserved Lanes, ->0, -> ect.. = Normal operation (efault): Lane Numbered in Order FG0 PIE Loopback enable 0 = Enable (Note ) = isable (efault) FG[:] XOR/LL F Frequency elect 000 = F0 0 = F 00 = F00 others = Reserved 00 = Reserve 0 = XOR mode Enabled 0 = LLZ mode Enable (Note ) = isabled (efault) FG F ynamic OT 0 = ynamic OT isabled = ynamic OT Enabled (efault) 0 = No VO ard Present (efault) = VO ard Present 0 = LFP isabled (efault) = LFP ard Present; PIE disabled NOTE:. ll strap signals are sampled with respect to the leading edge of the (G)MH Power OK (PWROK) signal.. itpm can be disabled by a 'oft-trap' option in the Flash-decriptor section of the Firmware. This 'oft-trap' is activated only after enabling itpm via FG. Only one of the FG0/FG/FG straps can be enabled at any time. PIE Routing U Table U Pair evice LNE Miniard WLN 0 U U LNE LN U LNE New ard RRVE MINI R RRVE LUETOOTH <ore esign> NEW R RRVE Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RRVE 0 ard Reader MER Table of ontent ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

4 I = LOK NEWR_LKREQ# MINI_LKREQ# R 0KRJ--GP R 0KRJ--GP +.V_RUN +.V_RUN R0 0R00-P +.V_RUN R00 0R00-P U0VKX-GP U0VKX-GP 0UVMX-GP 0UVMX-GP 0 UVKX-GP UVKX-GP UVKX-GP UVKX-GP 0 UVKX-GP 0 UVKX-GP LKTREQ# LKREQ#_ PLK_FWH PLK_K LK_PI_IH V_0_K0_IO UVKX-GP UVKX-GP V_0_K0 UVKX-GP UVKX-GP P0VJN-GP LK_M_R R RJ--GP R LK_M_IH F RJ--GP P0VN-GP H_TP_PI# H_TP_PU#,, IH_MLK,, IH_MT K_PWRG 00.0/0 LK_XTL_IN X LK_XTL_OUT X-M-GP P0VJN-GP R RF-L-GP R RJ--GP R0 RJ--GP R RJ--GP LKREQ#_ PI_TME _EL ITP_EN X X V_0_K0 V_0_K0_IO NEWR_LKREQ# LK_PIE_NEW LK_PIE_NEW# P0VN-GP 00.0/00 LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PU_ITP LK_PU_ITP# LK_PIE_LN 0 LK_PIE_LN# 0 LK_PIE_NEW LK_PIE_NEW# NEWR_LKREQ# MINI_LKREQ# LK_PIE_MINI LK_PIE_MINI# LK_MH_GPLL LK_MH_GPLL# LK_PIE_IH LK_PIE_IH# LK_M_IH P0VN-GP F F Main source:.0.00 (LGPVTR) nd source:.00.0 (RTMN-0-V-GRT) rd source: 00.0/00 LK_PIE_T LK_PIE_T# MH_REFLK MH_REFLK# LK_MH_REFLK LK_MH_REFLK# o-layout Ref:.0.0 (ILPRKLFT) V_0_K0 V_0_K0 _EL LK_MH_REFLK LK_MH_REFLK# R 0KRJ--GP R0 0KRJ--GP ITP_EN ITP_EN Output 0 R PU_ITP R 0KRJ--GP PI_TME PI_TME 0 Output Overclocking of PU and R allowed Overclocking of PU and R not allowed _EL PIN 0 PIN 0 OTT OT RT0 R0 LK T VREF V VPI VR VPU VPLL U_MHZ/FL PI_TOP# PU_TOP# U K_PWRG/P# PI0/R#_ 0 PI/R#_ PI/TME PI PI/_ELET PI_F/ITP_EN V_IO VPLL_IO VR_IO VR_IO VR_IO VPU_IO PUT0 PU0 0 PUT_F PU_F PUT_ITP/RT PU_ITP/R ILPRKLFT-GP-U RT/R#_F R/R#_E 0 RT R RT0 R0 RT/R#_H 0 R/R#_G RT R RT R RT/R#_ R/R#_ P0VN-GP E P0VJN-GP P0VN-GP P0VN-GP R0 RJ--GP FL/TET_MOE REF0/FL/TET_EL N# GN GNPI GNREF GN GNR GNR GNR GNPU GN 0 RT/TT R/T MHZ_NON/RT/E MHZ_/R/E GN RT0/OTT_ 0 R0/OT_ R0 0KRJ--GP R0 E0 P0VJN-GP E 0KRJ--GP P0VJN-GP GM PM EL F EL F EL0 F 0 00M X 0 0 M M 0 M M M 00M M 0M PU F PU_EL PU_EL PU_EL0 R 0KRJ--GP R 0RJ--GP R KRJ--GP R KRJ--GP R KRJ--GP R KRJ--GP F F F MH_LKEL0 MH_LKEL MH_LKEL <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock Generator LGPVTR ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

5 I = PU H_#[..] H_#[..] H_T#0 H_REQ#[..0] H_T# H_0M# H_FERR# H_IGNNE# H_TPLK# H_INTR H_NMI H_MI# TP0 TP0 TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_0 RV_PU_ J # L # L # K # M # N # J # N 0# P # P # L # P # P # R # M T0# K REQ0# H REQ# K REQ# J REQ# L REQ# H_# Y H_# # U H_# # R H_#0 # W H_# 0# U H_# # Y H_# # U H_# # R H_# # T H_# # T H_# # W H_# # W H_# # Y H_#0 # U H_# 0# V H_# # W H_# # H_# # H_# # # V T# 0M# FERR# IGNNE# TPLK# LINT0 LINT MI# M RV#M N RV#N T RV#T V RV#V RV# RV# TET RV# RV# RV# F RV#F U OF KEY_N RRVE R GROUP 0 R GROUP IH G-KT-GPU.000. XP/ITP IGNL ONTROL # NR# PRI# EFER# R# Y# R0# IERR# INIT# LOK# RT# R0# R# R# TR# HIT# HITM# PM0# PM# PM# PM# PR# PREQ# TK TI TO TM TRT# R# THERML PROHOT# THRM THRM THERMTRIP# HLK LK0 LK H E G H F E F 0 PU_IERR# H F F G G G E H_PURT# H_R#0 H_R# H_R# ITP_PM#0 ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_TK ITP_TI ITP_TO ITP_TM ITP_TRT# 0 ITP_RT# H_# H_NR# H_PRI# H_EFER# H_R# H_Y# H_REQ#0 R RJ--GP H_INIT# R0 0RJ--GP R RJ--GP H_LOK# H_PURT#, H_R#[..0] H_TR# H_HIT# H_HITM# ITP_PM#0 ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_TK ITP_TI ITP_TO ITP_TM ITP_TRT# ITP_RT# +.0V_P H_THERM H_THERM +.0V_P PU_PROHOT# H_THRMTRIP#,,, R RJ--GP +.0V_P 00.0/00 LK_PU_LK LK_PU_LK# H_THERM, H_THERM routing together, Trace width / pacing = 0 / 0 mil H_THRMTRIP# should connect to IH and MH without T-ing. H_THERM H_THERM 00P0VKX-GP <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU-F(/) ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

6 I = PU H_INV#[..0] H_TN#[..0] H_TP#[..0] H_#[..0] H_INV#[..0] H_TN#[..0] H_TP#[..0] H_#[..0] U OF Layout notes Z= Ohm 0." MX for PU_GTLREF0 +.0V_P R KRF--GP R KRF--GP PU_GTLREF0 KP0VKX-GP H_TN#0 H_TP#0 H_INV#0 H_TN# H_TP# H_INV# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# E 0# F # E # G # F # G # E # E # K # G # J 0# J # H # F # K # H # J TN0# H TP0# H INV0# N # K # P # R # L 0# M # L # M # P # P # P # T # R # L # T 0# N # L TN# M TP# N INV# T GRP0 T GRP # Y # # V # V # V # T # U # U 0# Y # W # Y # W # W # # # TN# Y TP# INV# U # E # 0# # # # # 0 # E # F # # E # 0# # # F # TN# E TP# F INV# 0 H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_TN# H_TP# H_INV# H_TN# H_TP# H_INV# OMP0 TET GTLREF OMP0 R R0 RF-L-GP R KRJ--GP OMP R RF-L-GP R0 KRJ--GP TET OMP U TET MI OMP R KRJ--GP PU_TET TET OMP R RF-L-GP OMP R RF-L-GP TET OMP Y F R KRJ--GP PU_TET TET F TET PRTP# E H_PRTP#,, TET PLP# H_PLP# PWR# H_PWR# PU_EL0 EL0 PWRGOO H_PWRGOO, PU_EL EL LP# H_PULP# PU_EL EL PI# E PI# T GRP T GRP Layout Note: omp0, connect with Zo=. ohm, make trace length shorter than 0.". omp, connect with Zo= ohm, make trace length shorter than 0.". G-KT-GPU.000. Route the PU_TET and PU_TET signals through a ground referenced Zo = -ohm trace that ends in a via that is near a GN via and is accessible through an oscilloscope connection. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU-F(/) ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

7 I = PU +_ORE +_ORE U OF E E E0 P E P E P E P E P E P E0 P F P F P F0 P F P F P F P F P F P F0 P 0 VI0 VI VI VI 0 VI VI 0 VI 0 ENE ENE G-KT-GPU E E0 E E E E E E0 F F0 F F F F F F0 G V J K M J K M N N R R T T V W +_ORE PU_VI0 F PU_VI E PU_VI F PU_VI E PU_VI F PU_VI E PU_VI F E PU_VI[..0] +_ORE +_ORE +.0V_P layout note: "+.V_" as short as possible R 00RF-L-GP-U R0 00RF-L-GP-U UVMX-GP UVMX-GP UVMX-GP T T0UVM-LGP UVMX-GP UVMX-GP UVMX-GP U0VKX-GP 0UVKX-GP +_ORE UVMX-GP UVMX-GP UVMX-GP U0VKX-GP _ENE _ENE UVMX-GP UVMX-GP 0 UVMX-GP U0VKX-GP 0 UVMX-GP UVMX-GP UVMX-GP U0VKX-GP +.V_ UVMX-GP UVMX-GP 0 UVMX-GP U0VKX-GP R 0R00-P UVMX-GP UVMX-GP UVMX-GP +.V_RUN 0UVMX-GP UVMX-GP UVMX-GP UVMX-GP _ENE and _ENE lines should be of equal length. U0VKX-GP UVMX-GP UVMX-GP UVMX-GP UVMX-GP UVMX-GP UVMX-GP Layout Note: Place as close as possible to the PU pin. 0 UVMX-GP UVMX-GP U F E E E E E E E E E F F F F F F F F F G G G G H H H H J J J J K K K K L L L L M M M M N N N N P OF P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F F F PU_GN PU_GN PU_GN PU_GN NTF PIN TP0 TP TP0 TP G-KT-GPU.000. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU-Power(/) ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

8 I = MH H_WING routing Trace width and pacing use 0 / 0 mil H_WING Resistors and apacitors close MH 00 mil ( MX ) H_ROMP routing Trace width and pacing use 0 / 0 mil H_WING H_ROMP R RF-L-GP Place R near to the chip ( < 0.") +.0V_P R RF--GP R 00RF-L-GP-U +.0V_P H_#[..0] H_VREF H_#[..0], H_PURT# H_PULP# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WING H_ROMP H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_R#0 H_R# H_R# H_#[..] H_# H_T#0 H_T# H_NR# H_PRI# H_REQ#0 H_EFER# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_R# H_HIT# H_HITM# H_LOK# H_TR# H_INV#[..0] H_TN#[..0] H_TP#[..0] H_REQ#[..0] H_R#[..0] H_#[..] H_INV#[..0] H_TN#[..0] H_TP#[..0] H_REQ#[..0] H_R#[..0] R KRF--GP R KRF--GP 0 UVKX-GP U0VKX-GP U F H_#_0 G H_#_ F H_#_ E H_#_ G H_#_ H H_#_ H H_#_ F H_#_ H_#_ H H_#_ M H_#_0 M H_#_ J H_#_ J H_#_ N H_#_ J H_#_ P H_#_ L H_#_ R H_#_ N H_#_ L H_#_0 M H_#_ J H_#_ N H_#_ R H_#_ N H_#_ N H_#_ P H_#_ N H_#_ L H_#_ N0 H_#_0 M H_#_ Y H_#_ H_#_ Y H_#_ Y0 H_#_ Y H_#_ Y H_#_ Y H_#_ W H_#_ H_#_0 Y H_#_ H_#_ H_#_ H_#_ H_#_ 0 H_#_ H_#_ E H_#_ E H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ E H_#_ F H_#_ H_#_ E H_#_ H_#_ E H_#_0 E H_#_ G H_#_ H_#_ H_WING E H_ROMP H_PURT# E H_PULP# H_VREF H_VREF HOT OF 0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_# H_T#_0 H_T#_ H_NR# H_PRI# H_REQ# H_EFER# H_Y# HPLL_LK HPLL_LK# H_PWR# H_R# H_HIT# H_HITM# H_LOK# H_TR# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_TN#_0 H_TN#_ H_TN#_ H_TN#_ H_TP#_0 H_TP#_ H_TP#_ H_TP#_ H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_R#_0 H_R#_ H_R#_ F H M J P R N M E P F G0 J E0 H J0 L L J H0 K 0 F K L0 H G F G E 0 H H J F H E H J L Y Y L0 M E L M E K F F NTIG-GM-GP-U-NF <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga-hot(/) ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

9 I = MH * is current setting FG trap +.V_RUN FG FG FG FG P_TRLT R0 KRF-GP FG R KRF-GP FG R K0RF-GP FG R K0RF-GP FG0 R KRF-GP FG R KRF-GP FG R KRF-GP FG R0 KRF-GP FG R K0RF-GP FG R KRF-GP FG0 R0 KRF-GP FG R0 KRF-GP FG R0 KRF-GP FG FG 0 PIE loopback enable PIE loopback disable FG LLZ mode enable LLZ mode disable FG XOR mode enable XOR mode disable FG F dynamic OT disable F ynamic OT enable FG MI Lane Reserved Normal operation Reverse MI lanes * FG 0 PIE and VO are VO concurrent Only PIE or VO operatiing simultaneously with PIE is operational * via the PEG port VO_TRLT VO interface disable VO interface enable * L T LFP disable LFP card present RN0 RN0KJ--GP VO/iHMI/P interface disabled PM_EXTT#0 PM_EXTT# Low MI X ITPM enable TL cipher suite with no confidentiality PIE GFX lane reversed,, PM_PWROK,0,,,, PLT_RT#,,, H_THRMTRIP#, PRLPVR * F setting High MI X ITPM disable TL cipher suite with confidentiality PIE GFX lane numbered in oder VO/iHMI/P interface enabled MH_LKEL0 MH_LKEL MH_LKEL TP TP TP TP TP PM_YN#,, H_PRTP# PM_EXTT#0 PM_EXTT# R 00RF-L-GP-U 00P0VJN-GP * * * FG FG FG FG FG FG FG FG0 FG FG FG FG FG FG FG FG FG FG0 RTIN# M RRVE#M N RRVE#N R RRVE#R T RRVE#T H RRVE#H H0 RRVE#H0 H RRVE#H H RRVE#H K RRVE#K L RRVE#L K RRVE#K N RRVE#N M RRVE#M T RRVE#T RRVE# RRVE# M RRVE#M Y U RRVE#Y G RRVE#G F RRVE#F H RRVE#H F RRVE#F T FG_0 R FG_ P FG_ P0 FG_ P FG_ FG_ N FG_ M FG_ E FG_ FG_ FG_0 N FG_ P FG_ T FG_ R0 FG_ M0 FG_ L FG_ H FG_ P FG_ R FG_ T FG_0 R PM_YN# PM_PRTP# N PM_EXT_T#_0 P PM_EXT_T#_ T0 PWROK T RTIN# T0 THERMTRIP# R PRLPVR G N#G F N#F N# N# H N#H G N#G E N#E H N#H F N#F G N#G H N#H H N#H H N#H H N#H G N#G H N#H F N#F H N#H G N#G E N#E G N#G F N#F N# N# F N#F N# NTIG-GM-GP-U-NF RV FG PM N R LK/ ONTROL/OMPENTION LK MI GRPHI VI ME MI H OF 0 _K_0 P _K_ T _K_0 V _K_ U0 _K#_0 R _K#_ R _K#_0 U _K#_ V0 _KE_0 _KE_ Y _KE_0 Y _KE #_0 _#_ Y _#_0 V _#_ R _OT_0 _OT_ Y _OT_0 F _OT_ Y M_ROMP G M_ROMP# H M_ROMP_VOH F M_ROMP_VOL H M_VREF M_PWROK M_REXT M_RMRT# PLL_REF_LK PLL_REF_LK# PLL_REF_LK E PLL_REF_LK# F PEG_LK F PEG_LK# E MI_RXN_0 E MI_RXN_ E MI_RXN_ E MI_RXN_ H MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ M_ROMPP M_ROMPN M_ROMP_VOH M_ROMP_VOL LK_MH_REFLK LK_MH_REFLK# MH_REFLK MH_REFLK# LK_MH_GPLL LK_MH_GPLL# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_RXP0 MI_RXP MI_RXP MI_RXP MH_LVREF TTN# M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# M_KE0 M_KE M_KE M_KE M_0# M_# M_# M_# M_OT0 M_OT M_OT M_OT V R F M_REXT R RF--GP E0 MI_TXP0 E MI_TXP E MI_TXP H0 MI_TXP MI_RXN0 MI_TXN_0 E MI_RXN MI_TXN_ E MI_RXN MI_TXN_ E MI_RXN MI_TXN_ H MI_TXP_0 MI_TXP_ E MI_TXP_ F MI_TXP_ H GFX_VI_0 GFX_VI_ GFX_VI_ G GFX_VI_ F GFX_VI_ E GFX_VR_EN L_LK H L_T H L_PWROK N L_RT# J L_VREF H P_TRLLK N P_TRLT M VO_TRLLK G VO_TRLT E LKREQ# K IH_YN# H TTN# H_LK H_RT# 0 H_I H_O H_YN TP LK_MH_REFLK LK_MH_REFLK# MH_REFLK MH_REFLK# LK_MH_GPLL LK_MH_GPLL# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP L_LK0 L_T0 M_PWROK L_RT#0 MH_LVREF ~= 0.V LKREQ#_ MH_IH_YN# +V_R_MH_REF +.0V_P TTN# +.V_U +.V_U R 0KRJ--GP R 0KRJ--GP U0VKX-GP R0 0RF-L-GP R 0RF-L-GP R KRF--GP +.0V_P R0 RF--GP R0 RJ--GP <ore esign> M_ROMP_VOH U0VKX-GP M_ROMP_VOL U0VKX-GP LKREQ#_ +.V_RUN 0KRJ--GP R TTN#_K Q MMT0WTG-GP E 0UVKX-GP 0UVKX-GP R 0KRJ--GP +.V_RUN +.V_U TTN#_K Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga-mi/fg(/) ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of R KRF--GP R K0RF--GP R KRF--GP

10 I = MH M Q[..0] M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U J _Q_0 J _Q_ N _Q_ M _Q_ J _Q_ J0 _Q_ M _Q_ M _Q_ N _Q_ N _Q_ U0 _Q_0 T _Q_ N _Q_ N _Q_ U _Q_ U _Q_ V _Q_ Y _Q_ 0 _Q Q_ V _Q_0 Y _Q Q_ 0 _Q_ Y _Q Q_ V _Q_ T _Q_ Y _Q Q_ V _Q_0 W _Q Q_ U _Q Q Q_ U _Q_ V _Q Q Q Q_0 _Q_ U0 _Q_ V _Q Q Q_ Y _Q Q_ V _Q_ V _Q_ T _Q_0 N _Q_ U _Q_ U _Q_ T _Q_ N0 _Q_ M _Q_ M _Q_ J _Q_ J _Q_ N _Q_0 M _Q_ J _Q_ J _Q_ R YTEM MEMORY OF 0 0 _R# _# _WE# _M_0 _M M M M M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M M M M M M M M M_0 _M M M M_ G T 0 0 Y0 M T Y U Y T J J T W U M J T Y U M G H G G F W G H H Y M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M M M M[..0] M Q[..0] M Q#[..0] M [..0] M #0 M # M # M R# M # M WE# M M[..0] M Q[..0] M Q#[..0] M [..0] M Q[..0] M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q UE K _Q_0 H _Q_ P _Q_ P _Q_ J _Q_ J _Q_ M _Q_ P _Q_ U _Q_ U _Q Q_0 Y _Q_ T _Q_ R _Q Q Q Q Q_ G _Q_ F _Q_ E _Q_0 _Q_ F0 _Q_ F _Q_ G _Q_ F _Q_ H _Q_ G _Q_ H0 _Q_ G _Q_ G _Q_0 H _Q_ H _Q_ G _Q_ H _Q_ G _Q_ H _Q_ F _Q_ F _Q_ G _Q Q_0 _Q_ Y _Q_ Y _Q_ F _Q_ F _Q Q Q_ V _Q_ U _Q_ R _Q_0 N _Q_ Y _Q_ V _Q_ P _Q_ R _Q_ L _Q_ L _Q_ J _Q_ H _Q_ M _Q_0 M _Q_ H _Q_ J _Q_ R YTEM MEMORY OF 0 0 _R# _# _WE# _M_0 _M M M M M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M M M M M M M M M_0 _M M M M_ U G F M Y 0 F G P K L V G G H U N L V H H G T N V U W U W T W Y H U M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M M M M[..0] M Q[..0] M Q#[..0] M [..0] M #0 M # M # M R# M # M WE# M M[..0] M Q[..0] M Q#[..0] M [..0] NTIG-GM-GP-U-NF NTIG-GM-GP-U-NF <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga-r(/) ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet 0 of

11 I = MH +.0V_P FOR ORE UF OF 0 TP TP +.V_U +.0V_P _XG_ENE _XG_ENE UG P _M N _M H _M G _M F _M _M _M _M _M Y _M W _M V _M U _M T _M R _M P _M N _M H _M G _M F _M G0 _M H _M G _M F _M _M _M _M _M Y _M W _M V _M U _M T _M R _M P _M Y _XG E _XG _XG _XG E _XG _XG _XG Y _XG E _XG _XG _XG _XG J _XG G _XG E _XG _XG _XG Y _XG H0 _XG F0 _XG E0 _XG 0 _XG 0 _XG 0 _XG T _XG T _XG M _XG L _XG E _XG J _XG H _XG G _XG F _XG _XG _XG Y _XG V _XG U _XG N _XG M _XG U _XG T _XG 000m _M/N _M/N _M/N _M/N W _M/N W _M/N T _M/N 00m J _XG_ENE H _XG_ENE POWER M GFX NTIG-GM-GP-U-NF GFX NTF M LF OF 0 _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _XG_NTF _M_LF _M_LF _M_LF _M_LF _M_LF _M_LF _M_LF +.0V_P W V W V W V W V W V M L K W V U M0 K0 W0 U0 M L K J H G F E Y W V U M K H G F E Y W V M L K J H G F E Y W V U 0 UVKX-GP T T0UVM-GP V M_LF_GMH M_LF_GMH M0M_LF_GMH V M_LF_GMH Y M_LF_GMH M0M_LF_GMH M_LF_GMH Place on the Edge 0 UVKX-GP oupling P Place P where LV and R taps U0VKX-GP UVKX-GP U0VKX-GP UVKX-GP 0 UVMX-GP U0VKX-GP 0UVMX-GP U0VKX-GP U0VKX-GP U0VKX-GP FOR M U0VKX-GP T T0UVM-GP UVMX-GP Place on the Edge UVKX-GP U0VKX-GP UVMX-GP +.V_U U0VKX-GP oupling P 0 mils from the Edge 0 UVMX-GP 0UVMX-GP U0VKX-GP U0VKX-GP UVKX-GP U0VKX-GP oupling P R _GMH_ 0RJ--GP upply ignal Group Imax +.0V_P.m +.0V_P _XG 00m +.0V_P VTT m +.0V_P _PEG m +.0V_P _MI m +.0V_P _M 0m +.0V_P _M_K m +.0V_P _HPLL m +.0V_P _MPLL.m +.0V_P _HPLL.m +.0V_P _PEG_PLL 0m +.0V_P _PEG_PLL 0m +.0V_P _XF.m +.V_RUN _H 0m +.V_RUN _TV m +.V_U _LV 0.m +.V_U +.V_U _M _M_K 000m m +.V_RUN _PEG_G u +.V_RUN _HV 0.m U0VKX-GP U0VKX-GP 0 U0VKX-GP G Y V U M K J G F E Y W V U H F J G E H G F G J H F T.m ORE NTIG-GM-GP-U-NF <ore esign> POWER NTF +.0V_P _NTF M _NTF L _NTF K _NTF J _NTF H _NTF G _NTF E _NTF _NTF _NTF Y _NTF W _NTF U _NTF M0 _NTF L0 _NTF K0 _NTF H0 _NTF G0 _NTF F0 _NTF E0 _NTF 0 _NTF 0 _NTF 0 _NTF Y0 _NTF W0 _NTF V0 _NTF U0 _NTF L _NTF K _NTF J _NTF H _NTF G _NTF E _NTF _NTF _NTF Y _NTF W _NTF V _NTF L _NTF K _NTF L _NTF K _NTF K _NTF K _NTF K Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga-power(/) ize ocument Number Rev ustom 00 ate: Thursday, eptember, 00 heet of

12 I = MH +.0V_P M PLL R 0R00-P +.V_RT_LO +.0V_P V_RT_0 R 0R00-P U0VKX-GP UVKX-GP OF 0 UH UVKX-GP VTT U R0 M PLL VTT T _RT_ VTT U T T0UVM-LGP E UVKX-GP UVKX-GP U0VKX-GP UVKX-GP U0VKX-GP UVKX-GP m 0R00-P +.V_RT_LO m M G UVKX-GP M PLL +.0V_P +.0V_P m +.V_RUN +.V HV.m U0VKX-GP M PLL 0UVKX-GP R0 0R00-P U0VKX-GP UVKX-GP R m.m M HPLL +.V_U R 0R00-P R 0R-0-U-GP M MPLL 0RJ--GP R0 0R00-P U0VKX-GP M HPLL T--F-GP T U T U0 T0 U T U T U T U T U T V U V U T V U VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT _RT_ 0UVKX-GP RT G G _PLL F VTT _PLL L _HPLL PLL _MPLL E.m _LV J V_TXLV KP0VKX-GP L FM0KF--GP 0ohm 00MHz +.V_RUN +.0V_P _PEG_G 0V XF _PEG_G u R0 0R00-P U0VKX-GP LV _LV J UVKX-GP R 0R00-P L M MPLL U0VKX-GP FM0KF--GP 0V_RUN_PEGPLL +.0V_P _PEG_PLL 0m 0ohm 00MHz 0 0UVMX-GP 0 U0VKX-GP PEG +.V_U 0m U0VKX-GP UVMX-GP U0VKX-GP POWER UVMX-GP +.0V_P R 0R00-P _M _M _M _M _M _M _M _M _M R0 P0 N0 R P N T R P 0 UVKX-GP 0UVMX-GP M 0V_RUN_PEGPLL +.0V_P R00 RF-GP L LMN-GP 0ohm 00MHz U0VKX-GP 0V_M_K.m m U0VKX-GP R0 0R00-P U0VKX-GP 0 UVMX-GP U0VKX-GP 0 0UVMX-GP 0UVMX-GP _XF _XF _XF XF +.V_RUN +.V_U R0 0R00-P V_TXLV_ +.V_TV_ +.V_RT_LO VRUN_TV _M_K_NTF L _M_K_NTF UVMX-GP m _M_K _M_K _M_K _M_K _M_K _M_K_NTF _M_K_NTF _M_K_NTF _M_K_NTF _M_K_NTF _M_K_NTF P N P N N M M M L M L M R 0R00-P 00.0/00 0 KP0VKX-GP _M_K F _M_K H0 _M_K G0 _M_K F0 K +.V HV.m VRUN_Q +.0V_P 0.m m 0UVKX-GP U0VKX-GP R 0R00-P M K K _TX_LV U0VKX-GP _TV TV_ 0UVKX-GP _HV _HV _HV TV HV 0m _H R 0R00-P _H L H0K-T0GP 0ohm 00MHz 0UVMX-GP m m m VRUN_TV 0UVMX-GP UVKX-GP 0UVMX-GP _PEG V _PEG U _PEG V _PEG U _PEG U H PEG _TV M U0VKX-GP VRUN_Q +.0V_P 0UVKX-GP 0V_RUN_HPLL +.0V_P H F H G _Q L _MI _MI _MI _MI m.m _HPLL F R0 0R00-P MI TV/RT 0m 0V_RUN_PEGPLL +V_RUN _PEG_PLL VTTLF VTTLF VTTLF _LV _LV 0.m U0VKX-GP U0VKX-GP U0VKX-GP L M L VTTLF VTTLF VTTLF LV VTTLF U U0VKX-GP EN +.V_U NTIG-GM-GP-U-NF GN <ore esign> Wistron orporation V_U_LV R0 0R00-P +.V_RT_LO F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. U0VKX-GP 0 UVKX-GP UVKX-GP UVKX-GP VIN VOUT N# G0-0TU-GP antiga-power/filter(/) 00 Main source:.00.hf nd source:.0.0f 0UVMX-GP ize ocument Number Rev ustom ate: Thursday, eptember, 00 heet of Reserved for TV ripple

13 GMH_GN GMH_GN GMH_GN GMH_GN PEG_MP M_LUE GMH_V RT_IREF GMH_H LV_VG M_GRN M_RE LIG TV_ TV_ TV_ L_T L_LK L_TRL_T L_TRL_LK _LK_ON _T_ON GMH_LK GMH_T GMH_T GMH_LK +.0V_P +.V_RUN +.V_RUN +.V_RUN +.V_RUN VG_TXOUT0+ VG_TXOUT+ VG_TXOUT+ VG_TXOUT0- VG_TXOUT- VG_TXOUT- VG_TXLK- VG_TXLK+ LKLT_TL L_LK L_T GMH_L_ON GMH_HYN GMH_VYN VG_TXLK- VG_TXLK+ VG_TXOUT0+ VG_TXOUT+ VG_TXOUT+ VG_TXOUT0- VG_TXOUT- VG_TXOUT- M_LUE M_GRN M_RE LV_EN _LK_ON _T_ON ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. 00 antiga-gn/lv/vg(/) ustom Thursday, October 0, 00 <ore esign> ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. 00 antiga-gn/lv/vg(/) ustom Thursday, October 0, 00 <ore esign> ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. 00 antiga-gn/lv/vg(/) ustom Thursday, October 0, 00 <ore esign> NTF PIN Place R0 close to MH within 00 mils. RT_IREF routing Trace width use 0 mil. I = MH ext. RT side R RF--GP R RF--GP TP TP G W U P N H F R M J G 0 0 W0 T0 J0 G0 Y0 N0 K0 F0 0 0 G G W T R M H U N N K G E G W G G N J E N L G E F V T M J Y N H Y N G G0 V0 T0 J0 E0 0 H G M N M0 F H Y L E Y U N J E N J G V T M M H Y L J H F E V L _NTF F _NTF _NTF V _NTF J0 _NTF M _NTF F _NTF _NTF U _NTF U _NTF L0 _NTF V0 _NTF _NTF L _NTF J _NTF _NTF U _ H _ H _ N#E E N# N# N# N# N# N# N# N# N# N# N# N# N#F F N#E E N# N# R P R U P F W E F H J Y M K M P H V T U U U U L NTF N 0 OF 0 UJ NTIG-GM-GP-U-NF NTF N 0 OF 0 UJ NTIG-GM-GP-U-NF R 0RF--GP R 0RF--GP R K0RF--GP R K0RF--GP U R L W N J F Y T N L G V R M V R P H F F H Y U T M F V U M J G Y T N J E N L U M H Y U T M G G0 0 V0 N0 H0 E0 T M J E N L H U H Y U T J F M E P L J F H Y U T F M J F E W G V R L H P L H N K F N T N K H F G V T R J G E Y P K H F F H F H V R J Y N L J G E F F W T N J H G U T H L Y G E G Y J F R K J F H Y K J OF 0 UI NTIG-GM-GP-U-NF OF 0 UI NTIG-GM-GP-U-NF R RF-GP R RF-GP RN RNKJ--GP RN RNKJ--GP R RF--GP R RF--GP R 0RF--GP R 0RF--GP TP0 TP0 TP0 TP0 RN RNKJ--GP RN RNKJ--GP TP TP R KRF-GP R KRF-GP RN RN0KJ--GP RN RN0KJ--GP TP TP PEG_OMPI T PEG_OMPO T PEG_RX#_0 H PEG_RX#_ J PEG_RX#_ L PEG_RX#_ L0 PEG_RX#_ N PEG_RX#_ P PEG_RX#_ N PEG_RX#_ T PEG_RX#_ U PEG_RX#_ Y PEG_RX#_0 Y PEG_RX#_ Y PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX_0 H PEG_RX_ J PEG_RX_ L PEG_RX_ L PEG_RX_ N0 PEG_RX_ P PEG_RX_ N PEG_RX_ T PEG_RX_ U PEG_RX_ Y PEG_RX_0 W PEG_RX_ Y PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ 0 PEG_TX#_0 J PEG_TX#_0 Y0 PEG_TX#_ M0 PEG_TX#_ M PEG_TX#_ R PEG_TX#_ N PEG_TX#_ T0 PEG_TX#_ U PEG_TX#_ U0 PEG_TX#_ M PEG_TX#_ PEG_TX#_ PEG_TX#_ 0 PEG_TX#_ PEG_TX#_ PEG_TX#_ M PEG_TX_0 J PEG_TX_ L PEG_TX_ M PEG_TX_ M PEG_TX_ M PEG_TX_ R PEG_TX_ N PEG_TX_ T PEG_TX_ U PEG_TX_ U PEG_TX_0 Y PEG_TX_ Y PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ L_TRL_LK M L_TRL_T M L LK K L T J L_V_EN M LV_IG LV_VG LV_VREFH E LV_VREFL E LV_LK# LV_LK 0 LV_T#_0 H LV_T#_ E LV_T#_ G0 LV_T_ LV_T_ F0 LV_LK# LV_LK LV_T#_0 LV_T#_ H LV_T#_ G LV_T_ G LV_T_ F L_KLT_EN G TV_ F TV_ H TV_ K TV_RTN H RT_LUE E RT LK H RT T J RT_GRN G RT_HYN J RT_TVO_IREF E RT_RE J RT_IRTN G RT_VYN L LV_T_0 H LV_T_0 L_KLT_TRL L TV_ONEL_0 TV_ONEL_ E LV_T#_ 0 LV_T_ 0 LV_T#_ J LV_T_ K LV PI-EXPRE GRPHI TV VG OF 0 U NTIG-GM-GP-U-NF LV PI-EXPRE GRPHI TV VG OF 0 U NTIG-GM-GP-U-NF R RJ--GP R RJ--GP R RF--GP R RF--GP R 0RF--GP R 0RF--GP U N00PT U N00PT R RJ--GP R RJ--GP

14 I = MEMORY +0.V_R_VTT 0 UVKX-GP +.V_U U0VKX-GP 0 UVKX-GP U0VKX-GP 0 UVKX-GP 0 M Q#[..0] 0 M Q[..0] 0 M M[..0] 0 M Q[..0] 0 M [..0] Layout Note: Place near M 0 U0VKX-GP U0VKX-GP Layout Note: Place one cap close to every pullup resistors terminated to +0.V_R_VTT. UVKX-GP U0VKX-GP UVKX-GP UVKX-GP UVKX-GP UVKX-GP 0 UVKX-GP UVKX-GP 00 UVKX-GP UVKX-GP +V_R_MH_REF 0 UVKX-GP 0 UVKX-GP UVKX-GP T T0UVM-LGP UVKX-GP UVKX-GP M # M #0 M # M_OT0 M_OT 0 UVKX-GP M 0 M M M M M M M M M M 0 M M M M M # M #0 M # M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M_OT0 M_OT 0 U0VKX-GP /P 0 / Q0 Q Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q 0 Q0 Q Q Q Q0# Q# Q# Q# Q# Q# Q# Q# Q0 Q Q 0 Q Q Q Q Q OT0 OT VREF 0 MH M GN MH KT-OIMM00-GP R# 0 WE# 0 # 0# 0 # KE0 KE 0 K0 0 K0# K K# M0 0 M M M M 0 M M 0 M L VP 0 00 N#0 0 N# N# N#0 0 N#/TET V V V V V V V 0 V 0 V V V V GN 0 MH MH.00.E M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# M M0 M M M M M M M M M M M M M M IH_MT IH_MLK +.V_U M R# 0 M WE# 0 M # 0 M_0# M_# M_KE0 M_KE M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# +.V_RUN R 0KRJ--GP R 0KRJ--GP IH_MT,, IH_MLK,, PM_EXTT#0 M M M 0 M #0 M_OT0 M_0# M_KE M M WE# M # M_# M_OT M M <ore esign> M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# +.V_RUN Layout Note: Place these resistors close to M, all trace length Max=.". RN RN +0.V_R_VTT RNJ--GP RN RNJ--GP RN RN RNJ--GP RNJ--GP RN RN RNJ--GP RNJ--GP RNJ--GP UMMY- ate: Thursday, October 0, 00 heet of put near connector UVKX-GP UMMY- RN RN RN M M M M M M M M_KE0 M # M # M R# M 0 M Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RII-OIMM LOT ize ocument Number Rev ustom 00 RNJ--GP RN RN0 RNJ--GP RNJ--GP RNJ--GP RN U0VKX-GP RNJ--GP RN RNJ--GP RNJ--GP UMMY- UMMY-

15 I = MEMORY +0.V_R_VTT 0 UVKX-GP +.V_U U0VKX-GP UVKX-GP U0VKX-GP UVKX-GP 0 M Q#[..0] 0 M Q[..0] 0 M M[..0] 0 M Q[..0] 0 M [..0] Layout Note: Place near M 0 U0VKX-GP Layout Note: Place one cap close to every pullup resistors terminated to +0.V_R_VTT. 0 U0VKX-GP UVKX-GP U0VKX-GP UVKX-GP 0 UVKX-GP UVKX-GP 0 UVKX-GP 0 UVKX-GP UVKX-GP 0 UVKX-GP 0 UVKX-GP UVKX-GP UVKX-GP +V_R_MH_REF T T0UVM-LGP UVKX-GP UVKX-GP M # M #0 M # PM_EXTT# M_# M_# M_KE M_KE M R# M # M WE#,, IH_MLK,, IH_MT 00 UVKX-GP 0 UVKX-GP M_OT M_OT M 0 M M M M M M M M M M 0 M M M M M # M #0 M # M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q IH_MLK IH_MT M_OT M_OT 0 U0VKX-GP MH /P 0 _ Q0 Q Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q 0 Q0 Q Q Q 0 N#0 N# N# 0 N#0 N#/TET 0 0# # KE0 0 KE 0 R# # 0 WE# L OT0 OT 0 M MH VREF GN MH MH Q0 Q Q Q 0 Q Q Q Q Q0# Q# Q# Q# Q# Q# Q# Q# M0 0 M M M M 0 M M 0 M K0 0 K0# K K# 0 00 V_P KT-OIMM00-GP.00.E V V V V V V V 0 V 0 V V V V GN 0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M M0 M M M M M M M M M M M M M M M_LK_R M_LK_R# M_LK_R M_LK_R# R 0KRJ--GP R 0KRJ--GP +.V_U +.V_RUN M_LK_R M_LK_R# M_LK_R M_LK_R# M WE# M # M # M_KE M M M # M 0 M M M_OT M_# M_KE +.V_RUN E UVKX-GP <ore esign> M_LK_R M_LK_R# M_LK_R M_LK_R# +0.V_R_VTT +.V_RUN Layout Note: Place these resistors close to M, all trace length Max=.". RN RNJ--GP RN RN RN RN0 RNJ--GP RNJ--GP RN RN RNJ--GP RNJ--GP RNJ--GP RNJ--GP UMMY- ate: Thursday, October 0, 00 heet of put near connector RN RN RN M_OT M M M M M M M M 0 M #0 M R# M_# M M Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RII-OIMM LOT ize ocument Number Rev ustom 00 RNJ--GP RN RNJ--GP RN RN RN0 UVKX-GP UMMY- RNJ--GP RNJ--GP RNJ--GP RNJ--GP RNJ--GP U0VKX-GP UMMY- UMMY-

16 I = IH OF UE 0 E E E E E E E0 E E E E E F F F F H F F F F F G G G G0 G G G G H H H H H H H H H H J J J J 0 E E E E E E E E F F F G G G G G G G G H H H H IHM-GP-NF H J J J K K L L L L L L L M M M M M M M M M N N N N N N N N N N P P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U V V V V V V V V W W W Y Y Y Y Y G H F H H J J J J IH_GN IH_GN IH_GN IH_GN,0,,,, +.V_LW Mini ard LN New ard TP TP TP TP PLT_RT# PI_WP# PI_MOO PI_# U_O# U_O# U_O# U_O# PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP NTF PIN PI_LK PI_#0 PI_MOI PI_MOO U +.V_RUN PLT_RT# R 0KRJ--GP GN I WP# LK O HOL# # MXLM-G-GP U PI_MOI PI_LK PI_HOL# RP 0 U_O#0 U_O# U_O# U_O# RN0KJ-L-GP Y U_O#0 U_O# U_O# GN LVG0GW--GP R 0R00-P UVKX-GP UVKX-GP R RJ-GP R RJ-GP R0 RJ-GP R RJ-GP R0 RF--GP PI_PLTRT# R0 0KRJ--GP UVKX-GP UVKX-GP UVKX-GP UVKX-GP +.V_RUN +.V_LW PIE TXN PIE TXP PIE TXN PIE TXP UVKX-GP U N PERN N PERP P PETN P PETP L PERN L PERP M PETN M PETP J PERN J PERP K PETN K PETP G PERN G PERP H PETN H PETP +.V_LW OF PI-Express PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# MI0RXN V MI0RXP V MI0TXN U MI0TXP U irect Media Interface MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP E PERN MI_LKN T E PIE TXN PERP MI_LKP T F PIE TXP PETN F PETP MI_ZOMP F MI_IROMP F PERN/GLN_RXN PERP/GLN_RXP UP0N PETN/GLN_TXN UP0P PETP/GLN_TXP UPN PI_LK_R UPP PI_#0_R PI_LK UPN PI_# PI_0# UPP F PI_#/GPIO/LGPIO UPN PI_MOI_R UPP PI_MOO_R PI_MOI UPN E PI_MIO UPP U_O#0 UPN N U_O# O0#/GPIO UPP N U_O# O#/GPIO0 UPN N U_O# O#/GPIO U W UPP W P U_O# O#/GPIO UPN Y M U_O# O#/GPIO UPP Y N U_O# O#/GPIO UPN W M U_O# O#/GPIO0 UPP W M U_O# O#/GPIO UPN V N U_O# O#/GPIO UPP V N U_O#0 O#/GPIO UP0N U P U_O# O0#/GPIO UP0P U P O#/GPIO UPN U U_RI_PN UPP U G URI G URI# IHM-GP-NF PI RN RNKJ--GP U 0 E E E0 G 0 F F E F0 0 F 0 F F G H G H G 0 H J PIRQ# E PIRQ# J PIRQ# PIRQ# U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN0 U_PP0 PI U_O# U_O# U_O#0 U_O# MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_IROMP_R REQ0# F GNT0# G REQ#/GPIO0 GNT#/GPIO REQ#/GPIO F GNT#/GPIO F REQ#/GPIO E GNT#/GPIO F LK_PIE_IH# LK_PIE_IH U_PN0 U_PP0 U_PN U_PP U_PN U_PP TP TP U_PN U_PP TP0 TP U_PN U_PP U_PN U_PP TP TP TP TP U_PN0 U_PP0 U_PN U_PP /E0# /E# /E# /E# IR# PR E PIRT# R EVEL# PERR# E PLOK# ERR# J TOP# TR# F FRME# PLTRT# PILK PME# R Interrupt I/F IHM-GP-NF OF PIRQE#/GPIO H PIRQF#/GPIO K PIRQG#/GPIO F PIRQH#/GPIO G U U U PI_REQ0# PI_GNT0# PI_REQ# PI_GNT# PI_REQ# PI_GNT# PI_REQ# PI_GNT# PI_IR# PIRT# PI_EVEL# PI_PERR# PI_PLOK# PI_ERR# PI_TOP# PI_TR# PI_FRME# PI_PLTRT# IH_PME# PI_PIRQE# PI_PIRQF# PI_PIRQG# PI_PIRQH# +.V_RUN luetooth New ard ard Reader MER LK_PI_IH TP PI_PIRQF# PI_TR# PI_REQ# PI_PIRQ# PI_PIRQ# PI_PIRQG# PI_REQ0# PI_PIRQH# PI_TOP# PI_PLOK# PI_IR# PI_PERR# PI_ERR# PI_PIRQE# PI_PIRQ# PI_PIRQ# PI_GNT0# R KRJ--GP PI_# R KRJ--GP PI_GNT# R KRJ--GP OOT IO trap PI_GNT#0 PI_# OOT IO Location 0 PI <ore esign> 0 swap override strap PI_GNT# R RF-L-GP TP TP TP low = swap override enable high = default U Pair 0 0 U U evice RRVE MINI R RRVE PI LP(efault) U LUETOOTH NEW R RRVE RRVE ard Reader MER +.V_RUN Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-PI/PIE/MI/U/GN(/) ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of RN RN RN PI_EVEL# PI_REQ# PI_FRME# PI_REQ# RN RNKJ--GP RNKJ--GP RN RNKJ--GP RNKJ--GP RNKJ--GP

17 I = IH IH_RTX R 0MRJ-L-GP X IH_RTX P0VJN-GP 0 P0VJN-GP X-KHZ-GPU IH_Z_OE_ITLK IH_Z_OE_YN IH_Z_OE_RT# IH_OUT_OE +.V_RUN P0VN-GP H O +RT_ELL R +RT_ELL T_RXN0_ T_RXP0_ T_TXN0 T_TXP0 T_RXN_ T_RXP_ T_TXN T_TXP IH_RTRT# Place within 00 mil of. R RF-L-GP 0 P0VN-GP 0KRF-L-GP 0 U0VKX-GP R 0KRF-L-GP R0 RJ--GP R RJ--GP R0 RJ--GP R RJ--GP TP G GP-OPEN U0VKX-GP IH_IN_OE IH_RTRT# RTRT# M_INTRUER# IH_INTVRMEN LN00_LP R0 GPIO 0U0VKX-GP 0U0VKX-GP 0U0VKX-GP 0U0VKX-GP 0KRJ--GP GLN_OMP Z_IT_LK Z_YN_R Z_RT#_R Z_TOUT_R T_LE# T_TXN0_ T_TXP0_ T_TXN_ T_TXP_ OF U RTX RTX RTRT# F0 RTRT# INTRUER# INTVRMEN LN00_LP E GLN_LK LN_RTYN F LN_RX0 G LN_RX LN_RX LN_TX0 LN_TX E LN_TX 0 GLN_OK#/GPIO GLN_OMPI GLN_OMPO F H_IT_LK H H_YN E H_RT# F H_IN0 G H_IN H H_IN E H_IN G H_OUT G H_OK_EN#/GPIO E H_OK_RT#/GPIO G TLE# J T0RXN H T0RXP F T0TXN G T0TXP H TRXN J TRXP G TTXN F TTXP IHM-GP-NF RT LP LN / GLN PU IH T FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/GPIO 0GTE 0M# PRTP# PLP# FERR# PUPWRG IGNNE# INIT# INTR RIN# NMI MI# TPLK# THRMTRIP# PEI TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP T_LKN T_LKP TRI# TRI K K L K K J J N J J E J F E G L F F H H J J H LP_L0 LP_L LP_L LP_L H_PRTP# H_FERR#_R LP_L[0..] LP_LFRME#, K0GTE H_0M# H_PRTP#,, H_PLP# R RJ--GP H_PWRGOO, H_IGNNE# H_INIT# H_INTR H_NMI H_MI# H_TPLK# G H_THERMTRIP_R H_THERMTRIP_ R RF-L-GP G Placed Within " from. H J G F H J E0 F0 LK_PIE_T# LK_PIE_T TRI R RF-L-GP Place within 00 mils from. LP_L[0..], +.V_RUN R 0KRJ--GP +.0V_P R RJ--GP H_FERR# +.V_RUN R 0KRJ--GP KRIN# +.0V_P R RJ--GP R H_THRMTRIP#,,, 0RJ--GP 00.0/00 +RT_ELL R 0KRF-L-GP R 0KRF-L-GP IH_INTVRMEN LN00_LP integrated Vccus_0,Vccus_,VccL_ INTVRMEN High=Enable Low=isable integrated VccLan_0VccL_0 LN00_LP High=Enable Low=isable <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R MRJ--GP M_INTRUER# IH-LN/H/T/LP(/) ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

18 I = IH +.V_LW +.V_RUN RN0 R 0KRJ--GP +.V_RUN RNKJ--GP R 0KRJ--GP RN RN RN0KJ--GP RNKJ--GP R 0KRJ--GP R KRJ--GP R KRJ--GP R 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R0 KRJ--GP R 0KRJ--GP RN RN0KJ--GP M_T M_LK LINKLERT# ME_E_T ME_E_LK PIE_WKE# M_LERT# PM_TLOW#_R ITP_RT#_ IH_RI# EMI# H_TP_PU# H_TP_PI# PM_LKRUN# INT_ERIRQ GPIO EI# EWI# GPIO LKTREQ# itpm elect, M_LK, M_T TP ITP_RT#_ PM_YN# H_TP_PI# H_TP_PU# PM_LKRUN# 0, PIE_WKE# INT_ERIRQ THERM_I#, VGTE_PWRG EI# TP R 0RJ--GP EWI# EMI# TP TP TP TP TP TP LKTREQ# TP _PKR MH_IH_YN# TP LINKLERT# ME_E_LK ME_E_T IH_RI# U_TT# ITP_RT#_ M_LERT# H_TP_PI# H_TP_PU# PIE_WKE# INT_ERIRQ VGTE_PWRG IH_TP EI# EWI# EMI# GPIO GPIO GPIO GPIO GPIO0 GPIO GPIO GPIO LK_EL0 LK_EL GPIO itpm_en IH_TP +.V_RUN OF U G MLK MT E LINKLERT#/GPIO0/LGPIO MLINK0 MLINK F R U_TT#/LPP# G Y_RT# M PMYN#/GPIO0 MLERT#/GPIO TP_PI# E TP_PU# L LKRUN# E0 WKE# M ERIRQ J THRM# 0 RI# VRMPWRG T G TH/GPIO H TH/GPIO G TH/GPIO GPIO LN_PHY_PWR_TRL/GPIO ENERGY_ETET/GPIO E TH0/GPIO K GPIO F GPIO0 J LOK/GPIO GPIO GPIO L TLKREQ#/GPIO E LO/GPIO G TOUT0/GPIO F TOUT/GPIO H GPIO GPIO/LGPIO M PKR J MH_YN# TP H0 PWM0 J0 PWM J PWM IHM-GP-NF M T GPIO locks Y GPIO Power MGT MI GPIO ontroller Link T0GP T0GP/GPIO H TGP TGP/GPIO F TGP TGP/GPIO E TGP TGP/GPIO 0 LK H LK F ULK P LP_# LP_# E LP_# G _TTE#/GPIO PWROK PRLPVR/GPIO TLOW# PWRTN# LN_RT# RMRT# K_PWRG LPWROK LP_M# 0 G0 M R 0 R R L_LK0 F L_LK L_T0 F L_T L_VREF0 L_VREF L_RT0# F L_RT# GPIO/MEM_LE GPIO0/U_PWR_K GPIO/_PRNT GPIO/WOL_EN 0 LK Gen elect IH_ULK _LP_# PM_LP_# GPIO PM_PWROK PM_TLOW#_R LN_RT# M_PWROK PM_LP_M# L_VREF0_IH L_VREF_IH GPIO GPIO0 GPIO LK_M_IH LK_M_IH IH_ULK PM_LP_#,, TP TP PRLPVR, PM_PWRTN# RMRT#_K K_PWRG M_PWROK TP L_LK0 L_T0 L_RT#0 TP0 0 U0VKX-GP +.V_LW R KRF-GP TGP TGP TGP T0GP PM_PWROK PRLPVR LN_RT# RMRT#_K GPIO0 GPIO GPIO GPIO GPIO R RF--GP M_PWROK R0 0KRJ--GP R 00KRJ--GP R 0R00-P R 0KRJ--GP R0 0KRJ--GP R0 0KRJ--GP R0 0KRJ--GP R0 0KRJ--GP R0 0KRJ--GP R 0R00-P +.V_RUN R KRF-GP U0VKX-GP RN R0 RF--GP RN0KJ--GP +.V_RUN PM_PWROK,, R 00KRJ--GP itpm_en R 00KRJ--GP itpm_en R 0KRJ--GP LK_EL0 LK_EL LK Gen select LK_EL0 0 = isable isable X X R R eligo = Enable 0KRJ--GP 0KRJ--GP Realtek 0 I 0 R 0KRJ--GP RN +.V_RUN LL_EL _LP_# U GN Y LVG0GW--GP R 0R00-P +.V_LW PM_LP_# PM_LP_#,,0,,,, RNKJ--GP,, IH_MT M_LK U N00PT M_T IH_MLK,, <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-GPIO/PM/L(/) ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

19 +RT_ELL +.0V_P R 0R00-P +.0V_P _V_PU_IO R 0R00-P +.V_RUN R 0R00-P +.V_RUN R 0R00-P +.V_LW R 0R00-P +.V_RUN +.V_LW _H R 0R00-P R0 0R00-P +.V_LW U0VKX-GP R 0R00-P OF +.0V_P UF I = IH RT _0 VREF_0 _0 VREF m _0 VREF_ E _0 VREF_U m _0 E _0 F 0 L 0 L 0 L 0 L 0 L *Within a given well, VREF needs to 0 L V_MIPLL_IH_0 +.V_RUN be up before the corresponding.v rail 0 M L 0 M E V_MIPLL_IH_0 0 P E IN-UH--GP +.V_RUN +V_RUN +.V_LW +V_LW 0 P E 0 T E 0 T E 0 U F R R 0 U G 0RJ--GP 0RJ--GP 0 V H 0 V H 0 V VREF_0 VREF_ J 0 V J 0 V K MI 0 V K 0 L U0VKX-GP UVKX-GP L m MIPLL R L M 0m MI W MI Y M N m V_PU_IO N V_PU_IO _V_PU_IO N +.V_RUN P G P +.V_RUN R J R R0 R V_PORE_IH_0 0 0R00-P R T T F0 T U0VKX-GP G T 0 U U PI_P_ORE_0 V F V G +.V_RUN +TPLL U W G J +.V_RUN L W J K K Y L-0UH--GP Y R _LN m H J _H 0R00-P J m TPLL m UH J U_0[] U_0 TP U_0[] U_0 F TP0 R E U_[] U_ +.V_RUN +.V_RUN F G U_ F U_[] 0R-0-U-GP H J U_ +.V_RUN U U_ IN-UH--GP E L U_ E F _GLN_PLL G0 G U_ F +.V_RUN H0 J0 U_ T U_ T U_ T U_ T _U U_ T U_ T U_ U U_ U U_ V G0 U_ V +.V_RUN G U_ W U_ W 0R00-P V_U_0 U_ Y R U_ Y U_ T J UPLL m L_0 G 0 U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP 0 U0VKX-GP U0VKX-GP U0VKX-GP m 0UVMX-GP HH-0PT 0UVKX-GP HH-0PT ORE UVKX-GP 0UVMX-GP U0VKX-GP m UVKX-GP U0VKX-GP U0VKX-GP GP 0m 0UVMX-GP 0UVMX-GP U0VKX-GP U0VKX-GP T T0UVM-LGP U0VKX-GP P_ORE U0VKX-GP 0 U0VKX-GP 0 U0VKX-GP PI U0VKX-GP E UVKX-GP U0VKX-GP U0VKX-GP U0VKX-GP RX 0UVMX-GP 0 U0VKX-GP 0 U0VKX-GP U0VKX-GP 0 U0VKX-GP U0VKX-GP PU TX m 0UVMX-GP 0 U0VKX-GP 0 U0VKX-GP U0VKX-GP 0 U0VKX-GP PU m 0 U0VKX-GP U0VKX-GP 0 0UVKX-GP UVKX-GP U0VKX-GP G m U0VKX-GP L_ L_ L_ U ORE U0VKX-GP U0VKX-GP LN0 <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-POWER(/) Number Rev 00 ate: Thursday, eptember, 00 heet of 0 LN_0 00.0/00 LN_0 U_0[] U0VKX-GP _LN_ LN_ m LN_ U_[] 00.0/00 +.V_RUN _GLN_PLL GLNPLL m GLN_ GLN_ +.V_RUN E +.V_RUN GLN_ E UVKX-GP R GLN L_ R V_GLN_0 GLN_ m 0R00-P ize ocument 0R-0-U-GP 00.0/00 IHM-GP-NF ustom U0VKX-GP U0VKX-GP 0m U0VKX-GP GLN POWER U0VKX-GP

20 I = LOM +.V_LOM +.V_LN +.V_LOM TP0 TP TP +.V_RUN TP +.V_LN +.V_LN R KRJ--GP +.V_LN LOM_ILE# 00.0/00 LN R LNPWR 0R00-P LNV R KRF--GP LNRET R 0KRJ--GP TRL R 0KRJ--GP TRL TP LNHP TP LNHN MI0- MI- MI0+ MI+ U N# N# N# N# 0 LOM_ILE# VUX_VLL WITH_ VMIN_VLL WITH_VUX RET P_ P_ HP HN MI0- MI- MI0+ MI+ VL V V VL VL VL VL RXN TXN N# N# RXP TXP N# N# VO_TTL VO_TTL VO_TTL VO_TTL VO_TTL VP_T V VL TTPT TETMOE R 0RJ--GP V V V V PU_VO_TTL# PU_VO_TTL# V V V V E00-0-NN000-GP VP_T VP_LK LE_LINK# N# LE_P# 0 LE_T# GN WKE# PERT# REFLKP REFLKN PIE_TXN 0 PIE_TXP PIE_RXN PIE_RXP XTLI XTLO R KRJ--GP R KRJ--GP LN_RXN LN_RXP LNX LNX +.V_LN U0VKX-GP U0VKX-GP R 0MRJ-L-GP X LNX LNX XTL-MHZ-GP P0VJN-GP PIE_WKE#, PLT_RT#,,,,, LK_PIE_LN LK_PIE_LN# PIE_RXN PIE_RXP PIE_TXN PIE_TXP 0 P0VJN-GP +.V_LN KP0VKX-GP U0VKX-GP U0VKX-GP +.V_LOM U0VKX-GP KP0VKX-GP KP0VKX-GP UVKX-GP U0VKX-GP +.V_LOM +.V_LN +.V_RUN R0 0R-0-U-GP +.V_LW R 0R-0-U-GP Q PM_LN_ENLE U0VKX-GP G R 0KRJ--GP G Q N00-F-GP G U0VKX-GP KP0VKX-GP U0VKX-GP 0 KP0VKX-GP U0VKX-GP KP0VKX-GP UVKX-GP O0-GP U0VKX-GP U0VKX-GP 0 UVKX-GP UVKX-GP 0UVMX-GP MI0+ MI0- MI+ MI- MI0_LN R RF-GP R RF-GP MI_LN R RF-GP R RF-GP 0UVKX-GP 0UVKX-GP <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LN Marvell-E00 ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet 0 of

21 I = IO Please close to pin. +.V_PHY +.V_PHY +.V_RUN UVKX-GP 0 UVKX-GP Please close to pin and pin. X_# _WP _# X_/_T X_/M_ X_/M T0/X_/M_0 X_/M_ M_IN# X_/M LK/X_/M_LK X_0 X_WP# X_R _T/X_WE# _T/X_RE# X_LE X_E# X_LE UVKX-GP +.V_RUN_R X_# _WP _# X_/_T X_/M_ X_/M T0/X_/M_0 X_/M_ M_IN# X_/M LK/X_/M_LK X_0 X_WP# X_R _T/X_WE# _T/X_RE# X_LE X_E# X_LE UVKX-GP UVKX-GP U VREG P 0 P P P P P P P P P0 P P P P P 0 P P P P R_V M_ M_ V_PLL VREG 0 R 0R00-P MOE_EL _M R_RREF R_RT# 00.0/00 U_PP0 U_PN0 XTL_TR R_K R_ R_O R_I _M R R_RT#_R LM0N-GP 00.0/00 R KRF--GP +.V_PHY +.V_PHY LK_M_R 00.0/00 PLT_RT#,,0,,, U_PN0 M_LK M_LK U_PN0 U_PP0 _LK/X_/M_LK _LK _LK U_PP0 +.V_PHY Power mode select No staff R and for power saving mode. R_ R_K R_O R_I MOE_EL R0 0KRJ--GP V_IN N#0 N# N# MOE_EL _M GPIO0 RREF RT# P M U0VKX-GP R0 KRJ--GP U0VKX-GP GN GN GN GN V V 00 UVKX-GP RTE-GRT-GP XTL_TR XTLI XTLO K O I 0 0 UVKX-GP R0 KRF-GP R R 00KRJ--GP 0KRJ--GP R0 0R00-P L LWN00QLUGP R 0R00-P P0VJN--GP 0 P0VJN--GP U K I O ORG GN TN-H--GP UVKX-GP P0VJN-GP <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserve for changing U VI/PI. RTE ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

22 I = UIO +.V_RUN U0VKX-GP 0 UVKX-GP U0VKX-GP Place close to pin Place close to pin +V IH_Z_OE_ITLK IH_IN_OE IH_OUT_OE IH_Z_OE_YN IH_Z_OE_RT# U_MI_IN0 R R +.V_RUN RJ--GP R 0R00-P U0VKX-GP RJ--GP IH_Z_OE_ITLK_R _Z_OE_IN0_R P0VN-GP U_MI_LK U_MI_IN0 V_ORE V_ORE 0 N#0/OTP V_IO 0 U ITLK I_OE O YN RT# MI_LK VOL_UP/MI_0/GPIO VOL_N/MI_/GPIO EP/GPIO0/PIF_OUT0OR PIF_OUT0 V V ENE_ ENE_/N# PORT_L PORT_R N# PORT_L PORT_R VREFOUT_ PORT_L PORT_R VREFOUT_ PORT_L PORT_R PORTE_L PORTE_R VREFOUT_E/GPIO PORTF_L PORTF_R GPIO 0 N# N# N#0 0 PP 0 U0VKX-GP U_ENE_ U_ENE_ U_HP_OUT_L U_HP_OUT_R U_EXT_MI_L U_EXT_MI_R U_VREFOUT_ U_INT_MI_L U_INT_MI_R U_VREFOUT_ U_LINE_OUT_L U_LINE_OUT_R U_P_P U0VKX-GP 0 +V U0VKX-GP U0VKX-GP R KRJ--GP UVKX-GP U_P_P Trace width> mils P P +V R KRF--GP R R U0VKX-GP _PKR_R KRF-L-GP 0KRF-L-GP KP0VKX-GP U_HP_OUT_L U_HP_OUT_R U_EXT_MI_L 0 U_EXT_MI_R 0 U_VREFOUT_ 0 INT_MI_L_R 0 U_LINE_OUT_L U_LINE_OUT_R U_HP_J#,0 EXT_MI_J# 0 Port ---> HP Port ---> Ext Mic Port ---> Int Mic Port ---> peaker From _PKR MONO_OUT GPIO GPIO GPIO/PIF_OUT GN HNLGXX-GP P VREFFILT U_P U_VREFFLT 0UVMX-GP zalia I/F EMI IH_OUT_OE IH_Z_OE_OUT R RJ--GP U_MI_LK_G E P0VJN-GP +.V_RUN U Y OE# GN LVG-GP R RJ--GP U_MI_LK <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R 0KRF-L-GP R KRF--GP 0UVMX-GP R UMMY- U0VKX-GP UIO OE H ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

23 I = UIO +V_RUN U_HP_OUT_R U_HP_OUT_L L LMPG00N-GP 0ohm 00MHz 000m 0.0ohm +V_PK_MP lose to U. lose to U. 0 U_PK_L 0 U_PK_L 0 U_PK_R 0 U_PK_R 0 U_HP_JK_R 0 U_HP_JK_L 0UVMX-GP KRJ--GP R0 U_HP_OUT_R 00 U_HP_OUT_L 00 0UVMX-GP 0UVMX-GP R KRJ--GP U0VKX-GP U_PK_L U_PK_L U_PK_R U_PK_R U0VKX-GP U_HP_JK_R U_HP_JK_L U_MP_GIN U_MP_GIN U_HP_OUT_R U_HP_OUT_L U OUTL+ OUTL- OUTR- 0 OUTR+ HPR HPL GIN GIN HP_INR HP_INL PV PGN PGN PV GN GN PV PGN HPV P V 0 U_P PKR_INR PKR_INL U_LIN_R U_LIN_L U_I U_ET +V_PK_MP 0UVMX-GP +V_PK_MP 0UVKX-GP 0UVKX-GP +V +V_PK_MP U_LINE_OUT_R U_LINE_OUT_L lose to Pin +V_PK_MP UVKX-GP From E MP_MUTE# +V_RUN ignal inverter for speaker shutdown U +V_PK_MP U_HP_J,0 U_HP_J# U_HP_J# MP_MUTE# U_HP_J U_HP_EN N00PT +V +V_PK_MP +V_PK_MP GIN ETTING MP_REGEN U_ET U_I R K_P_R K_P From E U_HP_J# U_PK_ENLE# MP_MUTE# +V_PK_MP PKR_EN# MUTE# HP_EN REGEN P 0 N VOUT I ET P U0VKX-GP 00 U0VKX-GP U0VKX-GP R 00KRJ--GP UVKX-GP MX-GP UVKX-GP U0VKX-GP UVKX-GP R 00KRJ--GP R 00KRJ--GP UVKX-GP U0VKX-GP 0KRJ--GP KRJ--GP R U N00PT U_PK_ENLE# MP_MUTE#_R R 0RJ--GP U_HP_EN MP_REGEN MP_P U0VKX-GP MP_N R 0RJ--GP R 00 00KRJ--GP R 00KRJ--GP R 0MRJ-L-GP U0VKX-GP R 00KRJ--GP 0UVKX-GP U_PK_ENLE N_PK_EN# W--GP R0 00KRJ--GP U_MP_GIN R 00KRJ--GP U_MP_GIN Main source econd source R 00KRJ--GP R 00KRJ--GP 00.0/0 R R TP00 (.000.0) 00K No M MX (.0.0) No M 0 Ohm G0 GP-OPEN-PWR G GIN GIN GIN 0 0 d 0 0d 0.d.d R R No M No M 0.0uF 0.0uF 0 Ohm 00K No M No M GP-OPEN-PWR G GP-OPEN-PWR G GP-OPEN-PWR uf No M <ore esign> No M 0.uF 0uF.uF Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. 0uF.uF UIO MP/PEKER ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of

24 +.V_RT_LO 0UVMX-GP +.V_RUN P_VER P_VER P_VER0 +.V_RUN U0VKX-GP E_Tx +.V_RUN +.V_RUN P close to -GN pin pair L LMG0N-GP U0VKX-GP _I P_INT# MER_ET# PLK_K_R PLK_K K_THERMTRIP# P_VER0 P_VER P_VER VT RUNPWROK PLT_RT#_ R0 X_ PUORE_ON K_XI K_XO PLT_RT#_ LP_L0 LP_L LP_L LP_L EI#_K EWI#_K K_VORF E_PI_I E_PI_O E_PI_# E_PI_LK PLK_K LP_LFRME#, INT_ERIRQ PM_LKRUN# KRIN# K0GTE,,0,,,, PM_LP_# K_ GPIO0/T GPIO/ K_PWRTN# K_L GPIO0 M GPIO/L _IN# GPIO0 GPIO/ T_, LI_LOE# GPIO0 GPIO/L 0 T_L,, VGTE_PWRG IO_I GPIO 00.0/00 GPIO E_PI_WP#_R 0 R RUNPWROK_R GPIO0 0,, RUNPWROK 0 PWRLE 0R00-P GPIO P GPIO/G_PWM GPIO/_PWM 00.0/00 GPIO/H_PWM GPIO0/F_PWM _OFF GPIO/TK GPIO LUETOOTH_EN, RMRT#_K 0 K_GPIO GPIO/TM PI GPIO/HM,, PM_LP_# GPIO/TI GPIO GPIO WIFI_RF_EN 00.0/00 GPIO/E_PWM GPIO V_V_POK,, PM_PWROK R PM_PWROK_R GPIO/TRT# GPIO PI_ILE# 0R00-P GPIO0/TO H_V_EN E_Tx GPIO GPO/OUT_R/R E_Tx LON_OUT E_Rx E_Rx PUORE_ON R PUORE_ON_R GPIO/R# GPIO/IN_R 0R00-PEMI#_K GPIO GPO/R0 GPIO0 00.0/00 GPIO GPIO PM_LN_ENLE 0 TTN#_K GPIO GPIO TTN#_K, U_PWR_EN# 0 GPO/TRI# GPIO _ENLE R 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R KRJ--GP R 0KRJ--GP R0 0KRJ--GP U0VKX-GP X00 X0 X0-00.0/00 U0VKX-GP M VERION I M VERION I VER VER K LK EMI U0VKX-GP 0UVMX-GP R0 0RJ--GP VER U0VKX-GP P0VN-GP 0 U0 VREF GPI0/0 GPI/ GPI/ 00 GPI/ 0 GPIO0 GPIO0 0 GPI 0 GPI 0 GPI 0 GPI P0VJN--GP 0 P0VJN--GP / / GN GN GN GN GN GN R 0 V LP X X-KHZ-GPU KR-GP GN 0 0 GPIO ER/IR 0 0P0VKX-GP 0RJ--GP R 0R00-P U0VKX-GP GPIO0/LPP# LRT# LLK LFRME# L0 L L L ERIRQ GPIO/LKRUN# KRT# G0 EI#/GPIO GPIO/MI# GPIO/PWUREQ# R 0RJ--GP OF VORF WPEL0G-GP PLT_RT#,,0,,, R 0MR-GP 0UVMX-GP T_IN# E_PI_I E_PI_O E_PI_# E_PI_LK LP_L[0..], GMH_L_ON R 0KRJ--GP 0 U0VKX-GP P_I_E PM_PWRTN# L_TT_EN K_P TLOW_LE RIGHTNE THERM_ L_TT TPT TPLK +.V_RT_LO 0KRJ--GP R, PURE_HW_HUTOWN# 00.0/00 R0 0R00-P MP_MUTE# K_ET# L_L_ET# P_,,, H_THRMTRIP# R 0RJ--GP EWI# EI# EMI# K_XI K_XO ERT#_ Q0 H0PT-GP R E 0RJ--GP K_L ERT# +.0V_P --GP U0 K_THERMTRIP# Q H0PT-GP KX/KLKIN KX 0 GPIO/LKOUT GPIO/T GPIO0/T GPIO/T GPIO/_PWM GPIO/_PWM GPIO/_PWM GPIO/PT GPIO/PLK GPIO/PT 0 GPIO/PLK GPIO/PT GPIO/PLK F_I F_O 0 E_PI_LK_ F_0# F_K E --GP R KRJ--GP R 0RJ--GP R 0RJ--GP EWI#_K EI#_K EMI#_K P/ FIU U0VKX-GP UVKX-GP --GP U N00PT <ore esign> K_ R 0RJ--GP E_Rx K0GTE KRIN# K_L K_ T_ T_L KOUT0/JENK# KOUT/TK KOUT/TM KOUT/TI 0 KOUT/JEN0# KOUT/TO KOUT/R# KOUT K KOUT KOUT KOUT0 0 KOUT KOUT/GPIO KOUT/GPIO KOUT/GPIO KOUT/GPIO/XOR_OUT GPIO0/KOUT GPIO/KOUT I = K THERM_L P_L R 0KRJ--GP K_PWRTN# R 00KRJ--GP LI_LOE# R 0KRJ--GP L_L_ET# R0 00KRJ--GP K_ET# R0 00KRJ--GP MER_ET# R0 00KRJ--GP K_THERMTRIP# R0 00KRJ--GP _ENLE R0 0KRJ--GP KOL0 R00 0KRJ--GP K_GPIO R0 0KRJ--GP IO_I R0 0KRJ--GP IO_I: Pull High for iscrete K internal Pull Low for UM OF KIN0 KIN KIN KIN KIN KIN KIN 0 KIN _POR# WPEL0G-GP RN RN KOL0 KOL KOL KOL KOL KOL KOL KOL KOL KOL KOL0 KOL KOL KOL KOL KOL KOL KOL KROW0 KROW KROW KROW KROW KROW KROW KROW ERT# +.V_RUN +.V_RT_LO 00.0/00 KOL[0..] KROW[0..] Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. K Winbond WPL ize ocument Number Rev ustom 00 ate: Thursday, October 0, 00 heet of RN0KJ--GP RNKJ--GP RN RNKJ--GP TP E UVKX-GP