Acoustic Level Dynamic Compression Characteristics with FPGA Implementation

Transcription

1 Poceedigs of te 7t WSEAS Iteatioal Cofeece o Sigal, Speec ad Image Pocessig, Beijig, Cia, Septembe 5-7, 27 8 Acoustic Level Dyamic Compessio Caacteistics wit FPGA Implemetatio Sugag Wei Depatmet of Poducatio Sciece ad Tecology, Guma Uivesity, Japa wei@cs.guma-u.ac.jp Weai Xu Dailia Maitime Uivesity, Cia wxu@ewmail.dlmu.edu.c Abstact: I tis pape, we popose a FPGA desig of a audio sigal level compesso, based o a appoximatio algoitm usig a polyomial. To implemet a compessio caacteistic i a digital audio system, te gai calculatio wit factioal umbes is pefomed by usig a polyomial expessio to appoximate te powe opeatio, te te compesso ca be desiged wit a umbe of additios, multiplicatios ad a divisio. Te aitmetic cicuits wee implemeted i FPGA tecology ad te 6-bit compesso used 54 logic elemets ad 352 flip-flops of te adwae esouce of EP2K2EFC484-2X fom Altea. Te poposed compesso ca be applied as a fuctioal uit i a o-cip audio system. Te pefomace of te poposed compesso is evaluated by aalysis ad simulatio. Key Wods: Audio sigal, Dyamic age cotol, Compessio atio, Gai, FPGA. Itoductio Digital audio systems ave advatages i audio sigal tasfeig, ecodig ad delay cotollig ove covetioal aalog systems. Vaious digital filtes o digital sigal pocessos(dsps) fo gettig te fequecy esposes ave bee poposed[]. It is desied tat a audio system wit a umbe of fuctioal modules suc as aalog-to-digital ad digitalto-aalog covetes, CPU, DSPs, memoy ad dyamic age cotolles is implemeted o a VLSI cip, called audio system o a cip[2, 3, 4]. Recetly, FPGA (Field Pogammable Gate Aay) cips ae ofte used to implemet a digital system fo soteig te developmet time to maket, because igpefomace FPGAs ave bee equipped wit DSPs, memoy ad logic elemets[5]. Dyamic age cotol of audio sigal levels is a geeal equiemet to get soud effects[3]. Compessos ad limites ae suc dyamic age cotolles ad may be also used to pevet peaks exceedig te maximum usable value i a audio system. As sow i Fig., a dyamic age cotolle pefoms te peak detectio, gai calculatio, attack time ad elease time cotol i te fuctioal block, GAIN CONTROL, ad te applys te gai to cotol te sigal level. I a covetioal dyamic age cotolle wit aalog cicuits, a voltage-cotolled amplifie (VCA) is used[4, 6] to cotol sigal level. v i GAIN CONTROL GAIN CALCULATION ATTACK/ RELEASE Figue : Dyamic age cotolle. I geeal, te VCA cicuit as te oliea iputoutput caacteistics, wic esult i te amoic distotio i te output sigal. Digital dyamic age cotolles may implemet te same fuctioal blocks as te aalog cicuits. Tus, te amoic distotio aise by te VCA may be avoided by usig te multiplicatio. Howeve, te mai poblem is to pefom te calculatio fo te powe tasfomatio, tat is, ow x y ( < x, y < ) is calculated efficietly wit few opeatios ad less adwae. I tis pape, a polyomial expessio is applied fo te powe tasfomatio, so tat te efficiet adwae implemetatio i FPGA tecology ca be easily acieved by usig a umbe of logic elemets ad flip-flops i a FPGA cip. To educe te adwae esouces, we popose a acitectue wit fewe multiplies, ad te multiplies ae desiged by G v o

2 Poceedigs of te 7t WSEAS Iteatioal Cofeece o Sigal, Speec ad Image Pocessig, Beijig, Cia, Septembe 5-7, 27 9 usig a sift-accumulatio algoitm. Te simulatio esults of 6-bit, 24-bit ad 32-bit compessos desiged usig FPGA implemetatio tecology sow tat te poposed compessio caacteistics ae vey close to te ideal oes. 2 Caacteistics of Compesso V o (db) V T : p: Te audio sigal levels ae usually expessed by multiples of te efeece voltage ad ae epeseted by decibels(db). Fo a compesso, te iput ad output sigal levels ae deoted as V i ad V o,espectively, ad tey ave te followig elatiosips: V i = 2log (A i ), () A i = v i, (2) V o = 2log (A o ), (3) A o = v o, (4) wee v i ad v o ae te iput ad output sigals as sow i Fig., espectively. A i ad A o ave te values elative to te maximum magitude of iput sigal wic is te efeece value i a digital audio system. Witout loss of geeality, we ca suppose V i, V o (db), te v i ad v o ae eal umbes i [-,] ad A i, A o ae eal umbes i [,]. Te compessio caacteistics ae defied i Fig.2, wic ae measued wit te RMS(oot mea squae) values of te sigal s magitudes. We te audio level V i of te iput sigal of a compesso is geate ta a tesold level V T, te sigal level is compessed wit a compessio atio p. Tat is, if V i > V T te V i : V o = p : ( p ). We p =, te compesso becomes a limite. Te elatiosip betwee te iput ad output levels is epeseted by te followig equatio: V o = (/p)(vi V T ) + V T (V i > V T ) V i (V i V T ). (5) Te attack time ad elease time cotol is a vey impotat fuctio to make te dyamic soud effects. I ou appoac, as sow i Fig., a AT- TACK/RELEASE fuctioal block is desiged ot oly to make te soud effects but also to smoot te gai obtaied i te GAIN CALCULATION block. Let te iput ad output of ATTACK/RELEASE block be G i ad G, espectively. G I is te gai obtaied fom te GAIN CALCULATION block, wee < G i. Te attack time ad elease time ae defied as follows: Let G = G i = G iitially. At te time t =, G i caged ad as a ew value (G i G ), te G is V T Figue 2: Compessio caacteistic. V i (db) cagig fom G to G i by te followig equatio, G = G i + (G G i ) exp( t/t ). (6) We G i < G, T a = T is defied as te attack time, wile T = T is te elease time we G i > G. I geeal, T T a. Fom Eq.(6), we ave G/ G i = exp( t/t ), (7) wee G = G G ad G i = G i G. Tus, te attack time ad elease time ae te itevals, wile te value caged o te output of ATTACK/RELEASE as become 63.2% of tat caged o te iput of te ATTACK/RELEASE block[?]. 3 FPGA Desig fo te Gai Computatio wit a Polyomial Expessio 3. Compessio Caacteistics wit a Polyomial Expessio We begi te computatio by cosideig te compessio caacteistics wit a compessio atio p(p ) as sow i Fig.2. Fom Eqs.(),(3) ad (5), we ave te followig elatiosip betwee te iput ad output sigals of te compesso wit a compessio atio p: A o = v (p )/p t A /p i (A i v t ) A i (A i < v t ), (8) wee v t is te sigal tesold avig a positive value wit espect to te level tesold V T satisfyig V T =

3 Poceedigs of te 7t WSEAS Iteatioal Cofeece o Sigal, Speec ad Image Pocessig, Beijig, Cia, Septembe 5-7, 27 v i REG-V MYP G v o ABS ATTACK/ RELEASE G i -v t A i α CMP x f (x) m REG-P A i f DIV f/ A i - SUB Figue 3: Acitectue of te poposed compesso. 2log (v t ). Te epesetatio of te gai, G, may be obtaied by (vt /A G = i ) (p )/p (A i v t ) (A i < v t ), (9) A o = G A i. () Because of te same sigs of v i ad v o sow i Fig., Eq.() is a geeal fom of Eq.(). v o = G v i. () It is difficult to obtai te gai by Eq.(9) diectly, wic as te powe calculatio wit factioal umbes. To simplify te powe calculatio, a polyomial expessio is deived to appoximate te compessio caacteistics. I te case of A i v t, te gai may be epeseted by te followig equatio: wee, G = (/A i ) f, (2) f = A i v (p )/p t A /p i. (3) Obviously, f < A i ad < G. Let α = A i v t, te Eq.(3) may be expessed by a polyomial of degee m of α to appoximate te gai calculatio as follows: f m (α) = b + b α + b 2 α b m α m. (4) Sice f m () =, te b =. Substitutig te polyomial expessio ad a two-value vaiable δ, } ito Eq.(9), (α > ) δ = (α ), (5) ad let x = δ α, (6) te te gai ca be expessed as follows: G = (δ/a i ) f m (α) (7) = f m (x)/a i. Tus te powe calculatio wit factioal umbes fo gettig compessio caacteistics is equivalet to te calculatio of a divisio ad te polyomial expessio wit paametes (b, b 2,..., b m ), wic is easily pefomed by usig aitmetic cicuits suc as adde, multiplie ad divide as sow i Fig.3. If te paametes ae set to b = ad b i = (i = 2,...m), fo α > ad G = α/a i = v t /A i A o = G A i = v t. Tus a limite caacteistic, p =, is obtaied. Obviously, te lage te degee of te polyomial expessio, m, te close to te ideal te appoximatio caacteistic is. Te least aquaes metod may be used to calculate te paametes (b, b 2,..., b m ) fo a give compessio caacteistics. To obtai te paametes i a sot time, a itepolatig metod may be used fo m 7[8]. 3.2 Acitectue of te Poposed Compesso We suppose tat te iput ad output audio sigals of te poposed compesso ae epeseted i a fixedpoit biay umbe epesetatio, called te two s complemet epesetatio, as follows, x = x.x x 2 x, (8)

4 Poceedigs of te 7t WSEAS Iteatioal Cofeece o Sigal, Speec ad Image Pocessig, Beijig, Cia, Septembe 5-7, 27 wee x i, } fo i =,, 2,,, ad x expesses te sig of x. Te value of x is obtaied by usig te followig equatio, x = x + x i 2 i. (9) i= i i C SWITCH C G (t-) REG Obviously, x as a value age of [, ). te umbe epesetatio is also applied to te ie aitmetic cicuits of te poposed compesso. A pipelie-type acitectue of te compesso is sow i Fig.3, i wic REG-P ad REG-V ae two pipelie egistes. Te block CMP implemets (3) ad (4), ad te mai aitmetic cicuits ae te multiplies fo computig te polyomial expessio ad implemetig te attack/elease fuctio ad te divide. i (a) Oigial cicuit SEL C G (t-) SEL SEL x b Iit Clkf REG f SWITCH REG (b) Modified cicuit Figue 5: Attack/elease cicuit. Figue 4: Aitmetic cicuit fo computig a polyomial expessio. We coside te polyomial expessio of degee m give i (7), wic ca be calculated by pefomig 2m times of multiplicatios ad m times of additios. We ca use te Hoe s ule to calculate te polyomail as follows: f m (x) = b x + b 2 x b m x m = (( ((b m x + b m )x + b 2 )x + b )x. Teefoe, te above calculatio ca be implemeted by pefomig te followig poduct-sum opeatio epeatedly m times, fi = f i x + b m i f = b m, (2) ad te aitmetic cicuit fo te polyomial expessio is desiged as sow i Fig. 4. Figue 5(a) sows a attack/elease cicuit pefomig two multiplicatios ad oe additio fo te gai data fom eac sigal sample. Te cicuit SWITCH switces paametes (C, C ), by compaig G(t ) wit G I (t), betwee (, ) fo te attack time cotol ad (, ) fo te elease time cotol, espectively. (, (C, C ) = ) (G i (t) > G(t )) (, ) (G i (t) G(t )), (2) wee t deotes a samplig time. Te paametes, (, ) ad (, ), ae obtaied by te followig equatios. = exp( /(f s T a + )), (22) =, (23) = exp( /(f s T + )), (24) =, (25) wee f s is te samplig fequecy of a digital audio system. I te cicuit, G(t) = C G(t ) + C G i (t), (26) is calculated usig two multiplies, oe adde ad a egiste. To educe te adwae esouces, we pefom te calculatio i two steps as follows: [Attack/elease time cotol] step REG := C G(t );

5 Poceedigs of te 7t WSEAS Iteatioal Cofeece o Sigal, Speec ad Image Pocessig, Beijig, Cia, Septembe 5-7, 27 2 i Table ad Table 2. Table : Resouce used i mai cicuits of te 6-bit compesso. Elemets DIV TOTAL LEs Registes Figue 6: Te gai smooted by attack/elease cicuit. Table 2: Resouce used i compessos. Wodlegt 6-bit 24-bit 32-bit LEs Pis Registes Clock Feq.(MHz) step 2 G(t) := C G i (t) + REG. Tus, te attack/elease fuctio ca be implemeted by usig oe multiplie ad some selectos as sow i Fig.5(b). Te attec/elease cicuit is desiged ot oly to make te soud effects but also to smoot te gai G i (t). Fig.6 illustates te smooted gai we te iput is a sie wave. 3.3 FPGA desig fo te aitmetic cicuits Fo te implemetatio of te poposed compesso, we use a field pogammable gate aay(fpga) cip, EP2K2EFC484-2X fom Altea, as te taget device. I te FPGA cip, tee ae 8,32 logic elemets (LEs) wit te.22µ VLSI pocess. Oe LE ca implemet a fou-iput combiatioal logic ad oe egiste. Cay-cais ae equipped fo fast cay popagatios betwee LEs duig additios. We use a adwae desciptio laguage, VHDL, to descibe te aitmetic cicuits of te compesso. Te te cicuits ae sytesized by usig FPGA libay of Altea ad mapped ito te FPGA cip EP2K2EFC484-2X. As metioed above, te multiplicatio ad divisio cicuits ae most complicated pats i te poposed compesso. To ealize a compact FPGA desig, we implemeted te multiplie ad te divide usig a sift-accumulatio algoitm ad estoig divisio algoitm, espectively. A -bit multiplie is desiged wit a -bit adde, oe 2-bit ad oe -bit egiste, ad te output is te MSB-side bits of te multiplicatio esult. Te divide as a simila stuctue wit te multiplie. Te esultig amouts of adwae esouces used i te compesso ad te clock fequecies fo 6-bit, 24-bit ad 32-bit compessos ae summaied 4 Expeimets ad eo aalysis Figue 4 sows te compessio caacteistics usig polyomial of degee seve, i wic te tesold level is set to -4 db ad te compessio atios ae set to,.4, 2, 4, 6,, espectively. Te paametes of te polyomials wee obtaied by usig te itepalatig metod. ad te caacteistics ae close to te ideal oes. We calculate te mea eo betwee te appoximatio caacteistics ad te ideal oes fo te pefomace evaluatio of te peseted desig metod by te followig equatios, k = V o (V k ) V om (V k ), (27) σ 2 = i = (28) 2 i σ =, (29) wee is te umbe of te iput-output sigal level samples, ad V o (V k ) ad V om (V k ) ae te output level values o te ideal caacteistic ad te appoximatio oe, espectively. Table 3: Te mea eo(db) V T = 4(dB), p = 2 degee 6bits 24bits 32bits m = m = Table 2 sows te mea eo fo te implemetatio wit te polyomial expessios of degee tee

6 Poceedigs of te 7t WSEAS Iteatioal Cofeece o Sigal, Speec ad Image Pocessig, Beijig, Cia, Septembe 5-7, 27 3 &')( #$ *,+ "! #$% Figue 7: Te compessio caacteistics by VHDL simulatio. ad degee seve, espectively. Fo V T = 4dB ad p = 2, te mea eos fo 6-bit, 24-bit ad 32- bit compessios ave almost te same values. Howeve, we V T = 5dB, fo example, te lage wodlegt makes bette compessio caacteistics. 5 Coclusios A FPGA implemetatio metod of a dyamic age cotolle, compesso, as bee peseted, by usig a polyomial expessio. Tus, te powe tasfomatio fo gettig te compessio caacteistic is coveted ito te calculatios of additios ad multiplicatios, wic could be easily implemeted by aitmetic cicuits. To evaluate te pefomace of te peposed compesso, compessos wit 6-bit, 24-bit ad 32-bit wodlegts, espectively, ave bee desiged ad simulated by usig a adwae desciptio laguage, VHDL. Te desig ad simulatio esults sow tat te ideal iput-output caacteistic ca be acieved by usig a polyomial of degee tee o a ige degee. Te implemeted compesso may be itegated ito a audio system o a FPGA cip fo pactical use. Refeeces: [] L. B. Jackso: Digital Filte ad Sigal Pocessig. st ed.kluwe Academic Publises, Bosto(986). [2] SOCs Dive New Poduct Developmet, Compute, Vol.32(6), pp.6-66 (999). [3] J. Bowick, Studios ad Studio equipmet, J. Audio Eg. Soc., 25(/), pp (977). [4] A. Jeaya, H. Teue ad W. Wolf, Multipocesso systems-o-cips, Compute, Vol.38(7), pp.36-4 (25). [5] W. J. Kitze, J. W. Kema, W. F. Duyvestey, C. L. Kibbele ad A. T. va de Voot, Noisedepedet soud epoductio i a ca: Applicatio of a digital audio sigal pocesso, J. Audio Eg. Soc.,36(/2), pp.8-26 (988). [6] PLD Wold 25, Altea (25) [7] A. J. Oliveia, A feedfowad side-cai limite/compesso/de-esse wit impoved flexibility, J.Audio Eg.Soc., 37(4), pp (989). [8] S. Wei ad N. Seki, Desig of compesso/limite o a digital sigal pocesso, J.Acoust. Soc. Jp.(J), 5(4), pp (994). [9] J. Stoe ad R. Bulisc, Itoductio to Numeical Aalysis(3d Editio), Spige, 22. [] P. Eles, K. Kucciski ad Z. Peg, System Sytesis wit VHDL, Kluwe Academic Publises, 998.