Design of normalised and simplified FAs in quantum-dot cellular automata

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1 Design of normalised and simplified FAs in quantum-dot cellular automata Yongqiang Zhang, Guangjun Xie, Mengbo Sun, Hongjun Lv School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei , People s Republic of China lvhongjun1958@sina.com Published in The Journal of Engineering; Received on 18th July 2017; Accepted on 10th September 2017 Abstract: Quantum-dot cellular automata (QCA), which is a burgeoning technique at nanoscale region to take the important place of complementary metal oxide semiconductor technology, has been studied for several years. The recent primary research emphasis is mainly focusing on circuit design, for instance, full adders (FAs) and multiplexers. The authors will present a new five-input majority gate to construct FAs. Three QCA normalised FAs based on different logical expressions are then selected and designed, denoted as NFA1 NFA3, respectively. To conveniently compare with existing adders, three simplified FAs are also designed, named SFA1 SFA3. Analysis results indicate that SFA3 presents better performance in some extent. 1 Introduction Since the presence of quantum-dot cellular automata (QCA), the theory in this domain has been developed rapidly including the pure research and experimental verification for the practicability of this technology. In theoretical area, most studies focus on circuit design and simulation such as QCA basic logic unit and field programmable gate array, at which full adders (FAs) also dominate, while the physical realisation mostly focuses on the demonstration of QCA cells. The cell can be seen as a square charge container with two free electrons and four dots located at each corner as shown in Fig. 1a. Owing to the Coulomb interaction between electrons attaining lowest electrostatic potential, two polarisation patterns are used to encode binary information, logic 1 (P = + 1) and logic 0 (P = 1), as shown in Figs. 1b and c, respectively [1]. A method to get the optimal logical expression based on majority voter for a circuit with three inputs was presented [2]. Adopting this means, an FA consisting of three three-input majority voters and two inverters was obtained and also implemented in QCA domain in one layer. With this logical expression for FA, the threelayer FA was also designed [3, 4]. In addition, several FAs with different layouts have only been implemented with three-input majority voters and inverters [5 13]. With the varieties of logical expressions for FAs, the circuits can also be designed with other logic units, for instance, five-input majority voters [14 27], three-input exclusive-or (TIEO) gate [28] and exclusive OR gates [29]. Pudi optimised the logical expression to reduce one inverter and to design a new QCA FA [30]. The principle of these methods is to take the place of three-input majority voter in FAs. This paper is organised as follows: Section 2 provides the circuit design guidelines about QCA technology. The analytical methods are provided in Section 3. Section 4 illustrates the designed FAs and the simulation results. Finally, we conclude this paper in Section 5. 2 QCA circuit design guidelines 2.1 Majority voter The primitive device in QCA is three-input majority voter (denoted as M3) is shown in Fig. 2a. The functionality of majority voter is represented as Boolean function F = MV( A, B, C) = AB + AC + BC, which means that the output F of a majority voter is equal to the value of majority of the inputs A, B and C in Fig. 2b. Fig. 2c illustrates the simulation results of the voter with QCADesigner. The cell F will receive the signal from device cell at the centre of voter, which means that the input signals arriving device cell should keep synchronous, or one input signal will arrive at the device cell preferentially, resulting in erroneous output values. The five-input majority voter (denoted as M5) plays the same role, but with five inputs. The design principle is same as M Crossover With the electrostatic interaction between each pair of electrons within two cells, the QCA circuits can be integrated in one layer. These circuits can definitely be built by means of multilayered approach such as complementary metal oxide semiconductorbased integrated circuits, while this structure has not yet achieved and the noise problem exists [31, 32]. Up to now there are two kinds of techniques to implement one-layer crossover. Kim studied the robustness of simple wire crossover consisting of normal cells and rotated cells rotated by 45 [33]. The rotated cells, however, are more sensitive to noise casted by other cells than normal cells, easily leading to fault results [34]. Shin proposed a new wire-crossing using the relation between hold and relax phases of clocked cells [35]. If two adjacent cells are placed in clock0 and clock2, there does not exist Coulomb interaction between these cells, which means the signal cannot be propagated in these cells. That is the main principle of coplanar crossover with clocking mechanism. This crossover can also be realised by clock1 and clock3 pair. 2.3 Inverter Besides the majority voter, inverter is also a key element in circuit to realise the converse of input signal [1]. Fig. 3a illustrates a simple inverter. Input cell A and output cell F are placed in same clock zone. The output cell in this design, however, cannot be fully saturated due to the rapid decay of kink energy with distance between cells seen from its simulation results. By adding one more cell before output cell, the amplitude of polarisation can be strengthened as shown in Fig. 3b. 3 QCA circuit evaluation methods 3.1 Physical properties The apparent physical properties to evaluate a QCA circuit is nothing more than circuit area, cell count, latency, layer count and cell types. The area of a circuit is defined as the rectangular area occupied by circuit on the Cartesian plane [36]. This figure of merit directly reflects the circuit size that may relate to number

The second term P 2 gives the dissipated power (P diss ) that is exactly our concern.

2 where G is a real three-dimensional (3D) energy vector and l is the coherence vector. The first term P 1 in above equation represents the difference between power input (P in ) and power output (P out ). The second term P 2 gives the dissipated power (P diss ) that is exactly our concern. The worst case for power dissipation can be obtained during one clock cycle Tc=[ T D, T D ] E diss = h 2 TD T D G dl dt dt = h 2 ( ) TD [ G l] T D TD l dg dt T D dt (2) Fig. 1 QCA cell a QCA cell representing NULL b QCA cell representing logic 1 c QCA cell representing logic 0 It is worth noting that the greater the changing rate of G is, the larger amount the energy dissipates. ( ) Modelling ( ) the rate with δ function and representing G T D and G TD with G and G +. The upper bound power dissipation model in [37] is given as P diss = E diss, h G T c 2T + c [ G ( + tanh h G ) + + G ( h G )] (3) k B T tanh k B T G + G Fig. 2 QCA three-input majority gate a Diagram b QCA layout c Simulation results where T is the Kelvin temperature and k B is the Boltzmann constant. With the power dissipation for a QCA cell, we can calculate the total power dissipation for a system by accumulating the dissipated power of all cells because the presented method for each QCA cell is identical. Fig. 3 QCA inverters a Two cells positioned diagonally in one clock b Adding one more cell before output of cells about one-layer circuit, which also decides the manufacturing cost of a die. The latency or clock frequency often accounts for the performance for one system, which is decided by the longest path the signal propagated. In one QCA circuit, the latency relates to the number of majority voter that signal experienced from input cell to output cell. As mentioned earlier, the multi-layer crossover can hardly be approached by physical model. The rotated cells are easily affected by noise, leading to fault results, so that one-layer design and normal cells are the best choices. 3.3 Probabilistic transfer matrix As a method for computing the reliability of a combinational circuit, the probabilistic transfer matrix (PTM) forms an algebra to represent circuits with probabilistic failure gates. The matrix of a gate stems from its truth table, which is a 2 m 2 n matrix for a circuit with m inputs and n outputs as shown in Fig. 4a crossover and Fig. 4b fanout, respectively. To generate this PTM, the circuit calculated must be divided into subcircuits that do not have a series of components. There are three connecting modes for connection of two components: parallel, if two gates with PTM 1 and PTM 2 are connected in parallel, the combined PTM is the tensor product of PTM 1 and PTM 2 ; series, if two gates with PTM 1 and PTM 2 are connected in series, the combined PTM is the product of PTM 1 and PTM 2 ; if two gates with PTM 1 and PTM 2 are connected by fanout, the combined PTM is calculated by the tensor product of PTM 1 and PTM 2 and also eliminating the rows that have different input values for one fanout [38]. 3.2 Power dissipation To characterise the maximum power dissipation is meaningful by using sharp transitions in clocks. The equation for instantaneous total power for a single QCA cell is written as P = h dg 2 dt l + h 2 G dl dt = P 1 + P 2 (1) Fig. 4 PTM a Crossover b Fanout

then ( ) F = MA, ( B, C, D, E) = M A, B, C, C o, C o ( ) = M A, B, C, C o, C o (4) The new five-input majority gate is illustrated in Fig. 5, where C o undertakes two-fold weights.

3 4 QCA FAs 4.1 Five-input majority gate Primo, a new five-input majority gate should be designed to get an outstanding FA. The logic function for the majority gate is as (4), where A, B, C, D and E are inputs and F is output F = MA, ( B, C, D, E) = ABC + ABD + ABE + ACD + ACE + ADE + BCD + BCE + BDE + CDE If D = E = C o, then ( ) F = MA, ( B, C, D, E) = M A, B, C, C o, C o ( ) = M A, B, C, C o, C o (4) The new five-input majority gate is illustrated in Fig. 5, where C o undertakes two-fold weights. It has only nine cells and can be used in both multi-layer and coplanar circuits. 4.2 FAs design The logical function of FA can be described as (6), where A, B and C are input signals, C o is carried out and S is sum C 0 = AB + AC + BC S = ABC + ABC + ABC + ABC With M3, the sum formula is presented as (7) [2]. It is clear that this FA consists of three M3 and two inverters ( ( ) ) S = M MA, ( B, C), M A, B, C, C (7) (6) By the reformation of formula, another logical expression is presented as (8) [30]. Compared to (7), it is reduced by one inverter ( ( ) ) S = M MA, ( B, C), M MA, ( B, C), B, C, A (8) With one M5, the logical function of sum can also be described as (9) S = M ( MA, ( B, C), MA, ( B, C), A, B, C ) (9) Fig. 5 Proposed five-input majority gate Fig. 6 Schematics of QCA FAs a FA1 b FA2 c FA3 The schematics of FAs for (7) (9) are illustrated in Figs. 6a c, marked as FA1 FA3, respectively. It is worth noting that the input C should be placed to facilitate cascade of n FAs to implement n-bit carry flow adder (CFA). The corresponding QCA normalised FAs of these layouts are displayed in Figs. 7a c, shortened as NFA1 NFA3. Noting each majority voter, inverter and crossover with characters M3 or M5, I and C, respectively (similarly hereinafter). The spacing between two wires is two cells width and the cell count in one clock zone is two at least. It can be seen that the delay of sum S for NFA1 and NFA2 is 1.25 clocks, whereas the latency of NFA3 is 1 clock. Figs. 8a c show the 4 bit normalised CFAs implemented by cascading four corresponding FAs, denoted as NCFA NCFA3, respectively. It is clear that the additional clock zone in junction between two adjacent adders will ensure the correctness of transmission signal. To cater to the previous work of others, we also design the corresponding simplified FAs (SFA1 SFA3) and 4 bit CFAs Fig. 7 QCA normalised FAs a NFA1 b NFA2 c NFA3

Fig. 8 QCA 4 bit normalised CFAs a NCFA1 implemented with NFA1 b NCFA2 implemented with NFA2 c NCFA3 implemented with NFA3 Fig. 9 QCA simplified FAs a SFA1 b SFA2 c SFA3 Fig.

in Figs. 9 and 10, denoted as SFAs and SCFAs, respectively. The main differences from NFAs and SFAs are the spacing between two wires and the minimal cell count in each clock zone.

4 Fig. 8 QCA 4 bit normalised CFAs a NCFA1 implemented with NFA1 b NCFA2 implemented with NFA2 c NCFA3 implemented with NFA3 Fig. 9 QCA simplified FAs a SFA1 b SFA2 c SFA3 Fig. 10 QCA 4 bit simplified CFAs a SCFA1 implemented with SFA1 b SCFA2 implemented with SFA2 c SCFA3 implemented with SFA3 (SCFA1 SCFA3) that does not conform to aforementioned design guidelines as shown in Figs. 9 and 10, denoted as SFAs and SCFAs, respectively. The main differences from NFAs and SFAs are the spacing between two wires and the minimal cell count in each clock zone. In the wiring of 4 bit SCFAs, we employ the corner line to take the place of straight line to save the circuit area. 4.3 Simulation results To authenticate these devices and circuits designed in this paper, bistable approximation engine of QCADesigner version with the parameters summarised in Table 1 is employed to verify the functionalities of proposed circuits [31]. Fig. 11 illustrates the correct simulation results for the proposed five-input majority gate in Fig. 5, where C o undertakes two-fold weights. Fig. 12 shows the simulation results for NFA1 NFA3, respectively. Apparently, both two circuits perform correct Table 1 Bistable approximation parameters Parameter Value cell size 18.0 nm 18.0 nm dot diameter nm cell-to-cell spacing 2.0 nm number of samples 102,400 convergence tolerance radius of effect nm relative permittivity clock high J clock low J clock shift clock amplitude factor layer separation nm maximum iterations per sample 10,000

We add one more input/output pair with red colour for 4 bit NCFA2 and NCFA3 to indicate the less clock zone than NCFA1 by 0.75 clock zones. Fig.

5 Fig. 11 Simulation results for the proposed five-input majority gate functions. Fig. 13 displays the correct waveforms for proposed NCFA1 NCFA3, respectively, where each colour pair corresponds to one input/output pair. We add one more input/output pair with red colour for 4 bit NCFA2 and NCFA3 to indicate the less clock zone than NCFA1 by 0.75 clock zones. Fig. 14 depicts the simulation waveforms to test the correctness for SFA1 SFA3, which explains the rationality of SFAs. The waveforms of three corresponding SCFAs are shown in Fig. 15. The colour pair also corresponds to one input/output pair. 4.4 Performance comparison In Fig. 6, we displayed three QCA FAs with different logic units, FA1 FA3, corresponding to various Boolean logic expressions. PTM is used, as above mentioned, to analyse circuit reliability. The overall probability of failure for FAs is shown in Fig. 16a. It is clear that FA3 has better reliability than both FA1 and FA2. Fig. 16b illustrates the probability of failure for S, which show FA2 and FA3 have equal robustness for S. Since three carry outs are generated by a three-input majority voter, so the reliability for three C o s is equal as shown in Fig. 16c. With above analysis, it shows that the FA based on M5ismorerobustthanothertwoadders. Table 2 lists the physical properties for QCA FAs that are all coplanar structures, which exclude the adders that inputs or outputs are surrounded by the circuits. As noted before, adders NFA1 NFA3 conform to aforementioned guidelines to design circuits, resulting in more cells than SFA1 SFA3 that are proposed to get optimal FAs. The proposed SFA3 gets smaller area and less cells than all other adders, but has more latency than adder in [25] by 0.25 clocks and adder in [28] by 0.5 clocks. As displayed in Table 3, the comparisons of average energy, leakage energy, switching energy dissipations with previous works are shown by considering three different tunnelling energy levels (0.5E k, E k, 1.5E k ) at 2.0 K temperature, respectively. Figs illustrate considerable optimisation in three energy dissipations with bar graph according to achieved results. It can be seen that SFA3 leads to almost 46.4, 19.4, 34.6, 40.5, 60.5 and 69.1% improvements in average energy dissipation in Fig. 12 Simulation results for normalised Fas a NFA1 b NFA2 c NFA3 Fig. 13 Simulation results for 4 bit normalised CFAs a NCFA1 b NCFA2 c NCFA3

6 Fig. 14 Simulation results for simplified FAs a SFA1 b SFA2 c SFA3 Fig. 15 Simulation results for 4 bit normalised CFAs a NCFA1 b NCFA2 c NCFA Fig. 16 Probability of failure of outputs versus device probability of failure a Overall FA bs cc o

Table 2 Physical properties for FAs FAs Area, μm 2 Latency, clocks Cell count/type Minimal spacing, cells Minimal cell count in a clock [7] 0.0432 1 59/normal 1 1 [22] 0.0468 1 49/normal 0.5 1 [25] 0.

7 Table 2 Physical properties for FAs FAs Area, μm 2 Latency, clocks Cell count/type Minimal spacing, cells Minimal cell count in a clock [7] /normal 1 1 [22] /normal [25] /rotated 1 2 [27] /normal 1 2 [28] /rotated 1 2 [29] /rotated [13] /rotated 1 1 NFA /normal 2 2 NFA /normal 2 2 NFA /normal 2 2 SFA /normal 1 1 SFA /normal 1 1 SFA /normal 0 1 Table 3 Power dissipation for FAs FAs Average energy dissipation, mev Average leakage energy dissipation, mev Average switching energy dissipation, mev 0.5E k E k 1.5E k 0.5E k E k 1.5E k 0.5E k E k 1.5E k [7] [22] [25] [27] [28] [29] [13] NFA NFA NFA SFA SFA SFA Fig. 17 Average energy dissipation of FAs in various tunnelling energy levels Fig. 18 Average leakage energy dissipation of FAs in various tunnelling energy levels comparison with the circuits in listed references, respectively, at 0.5E k tunnelling energy level and at 2.0 K temperature. Fig. 20 shows the power dissipation maps of these FAs at 0.5E k tunnelling energy level and at 2.0 K temperature. In this figure, the darker the cells are, the more energy dissipates. Yet, there is no relevance to each FA in the cells colour. Table 4 summarises the physical properties for 4 bit QCA CFAs in terms of area, cell count and latency. The larger area and cell

Fig. 19 Average switching energy dissipation of FAs in various tunnelling energy levels Fig. 20 Power dissipation maps for FAs at 0.5Ek tunnelling energy level and 2.

2080 262 1.75 [25] 0.3000 295 1.50 [27] 0.4012 401 4.25 [29] 0.8442 527 4.00 [13] 0.3948 373 1.75 NCFA1 0.8732 465 4.25 NCFA2 0.6784 390 3.50 NCFA3 0.6360 364 3.25 SCFA1 0.3468 309 4.25 SCFA2 0.

8 Fig. 19 Average switching energy dissipation of FAs in various tunnelling energy levels Fig. 20 Power dissipation maps for FAs at 0.5Ek tunnelling energy level and 2.0 K temperature a g FAs in [7, 22, 25, 27 29, 13] h m Proposed NFA1, NFA2, NFA3, SFA1, SFA2, SFA3 Table 4 Physical properties for 4 bit CFAs CFAs Area, μm 2 Cell count Latency, clocks [7] [25] [27] [29] [13] NCFA NCFA NCFA SCFA SCFA SCFA count for NCFAs derive from straight input/output wires and also the minimal cell count in each clock, which can be seen from SCFAs designed with bent wires, resulting in smaller area. Although SCFA3 has a bit more latency, it gets smallest area and least cell count. 5 Conclusions Primo, in this paper, we detailed the circuit design guidelines by simulation and evaluation methods to restrict the building block for constructing a normalised circuit system. To explain how these guidelines and methods work, three normalised FAs named NFA1 NFA3 are designed, which are based on different logical expressions. Moreover, three corresponding simplified FAs, denoted as SFA1 SFA3, are also proposed and compared with NFAs and previous FAs. These FAs are then used to design 4 bit CFAs. Reliability analysis shows that FA3 with five-input majority gate has more robust structure than FA1 and FA2, with PTM. The analysis for FAs demonstrates that SFA3 reaches better properties than other FAs in some respects, i.e. reduced by 46.4, 19.4, 34.6, 40.5, 60.5 and 69.1% in average energy dissipation compared with schemes in references. The SCFA3 consisted of SFA3 which also ranks first in terms of area and cell count. 6 Acknowledgment This work was supported by the National Natural Science Foundation of China (no ). 7 References [1] Tougaw P.D., Lent C.S.: Logical devices implemented using quantum cellular automata, J. Appl. Phys., 1994, 75, (3), pp [2] Zhang R., Walus K., Wang W., ET AL.: A method of majority logic reduction for quantum cellular automata, IEEE Trans. Nanotechnol., 2004, 3, (4), pp [3] Cho H., Swartzlander E.E.Jr.: Adder designs and analyses for quantum-dot cellular automata, IEEE Trans. Nanotechnol., 2007, 6, (3), pp [4] Cho H., Swartzlander E.E.Jr.: Adder and multiplier design in quantum-dot cellular automata, IEEE Trans. Comput., 2009, 58, (6), pp [5] Hayati M., Rezaei A.: Design and optimization of full comparator based on quantum-dot cellular automata, ETRI J., 2012, 34, (2), pp [6] Ghosh B., Singh C., Salimath A.K.: A novel approach of full adder and arithmetic logic unit design in quantum dot cellular automata, J. Low Power Electron., 2013, 9, (4), pp [7] Abedi D., Jaberipur G., Sangsefidi M.: Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover, IEEE Trans. Nanotechnol., 2015, 14, (3), pp [8] Hayati M., Rezaei A.: Design of novel efficient adder and subtractor for quantum-dot cellular automata, Int. J. Circuit Theory Appl., 2015, 43, (10), pp [9] Liu W., Swartzlander E.E.: Design of 3-D quantum-dot cellular automata adders, IEICE Electron. Express, 2015, 12, (6), pp. 1 5 [10] Roohi A., DeMara R.F., Khoshavi N.: Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder, Microelectron. J., 2015, 46, (6), pp [11] Kumar D., Mitra D.: Design of a practical fault-tolerant adder in QCA, Microelectron. J., 2016, 53, pp

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Design of Optimized Quantum-dot Cellular Automata RS Flip Flops

Int. J. Nanosci. Nanotechnol., Vol. 13, No. 1, March. 2017, pp. 53-58 Design of Optimized Quantum-dot Cellular Automata RS Flip Flops A. Rezaei* 1 Electrical Engineering Department, Kermanshah University