Resistor-Logic Demultiplexers for Nanoelectronics Based on Constant-Weight Codes

Transcription

1 Resistor-Logic Demultiplexers for Nanoelectronics Base on Constant-Weight Coes Philip J. Kuekes, Warren Robinett, Ron M. Roth, Gaiel Seroussi, Gregory S. Snier, an R. Stanley Williams * Abstract The oltage margin of a resistor-logic emultiplexer can be improe significantly by basing its connection pattern on a constant-weight coe. Each istinct coe etermines a unique emultiplexer, an therefore a large family of circuits is efine. We consier using these emultiplexers for builing nano-scale crossbar memories, an etermine the oltage margin of the memory system base on a particular coe. We etermine a purely coe-theoretic criterion for selecting coes that will yiel memories with large oltage margins, which is to minimize the ratio of the imum to the minimum Hamming istance between istinct coewors. For the specific example of a crossbar, we iscuss what coes proie optimal performance for a memory. Inexing Terms emultiplexing, error correction coing, nanotechnology, resistie circuits, Hamming istance. * Manuscript receie Sept. 0, 005. This research was supporte in part by the Defense Aance Research Projects Agency. P. J. Kuekes is with Hewlett-Packar Laboratories, Palo Alto, California USA ( philip.kuekes@hp.com) W. Robinett is with Hewlett-Packar Laboratories, Palo Alto, California USA ( warren.robinett@hp.com) R. M. Roth is with the Computer Science Department, Technion, Haifa 3000, Israel. This work was one while isiting Hewlett-Packar Laboratories, Palo Alto, California 94304, USA ( ronny@cs.technion.ac.il) G. Seroussi is with the Mathematical Sciences Research Institute, Berkeley, CA 9470, USA. This work was one while the author was with Hewlett-Packar Laboratories, 50 Page Mill Roa, Palo Alto, CA 94304, USA. ( gaiel@msri.org) G. S. Snier is with Hewlett-Packar Laboratories, Palo Alto, California USA ( snier.greg@hp.com) R. S. Williams is with Hewlett-Packar Laboratories, Palo Alto, California USA (phone: ; fax: ; stan.williams@hp.com)

2 I. INTRODUCTION A nanoelectronic emultiplexer (emux) circuit [] can be lai out on a crossbar [] [3] using configurable resistors [4] or configurable ioes [] at the crosspoint junctions. In both cases, error-correcting coes can be use to improe the circuit performance. In comparison with ioe-base circuits, emux circuits base on resistors hae an inherent problem in achieing an aequate oltage margin to istinguish between their actiate an non-actiate output lines. On the other han, resistor-base emux circuits hae better efect-tolerance properties, in some respects, than ioe-base emuxes. This efect tolerance arises from the reunancy (reunant signal paths) introuce by the coing (not from "error correction" in the traitional sense, since there is in fact no ecoer in the circuit to perform correction). These efecttolerance properties of resistor-base emuxes are escribe elsewhere [5]; in this paper, we focus on an improe means of hanling the resistor-emux's primary problem: achieing an aequate oltage margin. Further motiation for choosing resistor-base emuxes is that nanoscale crossbars containing resistors (rather than ioes) are far more feasible to manufacture with current processes. In [6], it was shown that error-correcting coes of a certain type can be employe to construct resistor-base emuxes with superior analog circuit properties specifically, goo oltage margins. In this paper, we improe on the performance of the circuit construction in [6] by extening it to a broaer class of coes the constant-weight coes (also calle "N-hot coes" or "m-of-n coes"). Constant-weight coes hae been preiously presente in a nano-scale emux esign [7] (calle a "ecoer" in that paper), using a specific coe with weight w= an size M=6. In this paper, we expan the analysis of constant-weight coes. We (a) present the entire family of emux circuit esigns base on constant-weight coes; (b) present a quantitatie moel for the oltages occurring on each of the output lines of a resistor-logic emux base on an arbitrary constantweight coe; (c) analyze the use of these emuxes in a nano-scale crossbar memory to eelop a performance measure; an () characterize the best possible coes for -of-64 emuxes. We briefly reiew the terminology of coing theory [8][9] releant to this paper. The Hamming weight w = wt( b ) of a bitstring (or bit-ector or wor) b is the number of ones in the bitstring. For equal-length bitstrings, the operations b AND b an b XOR b are performe bit-wise, proucing bitstrings of the same length as the input bitstrings. The Hamming istance between two equal-length bitstrings b an b is = ist ( b, b ) = wt ( b XOR b ), which is the number of bit-positions in which the two bitstrings iffer. A binary coe of size M an length n is a set consisting of M length-n bitstrings (or coewors) that we use as nanowire aresses in our emux circuits. The minimum Hamming istance between any pair of istinct coewors is enote by min. Any coe may be escribe using these parameters as an (n,m, min ) coe. The imum Hamming istance between any pair of coewors is enote by. The imension of a coe is efine as log M. An important type of coe is the binary linear coe, which consists of a set of M = k length-n coewors that is close uner component-wise aition moulo, an thus forms a linear ector space oer the integers moulo. A binary linear coe is referre to as an [ n, k, min ] coe, or alternatiely as an ( n, k, min ) coe. Another important type of coe is the constant-weight coe, in which all coewors hae the same weight w; such a coe is escribe as an (n,m, min,w) coe. A subtype of the constant-weight coe is the balance

3 coe, in which each coewor is "balance" by haing an equal number of ones an zeroes, an which therefore has the property that w = n. II. DEMUX CIRCUIT The funamental esign pattern of these coe-base emuxes is that each coewor efines the connection pattern for one nanowire in the array of output lines. The coe has M coewors an the emux circuit has M output lines. Fig. shows the circuit iagram for an example emux base on a particular M=4 coe. Fig.. Demux circuit for a simple -of-4 emux base on a (6,4,4,3) coe. (a) The analog circuit realizing the emux, incluing the layout onto the crossbar. The thick ertical lines represent CMOS-scale wires (conentional wires), an the thin horizontal lines represent nanowires. The crossing nanowires an conentional wires constitute a mixe-scale crossbar, an resistors are shown at the configure junctions. (b) The igital circuit implemente by (a), with specific groups of wires ientifie as name signal ectors. The k= bit input aress is a. The output of the encoer is the n=6 bit coewor u. All the nanowire output lines of the emux collectiely form the M=4 bit output ector s. The encoer circuit an configuration pattern must match one another, since they are etermine by the same coe. The coe can be rea irectly from the configuration pattern of the crossbar, one coewor per output line in Fig., the coe use is {000, 000, 000, 000}, an each output line is labele with its encoe aress h. The encoing function E, implemente by the encoer circuit, must prouce coewors u matching those efine in the configuration pattern. Thus the specific configuration pattern shown for the crossbar in Fig. a implies a particular coe which must be use in the encoer. The esign pattern illustrate aboe may be state formally as follows. First, the length k of aress ector a must be a whole number of bits long, k = ceiling(log M ), () where ceiling (r) is the smallest integer i with i r. The encoing function E takes the length-k ector a as input, an prouces a length-n coewor u as output. u = E( a) () We enumerate the emux's output lines using a k-bit inex ector i (the unencoe aress of each output line) an we may then express the encoe aress h of each output line as h = E() i (3) k Since in general M, ali aresses a fall in the range [ 0, M ], with a interprete as a k- bit integer. Likewise, ali alues of i fall into the same range. We will assume the alues of a an i are ali in the rest of the paper. 3

4 For an arbitrary output line S i associate with coewor h = E(i), each bit of the n-bit ector h specifies whether a connection is configure at each of the n junctions where the n CMOS aress lines cross this particular nanowire (See Fig. a). A "" specifies a configure resistor at the junction, an a "0" specifies no connection. In Fig., for example, the top output line S00 has inex i=00 an encoe aress h=000. It is useful to label each nanowire output line with an encoe aress h, since the operation of the AND gate on an output line S i may be thought of as recognizing a particular encoe aress h = E(i) when it appears on the CMOS aress lines (as signal ector u = E(a) ). Output line S i thus turns on when it recognizes the conition h = u. This conition occurs if an only if i = a, showing that each input aress a causes exactly one output line (S a ) to turn on. A. Demux Output Voltages: Demux Base on General Coe We consier a single arbitrary emux output line, similar to those shown in Fig., in a emux base on an arbitrary coe. We assume that all the resistors in the crossbar are linear an hae the same resistance alues R. The current input aress signal a prouces an output ector u = E( a) from the encoer, which ries all the CMOS wires in the crossbar. Howeer, for a particular nanowire output line, not all of the junctions on that nanowire are configure, an so only a subset of these aress bits affects the output oltage of the nanowire. The oltage on an arbitrary output line may be calculate by counting up the number of ones (n ones ) an zeroes (n zeroes ) riing this output line's configure resistors, an analyzing the circuit as a oltage iier as shown in Fig.. Fig.. The oltage iier forme by the input signals on the configure resistors for a single arbitrary emux output line in a emux base on a (6,4,4,3) coe (Fig. ). The ones in h specify which resistors are connecte; this subset of the signals in u forms a oltage iier. Within that subset, the ratio of ones to total connections etermines the output oltage. The resistors connecte to the "logic " oltage form the upper parallel bunle, an the resistors connecte to "logic 0" form the lower parallel bunle. We assume normalize riing oltages in which a "zero" bit in the aress is at GROUND=0 V, an a "one" bit is at V DD = V, with the output oltage measure with respect to GROUND. The normalize output oltage of the oltage iier may be calculate as a ratio of the equialent resistance of the lower parallel bunle of resistors R lower to the total resistance of both parallel bunles R lower + Rupper. This simplifies to a ratio of the number of ones to the total number of connections (which is equal to the total number of ones an zeroes). R Rlower nzeroes nones = = = (4) R R R lower + Rupper + nones + nzeroes nzeroes nones We consier the output line S i labele by encoe aress h = E(i). The total number of configure resistors on this output line ( n + n ) is the number of ones in h, that is, wt (h). ones zeroes 4

5 Letting u E( a) = be the coewor riing the CMOS aress lines, the ones in u represents ones on the CMOS lines, an ones in h represent configure resistors. Therefore, the intersection u AND h gies the ones riing configure resistors. The number of ones among the configure connections of output line S i is therefore wt( u AND h) yiels h ( u AND h) wt( h) n ones =. Substituting into (4) wt = (5) This quantitatiely characterizes the normalize oltage h of all output lines of a emux base on an arbitrary coe (in particular, also a constant-weight coe), for any ali aresses a that may occur as input signals to the emux. By () an (3), u an h are coewors of the coe. Equation (5) is ali for any coe whatsoeer, an is not limite to constant-weight coes. B. Demux Output Voltages: Demux Base on Constant-Weight Coe We now erie a ersion of (5) specialize to constant-weight coes. We enote the complement of a coewor c by c. For any two coewors u an h of a constant-weight (n,m, min,w) coe, consiere together as shown in Fig. 3, we partition the -element columns into four subsets, base on the four possible alues of the corresponing bit-pairs; thus the weights of these subsets are w = wt( u AND ), w = wt( u AND ), w = wt( u AND ), an w = wt( u AND ). 00 h h 0 h 0 h Fig. 3. The relationship between istance an intersection of coewors of constantweight coes, using the (6,4,4,3) coe from Fig. as an example. Since we are concerne only with weights, we chose coewors h an u in which the columns corresponing to w 00, w 0, w 0, an w happene to form contiguous blocks, so that the with of the blocks graphically inicate the weights. (In general, the bits of these four groups woul be scattere throughout the coewors.) The same alues of h an u from Fig. are use here. Since this is a constant-weight coe, w = wt( h ) = w0 + w an w = wt( u ) = w0 + w, which implies w 0 = w0. The istance between u an h is thus = ist( u, h) = wt( u XOR h) = w0 + w0 (6) an so w 0 = w0 =. We enote the weight of the intersection as a = wt( u AND h) = w. Therefore, for constant-weight coes with weight w, an any pair of coewors u an h, it is always true that w = a +. (7) 5

6 The istance between coewors in a constant-weight coe is always een, an so is always an integer. For a constant-weight coe with weight w, we may combine (5), (6) an (7) to get a w h = = = with = ist( u,h). (8) w w w This characterizes the normalize oltage at any emux output line (labele with its encoe aress h), for any input signal (represente by the encoe input aress u), ali for a emux base on any constant-weight coe with weight w. The istance between coewors of a constant-weight coe must fall in the interal [ 0,w ], an therefore the normalize output oltage remains in the unit interal: [0,]. h We enote the istance profile of a coe (the istinct istances that occur between pairs of coewors, sorte into ascening orer) as integer ector, an the (normalize) istinct oltages that appear on the output lines of the emux as real ector. From (8) we get =, (9) w where enotes the all-one ector. in The normalize output oltage h in (8) assumes normalize riing oltages 0 = 0 (for logicin 0) an = (for logic-) on the CMOS aress lines. The emux circuit is assume to be compose entirely of linear resistors, an for arbitrary aress line oltages in in 0 an, the (non-normalize) output oltage is out in in in h = ( 0 ) h + 0. (0) Thus, for a emux base on a gien coe, there remain two egrees of freeom choosing the logic- an logic-0 oltages in in an 0. Since these riing oltages originate in the CMOS circuitry (see Fig. a), they can be freely specifie by the circuit esigner. Combining (9) an (0) gies out = in in in ( 0 ) + 0. () w This characterizes the istinct output oltages of the emux in terms of the weight w an istance profile of the coe, an the two riing oltages in in an 0 on the CMOS input lines to the out emux circuit. The set of istinct output oltages in inclues all the output oltages that out occur for any ali input aress ector a. As an example, Fig. 4 shows how,, an are relate in a emux constructe from a particular coe. Fig. 4. Distance istribution for an (,66,4,5) constant-weight coe. This shows the relatie number of coewor pairs with a gien istance between the coewors (ertical axis) s. the arious istances (horizontal axis). The istinct istances between coewors that actually occur efine the coe's istance profile = [ ]. This shows that the largest istance is =8. The minimum istance is min =4. This coe has weight w=5 an therefore imum possible istance w=0. The normalize ector 6

7 of istinct oltages (9) is thus = [ ]. From (9) an (), the out istinct oltages that occur on emux output lines are linearly relate both to an in in to. Supplying two arbitrary oltages 0 an as riing oltages linearly maps the out oltage pattern in the unit interal to the oltage pattern in the oltage interal in in, ]. [ 0 III. NANO-SCALE CROSSBAR MEMORY APPLICATION Our application is a pair of emux circuits that rie the rows an columns of a nano-scale crossbar memory array [6]. In this system, the two emuxes are implemente using mixe-scale crossbars (conentional wires cross nanowires) whereas the memory array itself is a pure nanoscale crossbar (Fig. 5a). The crosspoint junctions of the memory array are assume to be hysteretic resistors [0], which can be ynamically reconfigure by applying certain oltage rops across them. The iea is to realize a memory system by storing bits in the iniiual junctions of the memory array, with the conention that high resistance represents a zero, an low resistance represents a one. The emuxes are configure once, at manufacturing time, an are assume to be stable thereafter; their function is to get the proper oltages to the junctions of interest in the memory array. To make such a system work, we must be able, for an arbitrary junction in the memory array, to (a) write a one or (b) write a zero or (c) rea the current state of the bit. The behaior of a hysteretic resistor, which is a two-terminal eice, is that it is controlle by the oltage rop that is put across it [0]. Putting large-magnitue oltage rops (either positie or negatie) across the eice will estroy it; putting a moerate-magnitue oltage rop across it will write either a one or a zero, epening on the polarity; an putting a low-magnitue oltage rop across it will not change its resistance. Specific oltage threshols for recentlymanufacture eices are gien in [0] ; howeer, these alues ary as the manufacturing process changes. Because of the nature of the hysteretic resistors, the circuits use to perform READ an WRITE operations hae quite ifferent requirements. They must both access the memory array through the row an column emux circuits, but otherwise may be completely inepenent CMOS circuits, that are alternately enable, epening on whether reaing or writing is currently occurring. In this paper, we focus on the WRITE operation, in which the primary problem is to elier to the selecte junction a oltage rop which is reliably aboe the write-threshol oltage, an below the estruction oltage (while guaranteeing that all the non-selecte junction oltage rops are well below the write threshol). Briefly, the main problem face by the READ circuit is one of iscrimination. It makes sense to use lower-magnitue oltages in reaing to make sure that acciental writes o not occur. With a low-magnitue oltage rop across the a hysteretic resistor, it will act as a normal resistor an its resistance can be measure to rea the state of the bit store in it. The problem is to esign a circuit that can iscriminate the resistance of the aresse junction from the other M junctions in the memory array. Designing an 7

8 effectie READ circuit therefore requires entirely ifferent techniques than those neee for esigning a WRITE circuit, an READ circuit issues are not consiere further in this paper. In orer to analyze the oltages that can be applie to memory junctions by emuxes riing the rows an columns of a crossbar, we make some assumptions: the resistance of the nanowires an conentional wires composing the system are negligible compare with the resistances of the configure junctions, an that the nonconfigure junctions are effectiely open circuits. the loaing of the emuxes by the memory array is negligible, so that the oltages that appear on the emuxes in isolation are ery close to the oltages that actually appear when riing the memory array. the CMOS riing circuits can be treate as ieal oltage sources, which o not sag with increasing loa. This enables the oltage-iier circuit moel expresse in (8), in which the oltage on each output line can be calculate inepenently of all other output lines. Gien these assumptions, the oltage rop across a junction in the memory array is simply the ifference between the oltages on the two crossing wires (see Fig. 5a), junc = row col. () By our assumptions, the oltages on each row or column wire are constant across the entire memory array, an thus the wires coney the emux output oltages (8), without istortion, to either sie of the junctions. Fig. 5. (a) The circuit geometry of a nano-scale crossbar memory system. The row emux actiates the selecte row, an the column emux actiates the selecte column, which intersect at the selecte junction. Howeer, eery emux output line has an output oltage, an so each junction (where a row an column cross) has a oltage rop etermine by the oltages on these two crossing wires. (b) Voltage-rop iagram showing the istinct oltages appearing on row wires (left) an column wires (right). The ertical imension represents absolute oltage. The fille circles represent the selecte line oltages, an the hollow circles non-selecte line oltages (See Fig. 4 for an example of the istinct oltages appearing on the output lines of a single emux circuit.). The otte lines linking a row oltage to a column oltage represent istinct oltage rops that can occur (across junctions in the memory array), with ertical istance representing the magnitue of the oltage rop. The polarity of each oltage rop is shown by whether the row oltage is aboe or below the column oltage. This iagram shows the magnitue of all the istinct oltage rops that can occur across junctions in the memory array. (c) The splay s an offset oltage t between the row oltages an column oltages. These ariables use the normalization (4) in which the output-oltage range of each emux has unit with (labele ""). This shows how the istribution of istinct emux output oltages an the oltage offset t between the two emuxes interact to etermine the oltage rops that occur. We write one bit at a time in the memory by using the two emuxes to actiate a selecte row an a selecte column, which cross at a specifie junction. The aress input signals to the row emux an column emux etermine which output line is selecte, for each of the two emuxes. Howeer, all the non-selecte junctions are still actie, an coul be accientally written to or out row out col 8

9 estroye if oer-threshol oltage rops happen to be unintentionally applie to them. Thus our goal is to set up the emux riing circuits an oltages such that we elier the intene oltage rop to the selecte junction, an elier oltage rops as small as possible to all the other nonselecte junctions in the memory array. Design Goal: We wish to minimize the ratio q, q = { } non _ selecte selecte, (3a) of the largest magnitue of the oltage rops eliere to any non-selecte junction with respect to the magnitue of the oltage rop eliere to the selecte junction. It is natural to efine the normalize oltage margin m as m = q, (3b) since this is the (normalize) ifference between the oltage rop we wish to elier to the selecte junction, an the worst-case oltage rop incientally eliere to a non-selecte junction. Two ersions of () are require for the row an column emuxes, with two separate pairs of riing oltages, proucing one set of oltages riing the rows, an another set of oltages out col riing the columns. We use () to combine these absolute oltages to obtain a matrix specifying all oltage rops that can occur in the memory array. We use a graphical technique (Fig. 5b) to isualize the istinct oltage rops that occur. We must first choose the four riing oltages for the row an column emuxes (logic- an logic-0 oltages for the row emux, an logic- an logic-0 oltages for the column emux). To keep things simple, it was aluable to use the igital circuit abstraction as much as possible, an to iscuss the resistor-logic emux circuit as a emultiplexer (a bona fie igital circuit); that is why we use the names "logic-" an "logic-0" for the two oltages riing the emux input lines. Howeer, at this point, as we combine the outputs of two resistor-logic emux circuits, we leae the igital abstraction. The four oltages are no longer consiere to be igital signals, but are four inepenently-ajustable oltages, which we nee to control in orer to elier the esire oltage rops to certain junctions in the memory array. For simplicity, we assume that the row an column emuxes are ientical (same coe, same number of output an input lines, same encoer circuitry). This restriction is not necessary, since, for example, there may be a reason to implement a rectangular rather than a square crossbar memory. There are only three egrees of freeom, since aing a constant to all four oltages has no effect on the circuit behaior. We can arbitrarily choose one of these oltages to be GROUND. Because the hysteretic resistors hae fixe oltage-rop threshols goerning their behaior, the oltage ifference between "logic-" an "logic-0" for both emuxes is constraine; this consumes two more egrees of freeom. One egree of freeom remains: the oltage offset between the row oltages an the column oltages. The situation is iagramme in Fig. 5c. out row 9

10 In Fig. 5c, the output oltages of both emuxes are normalize to the output oltage range. This is a ifferent normalization than the one use earlier. It is a coe-epenent normalization, which employs knowlege of the coe parameter to scale the emux's two riing oltages in = an (4a) w in =, (4b) 0 such that the imum an minimum oltages that occur on the output lines completely fill the unit interal. This can be erifie by calculating an w for a particular coe, extracting out from, an substituting (4a) an (4b) into (), yieling =. The output line oltages corresponing to the istances 0, min an containe in are, respectiely, the oltage on the selecte line ( ON ), the highest oltage on a non-selecte line ( OFF ), an the min ). lowest oltage on a non-selecte line ( OFF 0 ON = =. (4c) min OFF =. (4) OFF min = = 0. (4e) in in 0 OFF OFF > min, as the names suggest. Howeer, if in in 0 When >, then <, then the oltages are flippe in polarity. In Fig. 5, the column oltages are flippe in this way. This is necessary to get the imum oltage rop across the selecte junction. Our goal is to imize the ariable t in Fig. 5c, which represents the normalize offset oltage between the row an column oltages. The ariable s in Fig. 5c represents the splay (how sprea out the non-selecte output oltages of a emux are specifically, the relatie with of the oltage range occupie by the non-selecte output lines); the splay s is etermine by the choice of coe, an can be calculate as OFF OFF min min s = = = where q ON OFF =. (5) q min The iagram of Fig. 5c proies a isual metaphor. To consier arious oltage offsets t between the row an column oltages, we imagine that there are two soli structures holing the row an column oltages, which may be sli up an own ertically with respect to one another, while the otte lines (representing oltage rops) are rubber bans that stretch. We slie the two structures back an forth until we hae foun an offset t where the ratio q (3a) is at a minimum. Excluing the selecte-junction oltage rop in orer to focus on non-selecte junctions, we consier the two largest-magnitue oltage rops of each polarity. The otte line between the lowest row oltage (lowest hollow circle on the left) an the highest column oltage (highest hollow circle on the right) represents the imum-magnitue oltage rop with min 0

11 negatie polarity (using the polarity conention of ()). As shown in Fig. 5c, this oltage rop has magnitue t. For the positie polarity, since the selecte-junction oltage rop is exclue, we must choose either the oltage rop between the highest row oltage an the secon-lowest column oltage, or between the lowest column oltage an the secon-highest row oltage. But by the symmetry of the system, these two oltage rops are equal. We arbitrarily choose the latter, which is shown in Fig. 5c as the otte line between the highest hollow circle on the left, an the bottom fille circle on the right. The magnitue of this oltage rop is t + s. The quantity ( t, t + s) is equal to the numerator of (3a). The enominator of (3a) represents the magnitue of the oltage rop across the selecte junction, which can be ( ) seen in Fig. 5c to be + t. We wish to minimize q t, t + s t t + s = = + t + t,. This + t mimimum occurs when t t + s =. (6a) + t + t Fig. 6 shows why the minimum of q occurs when these two expressions are equal, an that the imum of the oltage margin = q also occurs at the same alue of t. m t t + s Fig. 6. Plot of,, + t + t q t t + s = + t, an m = q s. oltage offset t for + t the (,66,4,5) example coe, which has s =. The minimum of q an imum of the oltage margin m occur when t =. 4 We can sole (6a) for t, the optimal oltage offset between emuxes. s t = (6b) In the normalization (4) of Fig. 5c, the oltage rop across the selecte junction is + t an the worst-case oltage rop across a non-selecte junction is t. Hence, from (5) an (6b), t q q = =. (7a) + t q + The circuit's normalize oltage margin is therefore t m = q = =. (7b) + t q + The alues of s an q are etermine by the coe use. Since the function at the right-han sie of (7b) is monotonically ecreasing in q, minimizing q minimizes the quantity q, an imizes the circuit's oltage margin m. Three ifferent normalizations hae been use in the preceing analysis: (a) normalize input oltages were use to analyze an iniiual emux circuit (4)(5)(8)(9); (b) for a emux base on a specific coe, knowlege of the coe parameter was use to normalize the emux's output

12 oltage range (4) (the parameters s an t use this normalization in Fig. 5c); an (c) the oltage rop across the selecte junction is the normalization unit for both q an m (7). This last normalization is epenent on both an the optimal oltage offset t. These three normalizations were inconenient for analyzing the memory circuit; to apply them to a real circuit, a final oltage scaling is neee to make the eliere oltage rop at the selecte junction match the write threshols of the hysteretic resistors in the junctions. To achiee our esign goal of imizing m, we must minimize q = in (7b), which is min a purely coe-theoretic quantity. This gies us a simple criterion for ealuating coes for this crossbar memory application. Coe selection criterion for the memory application: minimize q =. (8) min Coes that hae low alues of q will prouce memory systems with low alues of q, which will hae higher oltage margins m than a coe with a higher q. For a gien memory size (or coe size) M, ery low q can be achiee if the coe length n is allowe to grow without limit. Howeer, increasing n incurs a cost in chip area. Therefore there is a trae-off between q an n, or, in other wors, gien a specification for the coe size M an the oltage margin m, we shall seek the shortest possible coe satisfying the specification. A. Example of Constant-Weight Coe Demuxes Use in a Memory System We will use an (,64,4,5) coe (also referre to in Figures 4, 5 an 6) to illustrate the use of constant-weight coes for constructing emux circuits for memory systems. This coe has n= an yiels a memory system with a = 0. 4 (oltage margin of 40%). m Fig. 7 shows the oltage rop iagram for a memory system base on (,64,4,5) emuxes, with the eliere oltage rop to the selecte junction scale to.5 V. We will here assume the threshol oltages of estruction = ± 4 V an write = ± V. Thus.5 V excees the writethreshol oltage, but is below the estruction threshol oltage. Fig. 7. The four scale riing oltages for a nano-scale crossbar memory system base on a (,64,4,5) constant-weight coe. The ertical istances show the oltage rops that can occur at arious junctions in the memory array. The 40% oltage margin of this system is a.0 V ifference between the.5 V eliere to the selecte junction, ersus the worst-case.5 V eliere to any other junction. This margin is allocate in this example so that we excee the.0 V write threshol by 0.5 V for the selecte junction, an the selecte junction is.5 V below the estruction threshol of 4.0 V. For all the non-selecte junctions, the worst-case eliere oltage rop is.5 V, which is 0.5 V below the write threshol.

13 The three ifferent normalizations use in the analysis can be seen in Fig. 7. The input oltage range for each emux is.5 V. The range of output oltages for each emux is.0 V. The alue of t = is calculate as the optimal normalize oltage offset for this coe, which is thus an 4 offset of 0.5 V. The oltage rop eliere to the selecte junction is.5 V. In this example, there are only two istinct oltages among the four riing oltages, but in general the four oltages may be istinct. IV. WHAT ARE THE BEST CONSTANT-WEIGHT CODES FOR MEMORIES? For the nano-scale crossbar memory application, in the foreseeable future, practical circuit issues limit the size M of the emuxes we might buil to the range 64 M 04, where M is not require to be a power of. As an example, we will choose a specific coe size M=64. Coes of this size etermine -of-64 emux circuits, which coul be use to make memory systems. With the number of output lines M hel constant, an the number of CMOS aress lines n allowe to ary, we ask: what are the best constant-weight coes (we can fin) for each alue of n? The area of the mixe-scale crossbar implementing an (n,m, min,w) emux is proportional to nm, so coes with low n are esirable to minimize chip area requirements. In contrast to the usual situation in coing theory, we are not concerne with getting high alues of min rather it is the relationship between min an that is of interest. In particular, we esire low alues of q =, or equialently, that min an are "near" one another. min In [], for M=64 constant-weight coes, some lower bouns for q were establishe for certain ranges of n. Some specific coes were also gien, for which the q -alues equal the lower bouns. These are the coes in Table I; the actual coes are explicitly escribe in the appenix. For coes shown in the table with M > 64, some coewors can be eliminate to reuce the coe size to M = 64 without changing the coe's parameter q =. The coes in all rows of min the table are optimal in n an q. For example, we consier the (5,70,6,6) coe in row 4 of Table I. For M=64 constant-weight coes with n [5,8], the lowest possible q alue for any such coe is q = 5, which is realize by this coe. Furthermore, it is an n=5 coe, on the 3 bottom en of the [5,8] range for n for this alue of q. This coe is optimal because the lower boun shows that (a) it is impossible to fin some other n=5 coe with a lower alue of q, an (b) there are no shorter coes with an equal or smaller q. Table I. Table of lower bouns on q for M=64 constant-weight coes, an coes at these bouns. 3

14 Range of Lower Known M=64 Constant-Weight Coes with low q n Boun Coe min q n q m for q 8 4 (8,70,,4) [9,0] 3 (9,84,,3) [,4] (,66,4,5) = [5,8] [9,3] 5 3 (5,70,6,6) (9,70,8,9) = Preiously, a constant-weight coe was foun through a brute-force search among (constraine) coes []. This (,64, 8, 6) coe with = has parameters n= an q = 3 ; the n=9 coe of row 5 of Table I is more efficient (shorter) than this coe. Constant-weight coes appropriate for other emultiplexer sizes (e.g., M = 8 or 56) can be obtaine similarly to those presente aboe for M = 64. The starting point is usually a goo constant-weight coe in the conentional sense of coing theory (e.g., with a large alue of M for gien n an min ), to which coing-theoretic operations of expurgation, shortening, an augmentation [7] are applie to optimize the coe for our requirements (i.e., a low q ratio). The mathematical tools from [0] still proie lower bouns on the best achieable alue of q gien M an n. Howeer, as the coe size increases, there might be gaps between the best parameters achiee by the constructions, an the bouns of [0], which might leae the question of coe optimality open. Neertheless, from a practical point of iew, the coes obtaine still proie excellent performance for the application at han. In [6], we presente a emux circuit construction that utilize complementary repeate coes base on linear coes. They are constructe (see Eq. 8 of [6]) by taking a starting linear coe an to each coewor appening its complement; which was calle "balancing" in [6]. When starting from an ( n, k, ) linear coe, this operation prouces an ( n, k,, n) constant-weight coe. These are balance coes, since they hae equal numbers of ones an zeroes in each coewor. They are therefore a specialize subclass of the constant-weight coes. Howeer, they cannot be efficient in terms of length n, because of the oubling of length inherent in their construction, an general constant-weight coes will be shorter. For example, the (,66,4,5) coe from Row 3 of Table I is optimal with n= an = m. A irectly comparable coe 5 from [6] is a (,64,8,) complementary repeate coe, which has the same oltage margin = m, but with n= it is twice as long as the optimal coe. 5 V. ENCODER AREA 4

15 The complexity of the encoer circuit for a general constant-weight coe may be greater than that of a complementary repeate coe, resulting in a cost of increase chip area. Howeer, there are seeral reasons why this may be irreleant for coe-base emux circuits. (a) A large number of memory arrays may be serice by a single encoer, so that the encoer cost is amortize oer many memory blocks []. (b) Een without amortization, the goo coes escribe for this application are often constructe by starting from a goo linear coe (e.g., the Golay coe [8]) an moifying it. Thus, the structure of the original linear coe can still be exploite to esign encoers that are significantly simpler than a full lookup table. (c) The area of the possibly larger encoer is counterbalance by the reuce area of the emux's mixe-scale crossbar (half the area, in the aboe example of the n= s. n= coes). Therefore, a larger encoer area is not likely to be a significant isaantage when using constant-weight coes in esigning emux circuits for the nano-scale memory application. VI. CONCLUSIONS We analyze emuxes base on general constant-weight coes an the entire memory circuit controlle by them. We were able to set lower bouns on the shortest coes (smallest emuxes) that coul proie a particular oltage margin in a memory, an then we ientifie coes that satisfie these bouns for the case of a crossbar. We mae a number of simplifying assumptions in orer to obtain a quantitatie criterion (8) for ealuating the efficiency of the coes: The resistors in the crossbar are linear. The configure resistors in the crossbar all hae the same alue of resistance. The non-configure resistors in the crossbar are open (infinite resistance). The conentional wires an nanowires of the crossbar hae negligible resistance. The CMOS oltage sources riing the emuxes o not sag uner loa. The loaing by the memory array has a negligible effect on the emux output oltages. Two ientical emuxes are use to rie the rows an columns. The hysteretic resistors in the crossbar all hae ientical write-threshols an estruction threshols, an the magnitues of these threshols are equal for both polarities. Although not all of these assumptions will hol for real nano-scale crossbar memories, the constant-weight coes efine by the criterion of (8) will still be preferable in most such systems because the shorter coes will still be more efficient for memories in which the analog circuit properties eiate from our assumptions. We hae therefore isentangle the issue of choosing a coe from the complicate analog circuit issues that arise in esigning a resistorbase emux. ACKNOWLEDGMENT We gratefully acknowlege J. Straznicky for aluable iscussions, an the Defense Aance Research Projects Agency (DARPA) of the Unite States for partial support. 5

16 APPENDIX: EXPLICIT DESCRIPTION OF THE CODES IN TABLE I Coe : (8, 70,, 4), =8. All binary wors of length 8 an Hamming weight 4. Coe : (9, 84,, 3), =6. All binary wors of length 9 an Hamming weight 3. Coe 3: (, 66, 4, 5), =8. Constructe from the Steiner system S(4,5,) [7, p. 70]. {000000, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , } Coe 4: (5, 70, 6, 6), =0. Coewors of Hamming weight 6 in the (5, 8, 6) shortene Norstrom-Robinson coe [7, p. 74]. { , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , } Coe 5: (9, 70, 8, 9), =. Constructe by shortening, expurgating, an augmenting [7, Ch. ] the subset of coewors of Hamming weight in the extene binary Golay coe [7, p. 64]. { , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , } 6

17 REFERENCES [] P. J. Kuekes, W. Robinett, G. Seroussi an R. S. Williams, "Defect-tolerant interconnect to nanoelectronic circuits: internally-reunant emultiplexers base on error-correcting coes," Nanotechnology, 6, 869, 005. [] A. DeHon, "Array-base architecture for FET-base, nanoscale electronics," IEEE Transactions on Nanotechnology, ol., pp. 3-3, 003 [3] G. Snier, P. J. Kuekes, T. Hogg an R. S. Williams, "Nanoelectronic architectures," Appl Phys A, 80, [4] P. J. Kuekes, R. S. Williams, an J. R. Heath "Molecular wire crossbar memory," US Patent #6,8,4, Oct. 3, 000. [5] P. J. Kuekes, W. Robinett, an R. Stanley. Williams, "Defect tolerance in resistor-logic emultiplexers for nanoelectronics," IEEE Tr. Nanotechnology, submitte for publication, 005. [6] P. J. Kuekes, W. Robinett, an R. Stanley. Williams, "Improe oltage margins using linear error-correcting coes in resistor-logic emultiplexers for nanoelectronics," Nanotechnology, 6, 49-3, 005. [7] Z. Zhong, D. Wang, Y. Cui, M. W. Bockrath an C. M. Lieber, "Nanowire crossbar arrays as aress ecoers for integrate nanosystems," Science, ol. 30, pp , 003 [8] F. J. MacWilliams an N. J. A. Sloane The Theory of Error-Correcting Coes, (North- Hollan, New York), 990. [9] S. B. Wicker, Error Control Systems for Digital Communication an Storage (Prentice Hall, Upper Sale Rier), 995. [0] G. Snier, "Computing with hysteretic resistor crossbars," Appl Phys A, 80, 65, 005. [] Ron M. Roth an Gaiel Seroussi, "On the secon moment of the istance istribution of binary coes," Proc. IEEE International Symposium on Information Theory, Aelaie, Australia, September 005, pp [] Greg S. Snier an Warren Robinett, "Crossbar emultiplexers for nanoelectronics base on n-hot coes," IEEE Tr. Nanotechnology, ol. 4, no., March

18 Fig. a. a CMOS circuitry A0 A Encoer S00 S0 S0 S u encoe aress h nano-circuitry: mixe-scale crossbar 8

19 Fig. b. b A0 A a encoe aress h Encoer S00 S0 S0 S s u 9

20 Fig.. connections h=0 00 u=0 00 n ones nzeroes n upper bunle: = n ones resistor lower bunle: zeroes = resistors V DD = = n ones nones + n GROUND=0 zeroes = + 0

21 Fig. 3. w w h w = a + u w 00 w 0 = w 0 = w = a

22 Fig. 4 a Coewor Pairs (,66,4,5) coe 0 selecte line Hamming istance =0 =4 =6 =8 min non-selecte lines w in in 0

23 Fig. 5a. a selecte row memory array selecte junction selecte column k-bit aress row selector (emux) k-bit aress column selector (emux) 3

24 Fig. 5b. b oltage rows columns selecte junction non-selecte junctions selecte-line oltage non-selecte-line oltage 4

25 Fig. 5c. c oltage rows columns t s t 5

26 Fig. 6. t = 4 q s + t + t m + t t t 6

27 Fig V.5 V 0 V 0 V selecte junction oltage rop (.5 V) non-selecte junctions oltage rop (.5 V) 7