Basics of Digital Logic

Transcription

1 ECE-78: Computer Hrdre Design Winter 7 Bsics o Digitl Logic BOOLEAN ALGEBRA AND LOGIC GATES This is the oundtion or design nd nlsis o digitl sstems. It dels ith the cse here vriles ssume onl one o to vlues: TRUE (usull represented the smol ''), nd ALSE (usull represented the smol ''). BASIC OPERATIONS X nd Y: Boolen vriles. Boolen vriles re used to represent the inputs or outputs o digitl circuit. These three re the sic logicl opertions. All the other opertions re derived rom these three. OPERATION BOOLEAN EXPRESSION OPERATION NOT X ( or X ) Logicl negtion AND X. Y Logicl conjunction o to sttements OR X + Y Logicl disjunction o to sttements TRUTH TABLES AND LOGIC GATES Truth Tle: A tulr listing o unction vlues or ll possile comintions o vlues on its input rguments. I there re n inputs, there re n possile comintions. Logic Gtes: Hrdre components tht produce logic or logic depending on the stte o inputs. Boolen unctions cn e implemented ith logic gtes. NOT gte: X = X' X = X' -input AND gte: X Y = X.Y X Y = X.Y -input OR gte: X Y = X+Y X Y = X+Y Logic Gtes (AND, OR, etc.) cn hve multiple inputs: X X Y Z = X.Y.Z Y Z = X+Y+Z+ AXIOMS THEOREMS. =. =. =. = = += + = + = + = = Vrile dominnt rule X. = X X + = X Commuttive rule X. Y = Y. X X + Y = Y + X Complement rule X. X = X + X = Idempotenc X. X = X X + X = X Identit Element X. = X + = Doule negtion X = X Associtive rule X. (Y. Z) = (X. Y). Z X + (Y + Z) = (X + Y) + Z Distriutive rule X. (Y + Z) = X. Y + X. Z X + Y. Z = (X + Y). (X + Z) Instructor: Dniel Llmocc

2 ECE-78: Computer Hrdre Design Winter 7 Other Theorems Asorption Adjcenc Consensus DeMorgn Simpliiction X. (X + Y) = X. X + X. Y = X + X. Y = X. ( + Y) = X X + X. Y = X. ( + Y) = X X. Y + X. Y = X (X + Y)(X + Y ) = X X. Y + X Z + YZ = XY + X Z (X + Y)(X + Z)(Y + Z) = (X + Y)(X + Z) Corollr: (X + Y)(X + Z) = X Y + XZ X. Y = X + Y, X. Y. Z = X + Y + Z + X + Y = X. Y, X + Y + Z+... = X. Y. Z X. (X + Y) = X. Y X + X Y = X + Y A useul ppliction o the theorems is on the simpliiction o Boolen unctions hich leds to the reduction o the mount o logic gtes. or emple: = (A + B C + D + E)(A + B C + D ) + E = (X + Y)(X + Y ), X = A + B C, Y = D + E = (X + Y)(X + Y ) = X = A + B C = (X + Y)(X + Y ) X = XX + XY + YX + YY Y = X + X(Y + Y) = X + X = X = (X )Z + Y + XY Z = X Y Z + XY Z = Y Z(X + X ) = Y Z = Y + Z X = + + = + ( + ) = + = + = ( + )( + ) = + = A(B + C ) + A = A(B. + C ) A = (A + B ). + C A = (B ). + C A = AB C DERIVING BOOLEAN UNCTIONS ROM TRUTH TABLES: Using s: A B C A B C = A BC + AB C + ABC Using s: A B C A B C = (A + B + C)(A + B + C ) Instructor: Dniel Llmocc

3 ECE-78: Computer Hrdre Design Winter 7 Other Logic Gtes -input NAND gte A B -input NOR gte A B -input XOR gte A B X Y X Y = X Y + XY = XY -input XNOR gte: A B X Y X Y = XY + X Y = XY SUM O PRODUCTS (SOP) AND PRODUCT O SUMS (POS) USING MINTERMS AND MAXTERMS: MINTERMS nd MAXTERMS ( vrile unction) Minterms Mterms m = M = + + m = M = + + m = M = + + m = M = m 4 = M 4 = m 5 = M 5 = + + m = M = m 7 = M 7 = + + or unction ith n vriles, there re n minterms (or n mterms) rom m to m n (or rom M to M n ) Note tht: m i = M i. A unction cn e epressed s sum o minterms or s product o mterms: A minterm cn e or. When the minterm is, the minterm is term o the unction. A mterm cn e or. When the mterm is, the mterm is term o the unction. Cnonicl orms: Sum o products (SOP) tht includes onl minterms or Product o sums (POS) contining onl mterms. Non-cnonicl orms: SOP tht includes terms tht re not minterms (or POS tht includes terms tht re not mterms). or emple: (,, ) = + (,, ) = ( + + )( + ) (,, ) = ( + + ) Instructor: Dniel Llmocc

4 ECE-78: Computer Hrdre Design Winter 7 Emple: X Y Z Sum o Products = X Y Z + XY Z + XY Z + XYZ (X, Y, Z) = (m, m 4, m 5, m ). (X, Y, Z) = m(,4,5,) Also: (X, Y, Z) = m(,,,7) Product o Sums = (X + Y + Z)(X + Y + Z)(X + Y + Z )(X + Y + Z ) (X, Y, Z) = (M, M, M, M 7 ). (X, Y, Z) = M(,,,7) Also: (X, Y, Z) = M(,4,5,) Note: (X, Y, Z) = m(,4,5,) = M(,,,7). TIMING DIAGRAMS A A B G B C C G PRACTICE EXERCISES Simpli the olloing unctions: = X Y Z + XY Z + XY Z + XYZ (X, Y, Z) = (m, m, m ) (X, Y, Z) = (M, M 4, M 7 ) = (X + Y + Z)(X + Y + Z ) = (A B + C + D)(A B + D) = A(C + D B) + A Provide the Boolen unctions nd sketch the logic circuit. Use the to representtions: i) Sum o Products, ii) Product o Sums. Also, provide the minterms nd mterms representtions. A B C Otin the logic unction (nd minimie i possile) o the olloing circuits: C C B Y B Y A A Dr the timing digrm o the olloing circuit: 4 Instructor: Dniel Llmocc

5 ECE-78: Computer Hrdre Design Winter 7 Design circuit tht veriies the logicl opertion o the OR gte. = '' (LED ON) i the OR gte orks properl. Assumption: hen the OR gte is not orking, it is generting 's insted o 's nd vice vers. Tip: irst, generte the truth tle.? Securit comintion: We hve lock tht onl opens hen e set eight (8) sitches s in the igure. Ech sitch represents Boolen vrile. Get the unction tht opens the lock ( logicl '' is generted) hen the sitches re conigured s in the igure. Here, n open lock is represented n LED tht is ON. ON () O () Design logic circuit (simpli our circuit) tht opens lock (= ) henever one presses the correct numer on ech numpd. We encode ech deciml numer on the numpd using BCD encoding. We epect tht ech group o 4 its e in the rnge rom to, the vlues rom to re ssumed not to occur. Tip: crete to circuits: one tht veriies the irst numer (9), nd the other tht veriies the second numer (5). Then perorm the AND opertion on the to outputs. This voids creting truth tle ith 8 inputs!? Numpd SIMPLIICATION O UNCTIONS USING KARNAUGH MAPS Numpd vriles: vriles: m m m m m m m m m m m m m 4 m 5 m m 7 m m m m m m 4 m 7 m 5 = ' + ' = m + m = ' + = '' + '' + = ' + ' = ' + ' 5 Instructor: Dniel Llmocc

6 ECE-78: Computer Hrdre Design Winter 7 4 vriles: m m m m m 4 m 5 m m 7 m 8 m 9 m m m m m 4 m 5 m m 4 m m 5 m m 7 m m m m m 8 m 9 m 5 m m 4 m = ''' + ' + '' = '' + = ' + ' Don t cre outputs X X X = ' = ' Instructor: Dniel Llmocc

7 ECE-78: Computer Hrdre Design Winter 7 PRACTICAL ASPECTS Digitl circuits re nlog circuits! PROPAGATION DELAY t P: Propgtion del. t P t P A A TRI-STATE BUERS Buers: The cn drive more current (e.g.: motors, highpoer LEDs) thn simple logic gtes. A common implementtion uses OPAMPs. A =A A =A' Tri-stte Buers: Z Stte: This is high impednce, hich eectivel mens tht is disconnected rom A. Applictions: Multipleors, Bidirectionl pins, Microprocessor Buses. Emple: Bi-directionl port (4 its): IN_DATA A OE OUT_DATA 4 OE = = Z OE = = A 4 A OE DATA OE = = Z OE = = A OE OE DATA IN_DATA OUT_DATA HAZARDS A digitl circuit cn generte glitches, hich re st spikes, usull unnted. Glitches cused the propgtion dels nd/or the structure o the circuit re knon s hrds. To tpes o hrd eist: o Sttic Hrds: The occur hen the propgtion dels re unlnced. It cn e ddressed dding ll prime implicnts to unction. These hrds hppen hen inputs chnge, ut the output is not supposed to chnge. To tpes:, or. Emple: All gtes hve propgtion del o 5 ns. 5 ns p c n c n q p q 7 Instructor: Dniel Llmocc

8 ECE-78: Computer Hrdre Design Winter 7 o Dnmic hrds: The re cused the structure o the circuit. The re diicult to detect nd ddress. The usull occur in multilevel circuits. To void, use onl to-level circuits nd ensure tht there re not sttic hrds. To tpes:, or. Signiicnce o hrds: o Asnchronous circuits: The re ver vulnerle to hrds nd ill usull render the circuits unusle. o Snchronous circuits: Hrds do not pose prolem here, s e use registers to sel ignore hrds. o Comintionl circuits: Hrds re usull not prolem ecuse the outputs solel depend on the current inputs (s long s the durtion eteen input chnges is greter thn the propgtion del, hich is usull the cse). UNSIGNED INTEGER NUMBERS: BINARY REPRESENTATION BINARY NUMBER SYSTEM Binr numers re ver prcticl s the re used digitl computers. or inr numers, the counterprt o the deciml digit (tht cn tke vlues rom to 9) is the inr digit, or it (tht cn tke the vlue o or ). Bit: Unit o inormtion tht computer uses to process nd retrieve dt. It cn lso e used s Boolen vrile. DIGIT Binr numer: This is represented string o its using the positionl numer representtion: n n CONVERTING A BINARY NUMBER INTO A DECIMAL NUMBER: Positionl numer representtion or inr numer ith n its: Most signiicnt (letmost) it (rightmost) it The inr numer cn e converted to positive deciml numer using the olloing ormul: D = i=n i i = n n + n n i= To void conusion, e usull rite inr numer nd ttch sui : ( n n ) Emple: its: () D = = 4 4 its: () D = = Mimum vlue nd rnge or given numer o its: Numer o its Mimum vlue Rnge n- n- Lest signiicnt n n - n - BIT Mimum vlue or n its: The mimum inr numer is given n n-it string o s:. Then, the mimum deciml numer is given : D = = n- + n = n - n its With n its, e cn represent n positive integer numers rom to n -. The cse n=8 its is o prticulr interest, s string o 8 its is clled te. or 8-it numers, e hve 5 numers in the rnge to 8 - to 55. Most signiicnt (letmost) it Lest signiicnt (rightmost) it 8 Instructor: Dniel Llmocc

9 ECE-78: Computer Hrdre Design Winter 7 CONVERTING A DECIMAL NUMBER (INTEGER POSITIVE) INTO A BINARY NUMBER Emples: Numer in se 5 Numer in se???? Numer in se Numer in se???? 5 Reminder Reminder stop here! Note tht some numers require eer its thn others. I e nt to use speciic it representtion, e.g., 8-it, e just need to ppend eros to the let until the 8 its re completed. or emple: (8-it numer) (8-it numer) CONVERSION O A NUMBER IN ANY BASE INTO A DECIMAL NUMBER To convert numer o se 'r' (r =,,4, ) to deciml, e use the olloing ormul: Numer in se 'r': (r n r n r r ) r D = i=n r i r i = r n r n + r n r n + + r r + r r i= stop here! Also, the mimum deciml vlue or numer in se 'r' ith 'n' digits is: D = rrr rrr = r r n + r n r n + + r r + r r = r n Emple: Bse-8: Numer o digits Mimum vlue Rnge n n n - 9 Instructor: Dniel Llmocc

10 ECE-78: Computer Hrdre Design Winter 7 Emples: (5) 8 : Numer in se 8 (octl sstem) Numer o digits: n = 5. Conversion to deciml: D = = 89 () 4 : Numer in se 4 (quternr sstem) Numer o digits: n = 4. Conversion to deciml: D = = CONVERTING A DECIMAL NUMBER (INTEGER POSITIVE) INTO A NUMBER IN ANY BASE This is generlition o the method to convert deciml Numer in numer into inr numer. or emple, i ou nt to convert se it into se-8 numer, just divide 8 nd group the reminders. Emple: Converting deciml numer to se-8: Reminder Numer in se 8???? stop here! HEXADECIMAL NUMBER SYSTEM This is ver useul sstem s it provides short-hnd nottion or inr numers. A hedeciml digit (lso clled nile) cn tke vlue rom to 5. To void conusion, the numers to 5 re represented letter (A-): Hedeciml digits A B C D E Deciml digits CONVERTING A HEXADECIMAL NUMBER INTO A DECIMAL NUMBER: Positionl numer representtion or hedeciml numer ith n niles (hedeciml digits): Most signiicnt (letmost) nile h n- h n- h h Lest signiicnt (rightmost) nile To convert hedeciml numer into deciml, e ppl the olloing ormul: D = i=n h i i = h n n + h n n + + h + h i= To void conusion, it is sometimes customr to ppend the prei to hedeciml numer: hn-hn- hh Emples: DA9: DA9 5 + D A B87C: B87C 5 + B C The tle presents the mimum ttinle vlue or the given numer o niles (hedeciml digits). Numer o niles Mimum vlue Rnge n n - n - Instructor: Dniel Llmocc

11 ECE-78: Computer Hrdre Design Winter 7 Mimum vlue or n niles: The mimum deciml vlue ith n niles is given : D = = n- + n n- + 5 n = n - n niles With n niles, e cn represent positive integer numers rom to n -. ( n numers) UNITS O INORMATION Nile Bte KB MB GB TB 4 its 8 its tes tes tes 4 tes Note tht the nile (4 its) is one hedeciml digit. Also, one te (8 its) is represented to hedeciml digits. While KB, MB, GB, TB (nd so on) should e poers o in the Interntionl Sstem, it is customr in digitl jrgon to use poers o to represent them. In microprocessor sstems, memor sie is usull poer o since it is determined the numer o ddresses the ddress us cn hndle (hich is poer o ). As result, it is ver useul to use the deinition provided here or KB, MB, GB, TB (nd so on). Digitl computers usull represent numers utiliing numer o its tht is multiple o 8. The st hedeciml to inr conversion llos us to quickl convert string o its tht is multiple o 8 into string o hedecimls digits. The sie o the dt us in processor represents the computing cpcit o processor, s the dt us sie is the numer o its the processor cn operte in one opertion (e.g.: 8-it, -it, -it processor). This is lso usull epressed s numer o its tht is multiple o 8 CONVERTING BETWEEN HEXADECIMAL AND BINARY NUMBERS Conversions eteen hedeciml nd inr sstems re commonplce hen deling ith digitl computers: Hedeciml to inr: We lred kno ho to convert hedeciml numer into deciml numer. We cn then convert the deciml numer into inr numer (using successive divisions). Binr to hedeciml: We cn irst convert the inr numer to deciml numer. Then, using n lgorithm similr to the one tht converts decimls into inr, e cn convert our deciml numer into hedeciml numer. These to conversion processes re too tedious. ortuntel, hedeciml numers hve n interesting propert tht llos quick conversion o inr numers to hedecimls nd vicevers: Binr to hedeciml: We group the inr numers in groups o 4 (strting rom the rightmost it). I the lst group hs eer thn our its, e ppend eros to the let. Then, e independentl convert ech 4-it group to its deciml vlue. Note tht 4 its cn onl tke deciml vlues eteen nd 4 - to 5, hence 4 its represent onl one hedeciml digit, i.e., 4-it group cn represent up to hedeciml digits. The igure elo shos n emple. inr dec he Binr: deciml: hedeciml: Then: Veriiction: = 5D 5 5 D = = 9 5D = 5 + D = A B C D 4 E 5 Hedeciml to inr: It is the reverse process o converting inr into hedeciml numers. We pick ech hedeciml digit nd convert it (ls using 4 its) to its 4-it inr representtion. The inr numer is the conctention o ll resulting 4-it groups. A C A = C = DO NOT discrd these eros hen conctening! Instructor: Dniel Llmocc

12 ECE-78: Computer Hrdre Design Winter 7 APPLICATIONS O BINARY AND HEXADECIMAL REPRESENTATIONS INTERNET PROTOCOL ADDRESS (IP ADDRESS): Hedeciml numers represent compct o representing inr numers. The IP ddress is deined s -it numer, ut it is displed s conctention o our deciml vlues seprted dot (e.g., ). The olloing igure shos ho -it IP ddress epressed s inr numer is trnsormed into the stndrd IP ddress nottion. IP ddress (inr): Conversion to hedeciml: IP ddress (he): 8A54C IP ddress nottion: A 5 4 C Gr pirs o hedeciml numers nd convert ech o them to deciml. The -it IP ddress epressed s inr numer is ver diicult to red. So, e irst convert the -it inr numer to hedeciml numer. The IP ddress epressed s hedeciml (8A54C) is compct representtion o -it IP ddress. This should suice. Hoever, it s decided to represent the IP ddress in 'humn-redle' nottion. In this nottion, e gr pirs o hedeciml numers nd convert ech o them individull to deciml numers. Then e conctente ll the vlues nd seprte them dot. Importnt: Note tht the IP ddress nottion (deciml numers) is NOT the deciml vlue o the inr numer. It is rther series o our deciml vlues, here ech deciml vlue is otined independentl converting ech to hedeciml digits to its deciml vlue. Given tht ech deciml numer in the IP ddress cn e represented hedeciml digits (or 8 its), ht is the rnge (min. vlue, m. vlue) o ech deciml numer in the IP ddress? With 8 its, e cn represent 8 = 5 numers rom to 55. An IP ddress represents unique device connected to the Internet. Given tht the IP ddress hs its (or 8 hedeciml digits), the ho mn numers cn e represented (i.e., ho mn devices cn connect to the Internet)? = devices. The numer o devices tht cn e connected to the Internet is huge, ut considering the numer o Internet-cple devices tht eists in the entire orld, it is ecoming cler tht its is not going to e enough. Tht is h the Internet Protocol is eing currentl etended to ne version (IPv) tht uses 8 its or the ddresses. With 8 its, ho mn Internet-cple devices cn e connected to the Internet? devices REPRESENTING GRAYSCALE PIXELS A grscle piel is commonl represented ith 8 its. So, grscle piel vlue vries eteen nd 55, eing the drkest (lck) nd 55 eing the rightest (hite). An vlue in eteen represents shde o gr. 55 MEMORY ADDRESSES The ddress us sie in processors is usull determined the numer o memor positions it cn ddress. or emple, i e hve microprocessor ith n ddress us o its, e cn hndle up to ddresses. I the memor content is one te ide, then the processor cn hndle up to tes = 4KB. Here, e use its per ddress, or 4 niles. The loest ddress (in he) is nd highest ddress (in he) is. Address : : : 8 its Instructor: Dniel Llmocc

13 ECE-78: Computer Hrdre Design Winter 7 Emples: A microprocessor cn onl hndle memor ddresses rom to 7. Wht is the ddress us sie? I ech memor position is one te ide, ht is the mimum sie (in tes) o the memor tht e cn connect? 8 its Address We nt to cover ll the cses rom to 7: The rnge rom to 7 is kin to ll possile cses ith 5 its. Thus, the ddress us sie is 5 its. We cn hndle 5 tes = KB o memor. : : : 7 A microprocessor cn onl hndle memor ddresses rom to. Wht is the ddress us sie? I ech memor position is one te ide, ht is the mimum sie (in tes) o the memor tht e cn connect? 8 its Address We nt to cover ll the cses rom to : : The rnge rom to is kin to ll possile cses : ith 4 its. Thus, the ddress us sie is 4 its. We cn hndle 4 tes = KB o memor. : A microprocessor hs 4-it ddress line. We connect memor chip to the microprocessor. The memor chip ddresses re ssigned the rnge 8 to B. Wht is the minimum numer o its required to represent ddresses in tht individul memor chip? I ech memor position is one te ide, ht is the memor sie (in tes)? B looking t the inr numers rom 8 to B, e notice tht the ddresses in tht rnge require 4 its. But ll those ddresses shre the sme irst to MSBs:. Thus, i e ere to use onl tht memor chip, e do not need those its, nd e onl need its. We cn hndle tes = 4MB o memor. Address : 8 : 8 : B A memor hs sie o 5KB, here ech memor content is 8-its ide. Ho mn its do e need to ddress the contents o this memor? Recll tht: 5KB = 9 tes. So e need 9 its to ddress the contents o this memor (ddress us sie = 9 its) In generl, or memor ith N ddress positions, the numer o its to ddress those positions is given : log N 8 its A -it ddress line in microprocessor ith n 8-it dt us hndles MB ( tes) o dt. We nt to connect our 5 KB memor chips to the microprocessor. Provide the ddress rnges tht ech memor device ill occup. Address : : : 8 its 5KB Ech memor chip cn hndle 5KB o memor. 5KB = 8 tes, requiring 8 its or its ddress. or -it ddress: e hve 5 hedeciml digits tht go rom to ( memor positions). We divide the memor positions into 4 contiguous groups, ech ith 8 memor positions. The igure shos the optiml o doing so: or ech group, the 8 LSBs o the memor ddresses correspond to the memor rnge o 5 KB memor. And the MSBs o the memor ddresses re the sme ithin group. or given memor ddress, e cn quickl determine hich group it elongs to looking t its MSBs. : 4 : 4 : 7 : 8 : 8 : B : C : C : 4 5KB 5KB 5KB Instructor: Dniel Llmocc

14 ECE-78: Computer Hrdre Design Winter 7 BINARY CODES We kno tht ith n its, e cn represent n numers, rom to n. This is commonl used rnge. Hoever, ith n its, e cn lso represent n numers in n rnge. Moreover, ith n its e cn represent n dierent smols. or emple, in 4-it color, ech color is represented 4 its, providing 4 distinct colors. Ech color is sid to hve inr code. N = 5 smols. With its, onl 4 smols cn e represented. With its, 8 smols cn e represented. Thus, the numer o its required is n = = log 5 = log 8. Note tht 8 is the poer o closest to N=5 tht is greter thn or equl to 5. In generl, i e hve N smols to represent, the numer o its required is given log N. or emple: Minimum numer o its to represent 7, colors: Numer o its: log 7 = 7 its. Minimum numer o its to represent numers eteen 5, nd 9,9: There re 9,9-5,+=497. Then, numer o its: log 497 = its. 7-it US-ASCII chrcter-encoding scheme: Ech chrcter is represented 7 its. Thus, the numer o chrcters tht cn e represented is given 7 = 8. Ech chrcter is sid to hve inr code. Unicode: This code cn represent more thn, chrcters nd ttempts to cover ll orld s scripts. A common chrcter encoding is UT-, hich uses pir o -it units: or most purposes, it unit suices ( = 55 chrcters): (Greek thet smol) = D (Greek cpitl letter Omeg): A9 Ж (Crillic cpitl letter he): 4 4 Instructor: Dniel Llmocc

15 ECE-78: Computer Hrdre Design Winter 7 BCD Code: In this coding scheme, deciml numers re represented in inr orm independentl encoding ech deciml digit in inr orm. Ech digit requires 4 its. Note tht onl vlues rom re 9 re represented here. This is ver useul code or input devices (e.g.: kepd). But it is not coding scheme suitle or rithmetic opertions. Also, notice tht the inr numers () to (5) re not used. Onl out o vlues re used to encode ech deciml digit. Emples: Deciml numer 47: This deciml numer cn e represented s inr numer:. In BCD ormt, this ould e: Deciml numer 58: This deciml numer cn e represented s inr numer:. In BCD ormt, the inr representtion ould e: The BCD code is not the sme s the inr numer! BCD deciml # There eist mn other inr codes (e.g., relective gr code, --- code, -out-o-5 code) to represent deciml numers. Usull, ech o them is tilored to n speciic ppliction. RELECTIVE GRAY CODE: Deciml g g Numer g g g g g g g n- n g n- g n- g g g n- g n- g g n- n- Appliction: Mesuring ngulr position ith 4-it RGC. 4 ems re emitted long n is. When light em psses (trnsprent spots, represented s hites), e get logicl, otherise. The RGC encoding mkes tht eteen res onl one it chnges, there reducing the possiilit o n incorrect reding (especill hen the em eteen djcent res). or emple: rom to onl one it lips. I e used to, to its ould lip: tht ould e prone to more errors, especill hen the ems re close to the line here the to res meet EMITTER RECEPTOR g g g g Angle g g g g 5 Instructor: Dniel Llmocc

16 N inputs ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-78: Computer Hrdre Design Winter 7 COMBINATIONAL CIRCUITS: MULTIPLEXERS (MUXS) This logic circuit selects one o mn input signls nd orrds the selected input to the output line. Boolen equtions or MUX-to-, MUX4-to-, MUX8-to-: s s s N- = s + s n = log N s c d s = s h s s s + 7 s s c + s s d s = s s s + s s s + s s s c + s s s d + Normll, multipleer hs N = n inputs, one output, nd selector ith n its. But, i multipleer hs N inputs, here N is not poer o, the numer o its o the selector is given : log N. MULTIPLEXERS WITH ENABLE An enle input provides us ith n etr level o control. I the multipleer is enled, the circuit orks. I the multipleer is not enled, no input is lloed into the output, nd the multipleer output ecomes (i the output is ctive-high) or (i the output i ctive-lo). The enle input cn e either ctive-high or ctive-lo: ACTIVE HIGH ENABLE E s s c d X X c d E s c d e g 4 5 s s s e + s s s + s s s g + s s s h ACTIVE LOW ENABLE E s s c d X X c d E s LOGIC CIRCUITS WITH MUXs Multipleers cn e used to implement Boolen unctions. The selector cn e thought s the input vriles, the input its re ied vlues tht re pssed onto the output ccording to the selector. This multipleor ith ied inputs implements logic unction. The unctionlit o this circuit is similr to tht o Look-Up Tle (LUT), hich is ROMlike circuit hose vlues re otined ddressing them. PGAs implement Boolen unctions using LUTs. In the emple, -to- LUT is n LUT ith inputs, i.e., it contins = 8 ddresses. s s s unction to e implemented 8-to- MUX s = -to- Look-up Tle s = Instructor: Dniel Llmocc

17 N inputs ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-78: Computer Hrdre Design Winter 7 BUS MULTIPLEXERS Usull e nt input signls to contin more thn one it. In the igure, ech input signl contins m its. This us multipleer cn e uilt m multipleers, ech tking cre o onl one it or ll the inputs. I() I() I(N-) m m m N- m n = log N s I() m- I() m- I(N-) m- N- n I() m- I() m- I(N-) m- N- n m- m- We hve N inputs nd thereore the selector hs n = log N its. Note tht the selector is the sme or ll the multipleers. I() I() I(N-) N- s n = log N DEMULTIPLEXERS A demultipleer perorms the opposite opertion o the multipleer. s s s c d c d s s Appliction: Time Division Multipleing (TDM) Digitl Telephon: (4 KH ndidth) 8 smples per second, 8 its per smple. This requires 4 its per second. In the igure, there re 4 telephone lines (4 signls). To tke dvntge o the communiction chnnel, onl one signl is trnsmitted t time. We cn do this since e re onl required to trnsmit smples o prticulr signl t the rte o 8 smples per second (or 5 us eteen smples, this is controlled counters). ( ( ( ( COUNTER /8 s COUNTER ( ( ( ( 7 Instructor: Dniel Llmocc

18 ECE-78: Computer Hrdre Design Winter 7 DECODERS Generll speking, decoders re circuits tht trnsorm the inputs into outputs olloing certin rule, provided tht the numer o outputs is greter thn or equl to the numer o inputs. Here, e discuss stndrd decoders or hich speciic input/output rule eists. These decoders hve n inputs nd n outputs. We sho emples o: -to-4 decoder, -to-8 decoder, nd -to-4 decoder ith enle. The output i is ctivted hen the deciml vlue o the input is equl to i. n DECODER n DECODER DECODER 8 E X X E DECODER ith 4 enle LOGIC CIRCUITS WITH DECODERS Decoders cn e used to implement Boolen unctions. Note tht ech output is ctull minterm. In the emple, minterm is ctivted hen =, here onl is. Also: 5 is ctivted hen =, 7 is ctivted hen =. unction to e implemented Appliction: Memor Decoding A -it ddress line in processor hndles up to = MB o ddresses, ech ddress contining one-te o inormtion. We nt to connect our 5KB memor chips to the processor. The pink-shded circuit: i) ddresses the memor chips, nd ii) enles onl one memor chip (vi CE: chip enle) hen the ddress lls in the corresponding rnge. Emple: i ddress = 5, onl memor chip is enled (CE=). I ddress = D, onl memor chip 4 is enled. 4 5KB 5KB 5KB 5KB B C Memor spce Memor devices ddress 5 KB 5 KB 5 KB 4 CE CE CE ddress(7..) ddress(8) ddress(9) 5 KB CE 8 Instructor: Dniel Llmocc

19 ECE-78: Computer Hrdre Design Winter 7 ENCODERS Generll speking, encoders re circuits tht trnsorm the inputs into outputs olloing certin rule, provided tht the numer o outputs is loer thn the numer o inputs. Here, e discuss stndrd encoders or hich speciic input/output rule eists. These encoders hve n inputs nd n outputs. The opertion is the opposite o stndrd decoder: i n input i is ctivted, then the inde i ppers t the output (in inr orm). n ENCODER n 4 ENCODER PRIORITY ENCODERS Stndrd encoder: e check hether speciic input is ctivted or the output to hve vlue. Wht hppens hen more thn one input is ctivted? We cn include n etr output tht is ctivted to indicte thn n unepected condition hs occurred. An interesting lterntive is to crete priorit encoder: i more thn one input is ctivted, then e onl p ttention to the input it o the highest order. or emple i =, then e onl p ttention to () = ; i =, e onl p ttention to () =. This results in the olloing truth tle or 4-to- priorit encoder: Wht i no input is ctivted? Here e run out o output its in to represent this cse. Thus, e include n etr output tht it is hen no input ctivted, nd otherise. CODE CONVERTERS PRIORITY ENCODER BCD TO 7-SEGMENT DECODER It is decoder ecuse the numer o outputs is greter thn the numer o inputs The truth tle considers the inputs nd outputs to e ctive-high. c d e g X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X e 4: g 9: : d c 7: : : : BINARY TO GRAY AND GRAY TO BINARY DECODERS It is decoder ecuse the numer o outputs is equl to the numer o inputs. or smll input sies, e cn use the truth tle method. But or lrge input sies (e.g.: 8 its), the olloing circuits re more eicient: g 7 g g 5 g 4 g g g g g 7 g g 5 g 4 g g g g Instructor: Dniel Llmocc

20 ECE-78: Computer Hrdre Design Winter 7 PARITY GENERATORS AND PARITY CHECKERS This is deined in the contet o n error detection sstem ith trnsmission nd reception units. Dt to e trnsmitted: X = n n Trnsmitted strem: Y = n n p, p: prit it Prit deinition: Even Prit: Y hs n even numer o s p e=, otherise Odd Prit: Y hs n odd numer o s p o=, otherise. This deinition is prolemtic since p is not knon. An lterntive deinition, sed on the ctul dt X is: Even Prit: X hs n odd numer o s p e =, otherise Odd Prit: X hs n even numer o s p o =, otherise. Prit Genertor: Circuit tht genertes the prit it sed on the ctul dt X Prit Checker: Circuit tht veriies hether the strem Y hs the correct prit. Emple: or the olloing error detection sstem, X =, n =. The prit genertor nd checker re ls o the sme prit: Even Prit Genertor: It genertes the prit it p e. Odd Prit Genertor: It genertes the prit it p o. Even Prit Checker: It veriies tht the received Odd Prit Checker: It veriies tht the received strem strem Y hs even prit. I so, rp e =, otherise rp e= Y hs odd prit. I so, rp o=, otherise rp o= (to signl (to signl n error) n error) p e =, rp e = p e p o =, rp o = p o Even/Odd Prit Genertor p e p o Trnsmitted its Even/Odd Prit Checker rp e rp o Even Prit Genertor Even Prit Checker Odd Prit Genertor p e p e rp e p o p e rp e p o p o Odd Prit Checker p o rp o p o rp o In generl or X = n n : p e = n n. p o = n n I the # o s in n n-it strem is odd, the n-it input XOR gte ill return, otherise. I the # o s in n n-it strem is even, the n-it input XNOR gte ill return, otherise. rp e = n n p e. We epect the numer o s in Y to e even, n XNOR ill detect this. Hoever, e nt rp e to e hen this does not hppen (to signl n error). Hence, e use n n + -it input XOR gte. rp o =. n n p o We epect the numer o s in to e odd, n XOR ill detect this. Hoever, e nt rp o to e hen this does not hppen (to signl n error). Hence, e use n n + -it input XNOR gte. Instructor: Dniel Llmocc

21 4 ords o its column 5 column column MSBs LUT4 LUT4 LUT4 LUT4 ILUT ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-78: Computer Hrdre Design Winter 7 LOOK-UP TABLES (LUTS) The LUT contents re hrdired in this circuit. A 4-to- LUT cn e seen s ROM ith ddresses, ech ddress holding one it. It cn lso e seen s multipleor ith ied inputs. This is ho PGAs implement logic unctions. A 4-to- LUT cn implement n 4-input logic unction. ILUT() ILUT() ILUT() ILUT() LUT 4 to OLUT 4-to- Look-up Tle (Red-onl memor ith positions) ILUT ddress dt() dt() dt() dt() dt(4) dt(5) 4 dt() OLUT dt(7) dt(8) dt(9) dt() dt() dt() dt() dt() dt() dt() dt() dt(4) dt(5) dt() dt(7) dt(8) dt(9) dt() dt() dt() dt() dt(4) dt(5) OLUT dt(4) dt(5) 4 ILUT LARGER LUTS A lrger LUT cn e uilt uilding circuit tht llos or more ROM positions. Eicient method: A lrger LUT cn lso e uilt comining LUTs ith multipleers s shon in the igure. We cn uild NI-to- LUT ith this method. The igure elo shos the cse or LUT -to- uilt out o to LUT 5-to-. Ech LUT 5- to- is uild out o to LUT 4-to-. NI NI- LUT NI to 4 LSBs ILUT(..) LUT NI to ILUT(4) MUX MUX LUT NI-to- ILUT(5) MUX LUT5-to- OLUT(i) LUT-to- We cn uild NI-to-NO LUT using NO NI-to- LUTs. This cn e seen s ROM ith NI ddresses, ech ddress holding NO its. The igure shos ho LUT -to- is uilt: LUT to its 5 5 LUT to 4 LUT to LUT -to- LUT -to- Instructor: Dniel Llmocc

22 ECE-78: Computer Hrdre Design Winter 7 PRACTICE EXERCISES. Implement the olloing unctions using i) decoders nd ii) multipleers: = X + Y + ZY = (X + Y + Z)(X + Y + Z ) (X, Y, Z) = (m, m, m ). = XY + YZ + XZ (X, Y, Z) = (M, M 4, M 7 ) = XYZ. Using ONLY 4-to- MUXs, implement n 8-to- MUX.. Implement -to- MUX using i) onl NAND gtes, nd ii) onl NOR gtes. 4. Veri tht the olloing circuit mde o out o ive -to-4 decoders ith enle represents 4-to- decoder ith enle. Tip: Crete the truth tle. E 4 E E E E E Using onl -to- MUXs, implement the XOR nd XNOR gtes.. Using onl 4-to- MUX, implement the olloing unctions. (X, Y, Z) = (m, m, m 5, m 7 ). (X, Y, Z) = (m, m, m 5 ) (X, Y, Z) = (m, m 5, m 7 ). (X, Y, Z) = (m 5, m 7 ). 7. Complete the olloing timing digrm: DECODER E E P P s s P Unknon P P P P PRIORITY ENCODER P Instructor: Dniel Llmocc