Cartesius Opening. Jean-Marc DENIS. June, 14th, International Business Director Extreme Computing Business Unit

Transcription

1 Cartesius Opening June, 14th, 2013 Jean-Marc DENIS International Business Director Extreme Computing Business Unit 1

2 Cartesius (Renatus, ) (*) René Descartes (French: [ʁəne dekaʁt]; Latinized: Renatus Cartesius; adjectival form: "Cartesian";[6] 31 March February 1650) was a French philosopher, mathematician, and writer who spent most of his adult life in the Dutch Republic. He has been dubbed the 'Father of Modern Philosophy'. Descartes' influence in mathematics is equally apparent; the Cartesian coordinate system allowing reference to a point in space as a set of numbers, and allowing algebraic equations to be expressed as geometric shapes in a two-dimensional coordinate system (and conversely, shapes to be described as equations) was named after him. He is credited as the father of analytical geometry, the bridge between algebra and geometry, crucial to the discovery of infinitesimal calculus and analysis. Descartes was also one of the key figures in the Scientific Revolution and has been described as an example of genius. Descartes was a major figure in 17th-century continental rationalism, later advocated by Baruch Spinoza and Gottfried Leibniz, and opposed by the empiricist school of thought consisting of Hobbes, Locke, Berkeley, Jean-Jacques Rousseau, and Hume. Leibniz, Spinoza and Descartes were all well versed in mathematics as well as philosophy, and Descartes and Leibniz contributed greatly to science as well. He is perhaps best known for the philosophical statement "Cogito ergo sum" (French: Je pense, donc je suis; English: I think, therefore I am), found in part IV of Discourse on the Method (1637) and 7 of part I of Principles of Philosophy (1644). La Haye en Touraine, the town was the birthplace of the philosopher René Descartes ( ), although his family home was in nearby Chatellerault. Descartes left La Haye in approximately 1606 to attend the College Henri IV at La Fleche. The town was renamed La Haye-Descartes in 1802 in his honor, and then renamed again to Descartes in (*) 2

3 Cartesius (SurfSara, 2013 ) Phase 1 (2013) 271 TFlops 572 compute nodes GB memory 1071 TiB storage IB FDR 3

4 Phase 2 (2014) Tflops (x5) compute nodes (32 Fat & 1620 Thin) (x3) GB Memory (x2,5) TiB storage & 202 GB/s (x7) IB FDR (no change) 4

5 Courtesy AIRBUS France/IESP Why ExaScale Computing? Oil & Gas: better resource detection flops ,5 0,1 Complexity of algorithm Visco-elastic FWI Petro-elastic inversion Elastic FWI Visco-elastic modeling Isotropic/anisotropic FWI Elastic modeling/rtm Isotropic/anisotropic RTM Isotropic/anisotropic modeling 50 TF Paraxial isotropic/anisotropic imaging (50x10 12) Asymptotic approximation imaging PF (10 16) 1 PF (10 15) Industrial challenges in oil and gas: depth imaging roadmap courtesy IESP Oil reservoir discovered Unclear image Non-significant image Aircraft: complete multi-physics simulation Human brain project Capacity: # of Overnight Loads cases run 10 2 Unsteady RANS LE S Available Computational Capacity [Flop/s] 1 Zeta (10 21 ) RANS High Speed RANS Low Speed Smart use of HPC power: Algorithms Data mining Knowledge 1 Exa (10 18 ) 1 Peta (10 15 ) 1 Tera (10 12 ) 1 Giga (10 9 ) 10 6 HS Design Aero Data CFD-based Optimisation Set LOADS Full MDO & CFD-CSM & HQ Capability achieved during one night batch CFD-based noise simulation Real-time CFD-based in flight simulation 5

6 (Some) Exascale challenges 1,000 x30 PFlops 30 1 x

7 Addressing the Exascale Challenges Optimize system Power Consumption (minimize PUE) Develop new HPC processors Fix the Memory wall TeraBytes Bandwidth Terabit interconnect (optical links everywhere) Non-Volatile Memory (NV-RAM) storage and fast memory SW complexity: manageability, programming models 7

8 Bull focus for ExaScale Computing Power Consumption Exponential increase in number of cores 100 millions of cores In 2011, 50% of CIO claimed that none of their compute tasks did use more than 120 cores #cores MWatts x20 20MW 1MW 1 PF PF 2020 FLOPS x1000 Average number of cores per supercomputer (Top 20 of Top500) 2020 exaflops 8

9 Bull research program for ExaScale Computing Power Consumption PUE optimization Down to 1 + ε (very) hot water Adiabatic Computer room Cogeneration No wasted energy. Any piece of heat is re-used Supercomputer management Power monitoring tools Use the right HW for the right app Application optimization Save (a lot) on energy consumption with (very) limited performance degradation Opportunities for Collaborations Exponential increase in number of cores SW stack OS Communications (MPI but not only) Batch Affinity (cpu/mem/node/ ) Data management (filesystems) Overpass current interconnect limitations Topology (ies) RDMA mechanisms Latency at large Scale Programming model (many) different programming models: MIMD+SIMD Languages Reliability MTBF close to zero automatic recovery mechanisms 9

10 Manageability at ExaScale The processor is the new transistor" (Chris Rowen) MPI, OpenMP, Threads, Cuda, OpenCL,... Message passing, shared memory Locality Raise level of abstraction Set of compute resources Parallelism based compute resources New high level programming languages Optimize compute environment Describe key characteristics of applications Elect the most appropriate set of node types Manage resources with heuristics predicting the future workload Migrate Processes Resource fragmentation reduction Hardware failures Prediction Allow dynamic application frameworks Automatic application loadbalancing Meshes refinement optimization Restart lost processes in case of failure 10

11 Programmability at ExaScale Parallelism / Concurrency is easy to apprehend but much more complex to express in an application program Distribute task and data to operate on Old SMP approaches (bulk parallelism à la OpenMP) making a come back (cf MIC) Old SIMD approaches (bulk parallelism à la CM2/CM5) making a come back (cf CUDA) At Highest level Message passing (MPI-3) Data decomposition With increasing degree of parallelism hierarchical approach is necessary 11

12 2020 exascale downscale to departmental and Embedded computing SME s computing By Pflops in a rack PetaFlop system (2012) ExaFlop / data center (2020) - TFlops in a chip Number of nodes [3-8],000 [50-200],000 (10x) Computation 1 PetaFlop 1 ExaFlop (Flops & Inst.) (1000x) Memory Capacity [1-2]00 TB > 100 PB (B) (1000x) Global Memory [2-5] 00 > 100 PB/s BW (B/s) TB/s (1000x) Interconnect [5-10]0 ~50 PB/s bisection BW TB/s (1000x) Storage Capacity [1-10] PB >1 EB (B) (1000x) Storage BW (B/s) [10-500] > 10 TB/s GB/s (1000x) IOP/s 100,000 > 100 M (1000x) Power Cons. [.5-1.] MW < 20 MW (W) (20x) PetaFlop/ departmental (2020) TeraFlop / embedded (2020) [50-100] 1 1 PetaFlop 1 TeraFlop > 10^14 > 10^11 > 100 TB/s > 100 GB/s ~10 TB/s N/A >1 PB > 1 TB > 10 GB/s > 10 MB/s > 100,000 > 100 < 20 KW < 20 W 12

13 Cogito Ergo Sum Computa Ergo Sum 13

14 Cogito Ergo Sum Computo Ergo Sum 14

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